SU920556A1 - Digital meter of period length - Google Patents

Description

one

The invention relates to a radio metering technique, is intended to measure the period of harmonic signals and can be used to create precision frequency measurement systems.

A period measurement device is known comprising a reference frequency generator and decadal dividers of the supports. frequency, shaper, selector, electronic counter, shaper, decadal dividers of the measured frequency and the circuit for the formation of the counting time l.

The disadvantage of this device is the relatively high measurement error in the study of the period of the signals that have passed through various conversion devices (receivers, frequency comparators and others), the internal noise of which introduces spurious phase modulation of the signal being analyzed, leading to a measurement error of the period.

The closest in technical essence to the invention is a period meter comprising a driver, elements AND, trigger, reference frequency generator, frequency divider, electronic counter, one-shot, trigger-and selector 2.

However, in this device there is a significant error in measuring the period of the signals

10 past various kinds of converters, as well as a measurement error due to a shaper, generating a rectangular voltage from a sinusoidal signal, and the noise of which leads to fluctuations of the edges of the measured signal.

The purpose of the invention is to improve the accuracy of measuring the duration of the period.

20

The goal is achieved in that the device containing the reference frequency generator has the first And element, the first input of which is connected through the driver to the input bus of the device, and the output is connected to the first trigger input, the second And element, the output of which is connected to the divider input frequency, time indication generator, the output of which is connected to the counter reset input, additionally introduced a combinational decoder, adder memory register, zero decoder, OR-NOT element, Nil formers, N-1, triggers and N-1 elements And the first inputs of which are connected via an additional driver to the input bus of the device, and the outputs are connected to the first inputs of additional triggers, the outputs of the triggers are connected to the inputs of the combinational decoder, the outputs of which are connected to the first inputs of the summator, the second inputs of which are connected to the outputs of the register memory, the synchronization input of which is connected to the output of the pulse generator of the reference frequency and with the second inputs of the AND elements, and its information inputs are connected to the outputs of the adder, the output with the transfer signal of which is connected to the counter input of the counter while the inputs of the element OR are NOT connected to the outputs of the drivers, and the output is connected to the first input of the second element AND, another input of which is connected to the output of the memory of the display time body, the input of the the indication time gate is connected to the zero decoder output and to the second trigger inputs, and the zero decoder input is connected to the output of the frequency divider. FIG. 1 shows a structural diagram of the device in FIG. 2 - time diagrams of signals at various points of the device. The digital period duration meter (Fig. 1) contains drivers 1, elements I2, generator 3 pulses of the reference frequency, trigger, element OR NOT, element 6, decoder 7 zero, frequency divider 8 combinational decoder 9 adder 10, register 11 memories , shaper 12 of indication time, counter 13. The device operates as follows. 9 4 Before starting operation, counter 13, memory register 11 and frequency divider 8 are in the zero state. From the output of the decoder 7 zero to the information inputs of the triggers. the zero potential arrives, which, under the action of the sync pulses passing to the output of the I2 elements in the period of presence at the second inputs of the I2 elements of positive pulses from the outputs of the corresponding formers 1, sets the triggers to the zero state. In this case, the combinational decoder 9 generates at its outputs a binary zero code supplied to the inputs of the adder 10. The second inputs of the last output from the memory register 11 also receive a zero code, therefore for each clock pulse from the generator 3 output reference frequency input to the register clock input 11, the summation of the zeros in the adder 10 occurs, the transfer signal does not occur at the output P, and the counter 13 remains in the initial state. The input signal, the period of which must be measured, is fed to the inputs of the formers 1, which form a rectangular voltage from a sinusoidal signal, the fronts of which due to parasitic phase modulation due to noise of the conversion units and the formers themselves, fluctuate around the average value. determined by the moment of transition of the signal under study through the zero level. Moreover, with the independence of the noise of the conversion units and shapers, fluctuations in different channels can be considered uncorrelated. From the outputs of the formers 1, the pulse signals (fig. 2a, b, c, d) are fed to the inputs of the element OR-NOT 5, at the output of which a pulse voltage is formed (fig. 2e), the negative front of which is determined by the positive front of the signal from the output of one of formers 1, which works before the others. Through the IB element, the pulses from the output of the OR-NOT 5 element are fed to the input of the frequency divider 8, which changes its state along the negative front of the input signal. Consequently, at the output of the decoder 7 zero, the potential of a single level (Fig. 2e), which is fed to the information inputs of the flip-flops 4, is formed along the positive front of Togo from the formers 1, which worked before the others. At the same time, the signals from the outputs of the formers 1 are fed to the inputs of the corresponding I2 elements, to the second inputs of which pulses are output from the generator 3 of the reference frequency pulses (Fig. 2 g). The moment of occurrence of pulses at the output of the element JOB I2 is determined by a positive signal front from the output of the corresponding former 1. Because of the fluctuation of the fronts of the pulsed direction or formers 1, the appearance of pulses at the outputs of the elements I2, and, consequently, at the inputs of the trigger synchronization h (fig. 2z, and, k, l) is a random process. Here, it is considered that the period duration of the signal of the reference frequency generator TQ is less than or equal to the mean square value of the fluctuation of the fronts at the output of the driver 1, i.e. TO. (;, Since only in this case the error due to parasitic phase modulation is reduced. Since the formation of the potential of a single level at the information inputs of the flip-flops C (Fig. 2e) is determined by the signal front of the former 1, which triggered first, and the appearance at the inputs synchronization of the flip-flops Q pulses from the outputs of the I2 elements (Fig. 2z, and, k, l) is determined by the signal front from the corresponding generator 1, then the installation of the flip-flops in one state is also a random process (Fig. 2m, n, o, p). Let the first m Oment of time to the unit state transition N triggers, Combination decoder 9 analyzes the outputs of all the triggers 4 and n (equivalent to the number in the binary code, which goes to the first inputs of the adder 10. Now for each generator pulse 3 reference frequency pulses fed to the synchronization input of register 11 of memory, the number N is added to the content of the last. Adder 10 sums the numbers modulo N and the signal nepeHotd from the output P goes to the counting input counter1 / | ka 13- Suppose that before the second group of triggers triggered, the generator k p 3 pulses of the reference frequency developed p.4 quantizing pulses. Then the number registered 66 in the memory register 11 and the counter 13 is N p. If we denote by -ti the number of flip-flops 4, which went into one state after the triggering 13 of the second group of flip-flops 4, and n the number of quantizing pulses produced by the generator 3 pulses of the reference frequency from the moment of triggering the second group of triggers to the moment of transition to the one state of the third group of triggers k, the number registered; in the counter 13 and the memory register 11, is N | n + N202- It is obvious that the total number registered in the memory register 11 and the counter 13 at the time of the operation of all N-flip-flops 4 is expressed. jl nini where K is the number of groups simultaneously triggered by the trigger t. After all N triggers t go into unit state, the code N is set at the output of combinational decoder 9, which for each pulse of the generator 3 pulses of the reference frequency is summed with the contents of register 1} memory modulo N, and the transfer signal from the output P of the adder 10 is calculated counter 13- Therefore, the total registered number is expressed as I rtf P-, + N: -no: where n is the number of quantizing pulses produced by the generator 3 pulses of the reference frequency during the time all triggers k are in one state (i.e. The frequency divider conversion factor for the frequency divider 8 is determined by the number of averaged periods of the signal under investigation, which, in turn, is chosen based on the required measurement time Tj-j. After setting the frequency divider 8 to zero, which occurs at the end of the cycle his work, on the positive front of the signal from the output of one of the formers 1, which worked before the others, the 7 deiftimator forms a zero potential at its output, and, consequently, at the information inputs of the triggers 4. Due to the presence of parasitic phase modulation, leading to fluctuations of rectangular voltage fronts at the outputs of the formers 1, the appearance of pulses on the outputs of the I2 elements (Fig. 2c, and k, l) and, consequently, resection of triggers into The zero state (Fig. 2m, n, o, p) is a random process. Therefore, by analogy with the beginning of the measurement time interval, it is possible to write the expression for the number registered in memory register 11 and the counter- 13 since the formation of the zero level potential at the output of the decoder 7 zero defined by the front of the driver 1 that triggered

-Njn. J where Mj is the number of flip-flops C remaining in the single state after zeroing the j-th group of flip-flops, P1 is the number of quantizing pulses produced by the generator 3 pulses of the reference frequency between the zeroings of the j-th and (j + 1) -th group flip-flops k, t - the number of groups simultaneously

zeroed flip-flops k. After the transition to the zero state of all N flip-flops k, an O code is applied to the first inputs of the adder 10 from the output of the combinator 9, and the increase in the contents of memory register 11 and counter 13 stops. In this case, in the register 11 of the memory and the counter 13, a number proportional to the measured period of the signal being analyzed is recorded, i.e.

To tn Mostly, lHtn-,. f

-

f

The average value of the measured time interval equal to N periods of the analyzed signal is defined as

T JC g5 t Mo. t Lbsch - -2. L, then Y

m

1 n: Toi

i

Consider the first term in expression (2) and find the limit to which it tends, with and TQ- 0. Obviously, in this case, the product njTo goes into a continuous random variable t, which characterizes the fluctuations of square fronts at the outputs of the formers 1, the ratio N {N becomes the probability density (jL) (ty) of the random variable t, and

the sum is replaced by an integral, i.e.

f GS I

tL-m. Е niTo -5tv

- jq 00 tM N. “0 V,

(dt J MtloV-to. ()

Similar reasoning with respect to the third term in the expression (2 allows to write

I-g MJ-Ch I jbTT-it ,,.

Eim

 J - 1 TO- O

u) (t;) dt, c)

Here t (j and tg are mathematical x Khitani, respectively, of the beginning and end of the measured time interval. Consequently, with Td-y O, we have an estimate of the measured time interval with the steering dispersion, with final N and TO, and the strength of the independence of the fluctuation of the phase in different channels, we obtain an estimate of this interval with a variance reduced by N times compared with the estimate obtained using single-channel period meters in known devices-x. Indeed, the random error in measuring the period of the signal under investigation is due to azit phase phase modulation is determined by the fluctuations of the square fronts of the formers 1 at the beginning and at the end of the measurement time interval, i.e.

,

2. - the variance of the measurement error of the time interval equal to N periods of the input signal by the single-channel method; J and S, respectively, dispersion of phase fluctuations of the beginning and end of the measured interval. When using the multi-channel method used in this device, we have. r.6HtaK- 1G i. the use of this device allows one to reduce the rms measurement error due to the parasitic phase modulation in H | Graz. The display time generator 12 is controlled by a signal from the output of the decoder 7 zero and generates a signal that prohibits the signal from going through the Ib element to the fixation time. Measurement results in memory register 1 1 and the counter 13- After the inhibit signal from the output of the display 12 time indicator , the latter generates a pulse, zeroing memory register 11 and counter 13. In this case, the inhibitory potential is removed from the input of the IB element and the measurement cycle repeats. Thus, the use of the proposed device allows the period measurement error due to parasitic phase modulation during the passage of the analyzed signal through the formers, which is achieved by introducing additional formers, AND elements, triggers, OR-NOT element, combination decoder, display time generator, zero decoder, adder, and a memory register that simultaneously measures the period of a signal that has passed several concurrently working identical building blocks. At the same time, random phase fluctuations in each channel are averaged, and the measurement result is accumulated in a single counter.

Claims (2)

 DETAILED DESCRIPTION OF THE INVENTION A digital period duration meter comprising a reference frequency generator, a first And element, the first input of which is connected via a driver to an input bus of a device, and an output connected to the first trigger input, a second And element, the output of which is connected to an input of a frequency divider, a display time generator, the output of which is connected to a counter reset input, characterized in that, in order to improve accuracy, a combinational decoder, adder, memory register, deshi are additionally introduced into it the zero climber, the element OR-NOT, Mt1 drivers, N-1 flip-flops and elements AND, the first inputs of which are connected via additional drivers to the input bus of the device, and the outputs are connected to the first inputs of additional triggers, and the outputs of the trigger connections to the inputs of the combiner decoder The outputs of which are connected to the first inputs of the adder, the second inputs of which are connected to the outputs of the memory register, the synchronization input of which is connected to the output of the reference frequency pulse generator and to the second inputs of the And elements, its information inputs are connected to the outputs of the adder, the output of the transfer signal of which is connected to the counting input of the counter, while the inputs of the OR-NOT element are connected to the outputs of the drivers, and the output is connected to the first input of the second element AND, the second input of which is connected to the reset inputs of the memory register .and with the output of the display time generator, the input of which is connected to the second a.drops of the triggers and to the output of the zero decoder, the input of which is connected to the output of the frequency divider. -. Sources of information taken into account in the examination 1. Equipment for frequency and belt measurements. Under A.P.Gorshkoa, M., Soviet Radio, 1971. 169. 2. Ermolov R.S. Digital frequency response. L., Energie, 1973, p. jriiiilliiiiiiritniiitiiiiiiiiiiiiiiMb, iiitrnnnnitiitiiiini MHIIHIttllllllHUiil riHtiimiiiiniiiiiiiniitnun 2.