SU1667053A1 - Logarithmic code adder - Google Patents

Abstract

The invention relates to computing and can be used in the construction of universal and specialized digital computers. The aim of the invention is to simplify the adder. The adder contains the element AND 2, the element OR - NOT 3, the element EXCLUSIVE OR 4, the first and second blocks 5 and 10 subtraction, the first and second multiplexers 6 and 7, block 11 addition, block 12 elements AND - OR, the first and second blocks 13 and 14 permanent memories with communications. 1 il.

Description

The invention relates to computing and can be used in digital computers in the processing of radar signals, the solution of problems of recognition.

The aim of the invention is to simplify the adder.

The drawing shows a diagram of the adder logarithmic codes.

The adder contains the input 1 of the first term adder, the element And 2, the element OR NOT 3, the element EXCLUSIVE OR 4, the first block 5 subtraction, the first and second multiplexers 6 and 7, the input 8 of the second term adder, the output 9 of the sign of the adder, the second block 10 subtracting, an add-on unit 11, an AND-OR element block 12, the first and second blocks 13 and 14 of the permanent memory, the output 15 of the attribute of the adder, the output 16 of the sum of the adder, the output 17 of the overflow of the adder.

The adder of logarithmic codes is designed to add two numbers with the same characters, represented in logarithmic codes. Logarithmic

the code of some number at is xi (092tail. Since 0 lai | 1, then 0 xi is -1od2J, where is the digit of the number a. The logarithmic code xi has the following format

sign z kik2,

where the sign of the number ai is written in the one-bit field sign, code 1 is written in the one-bit field z, if ai 0, the entire part Iog2 lai I is written in the field ki having 1dalg bits, the fractional part Iog2 is written in the field K2 jail With 4, K2 15 and the logarithmic code x 1 is 21 bits. The sign Iog2 lail is always negative and therefore not recorded.

The adder works as follows.

Let it be necessary to find the sum B ai + 32. The logar codes of the numbers ai and az come to the inputs of device 1 and 8. It is necessary to find the logarithm code of sum B

2 ° 92V 2l ° gai j 21A9a2

Choose max (logai, Ioga2). Let logai ioga2. Then

2l ° 92B f - + 2lo9a2 logai 2loga1 (1).

Yo

ABOUT

about

J

about

ate with

From where

IOQ2B 109231 + IOQ2 (1 +).

The sign zi of the first addendum goes to the first inputs of the AND 2, OR-NOT 3 and EXCLUSIVE OR 4 elements. The whole and fractional parts of the Iog2 lai I code, supplemented with the sign, are fed to the input of the decrementing subtraction unit 5. Code Iog2 lai I is fed to the first input of the multiplexer 6 and the second input of the multiplexer 7.

The sign Z2 of the second addendum enters the second inputs of the AND 2, OR-NOT 3, EXCLUSIVE OR 4 elements. The whole and fractional parts of the Iog2 Ia2l code, supplemented with a sign, are input to the subtracted subtraction unit 5. The Iog2 1321 code is fed to the second input of the multiplexer 6 and to the first input of the multiplexer 7. The sign of the number from the input 1 passes to the output 9 of the adder.

In block 5 subtraction, the difference Iog2ai - 1 2 2 E 2 is formed. If the difference sign is zero, then Iog2ai is 1od2E2, and vice versa. Therefore, max (Iog2ai, 1od2E2) is formed at the output of multiplexer 6., and 7 mln (Iog2ai, Iog232) is output at multiplexer output. From the outputs of multiplexers 6 and 7, the values are fed to the inputs of the subtracted and decremented block 10, at the output of block 10, the difference is formed - C, which contains ki integer bits and n fractional, m most significant bits (- Ci) of this difference the inputs of the memory block 13, 2 subsequent bits (- C2) are fed to the address inputs of the memory block 14.

At the first output of the memory block 13, a function is formed.

goTs1od2 Iail, log2 Ia2) -max (fog2 Iall, log2 lajl)

log2 (1 + 2)

-Iog2 ()

At the second output of the memory block 13, a Pi-bit function 2-ci is formed.

1 + 2

-C1

At the output of memory block 14 forms, -c.

c value

C2.

At the output of the sum of block 11 of addition, the value of log2B Iog2ai + is formed

+ 1od2 (1 + 2 C1) + - C2. Esl1 r2 0,

1 + 2 с1

this value passes through block 12 of the AND-OR elements to output 16. If one of the signs of zi or Z2 is 1, then in the kika bits of the corresponding number the minimum possible number 0000, 00 ... 00-1000.00 ... 00 is written -16 (at).

The number having z M will be large and through the block 12 elements AND-OR will pass to the output 16. If zi Z2 1. At the output 15 the result sign is formed

z 1. Output 16 will generate the minimum possible number.

The sign of the overflow of the discharge grid V is read from the inverse output of the sign bit of the block 11 of the

0 arrives at output 17. For k 15, it is convenient to have m 11, Pi 5, g 5, the adder's bit width equal to 22. Then the error of the adder of logarithmic codes does not exceed 2.

5 An additional positive effect of the invention is to increase speed.

Claims (1)

Claims adder logarithmic codes, containing the element AND, the element EXCLUSIVE OR, the first subtraction unit, the first and second multiplexers, the addition unit, the first and second permanent memory blocks, and the output of the sign of the first unit 5 is connected to the control inputs of the first and second multiplexers, the output of the first multiplexer is connected to the input of the first addendum block, characterized in that 0 simplify the adder, it contains an OR-NOT element, the second subtraction unit and the AND-OR element block, and the input of the discharge of the sign of the input of the first term of the adder is connected to the first inputs 5 of the element AND, the element OR NOT and the element EXCLUSIVE OR, the input of the bit of the sign of the input of the second term of the adder is connected to the second inputs of the element AND, the element of OR-NOT and the element of the EX key0 OR, the output of the element of AND is the output of the sign of the adder the sign of the input of the first term of the adder is the output of the sign of the adder, the inputs of the information bits and the input of the discharge The 5 characters of the input of the first adder are connected respectively to the inputs of the input of the decremented first subtraction unit, the inputs of the input bits of the subtracted which are connected respectively to the inputs of the information bits and the input of the character of the input of the second term of the adder the adder components are connected respectively with the inputs of the bits of the first and second information inputs of the first multiplexer, the second and first information inputs of which are connected respectively with the first and second information inputs The second multiplexer, the output of which is connected to the input of the decremented second subtraction unit, the input of the subtracted which is connected to the output of the first multiplexer and the first input of the first group of the block of AND-OR elements, the output of which is the sum totalizer output, the overflow output of which addition, the outputs of the high and low bits of the output of the second subtraction unit are connected respectively to the address input of the first block of the permanent memory and to the first address block the input of the second constant memory unit, the first and second outputs of the first permanent memory unit are connected respectively to the input of the second term of the addition unit and the second address input of the second permanent memory unit, the output of which is connected to the input of the third addendum unit, sum output which is connected to the first input of the second group of the AND-OR element block, the outputs of the EXCLUSIVE OR element and the OR-NOT element are connected respectively to the second inputs of the first and second groups of the AND-OR element block. t WG R.2. 14 j