SU1536392A1 - Device for interfacing computer and peripherals - Google Patents

Abstract

The invention relates to automation and computer technology and can be used for organizing communication controllers in multiprocessor systems, subscriber stations and terminal complexes, as well as control devices for workstations of users of automated control systems. The aim of the invention is to extend the functionality by increasing the nomenclatures of the connected external devices. The device contains a firmware control block, a memory block, three switches, five registers, a shift register, a control trigger, a switching trigger, a pulse generator, two single vibrators, three OR elements, three I. elements. 1 Il.

Description

The invention relates to automation and computing technology and can be used for organizing communication controllers in multi-microprocessor systems of subscriber stations and terminal complexes, as well as control devices for workstations of users of automated control systems.

The aim of the invention is to expand the functionality of the device by increasing the range of connected external devices,

The drawing shows a block diagram of the device.

The device contains the first switch 1, the group of information inputs 2, the group of information inputs 3, the group of the inverter 4, the first element OR 5, the input 6 of circulation, the trigger 7 switching, the second. element OR 8, setup input 9, second AND 10 element, microprogram control unit 11, second switch 12, second register 13, output group 14-17, third register 18, first register 19, first element AND 20, shift register 21, third the element 22, the pulse generator 23, the control trigger 24, the second single vibrator 25, the third element OR 26, the first single vibrator 27, the fourth register 28, the third switch 29, the memory block 30, the decoders 31, 32 ,. the encoder 33, the fifth register 34, uses an associative drive as the memory unit 30.

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The device operates in two main modes, providing respectively maintenance of the call from the computer processor to the external device (HL) of the N-th type (1 mode) and the call from the WU to the processor (II mode). In case of coincidence in the time of receipt of requests on I and II modes, the device processes the request for I mode.

The operation of the device begins with the initial installation. The signal at input 9 of the device through the OR element 8 sets the switching trigger 7 to one state, thereby switching the switches 1.12 to mode II (i.e., connecting to switch 1 the control bus VU on inputs 4 of the device and the information bus VU through the inputs 3 of the device, and to the switch 12, the control bus of the computer via the outputs 15 of the device and the input information bus of the computer through the outputs 17 of the device).

Consider mode II operation of the device. At inputs 3, the character code from the alphabet of the N-th slave enters and sets on the second group of information outputs of switch 1. One of the 4 N inputs receives the N-HI inverter signal. The unit on the second control input of the switch 1 blocks the installation of information on its first group of outputs. The signal from the H-th input 4.H through the element OR 5 and the one-shot 25 sets to 1 control trigger 24, thereby connecting to the circuit through the element And 22 a pulse generator 23, and a clock signal arrives at the synchronous input of the shift register 21. The first bit of register 21, which had a state of 000 ... O at the start of operation of the device, is set to 1. Setting 1 to trigger 24 leads to compression through an And 10 element of the enable signal on the third control input of switch 1, thereby blocking switching to the outputs of the switch 1 of whatever information from its inputs. At the first input of the element AND 10, a single potential is left from the output of the microprogram control unit 11, which generates this signal in the inactive state.

The signal from the unit output of the first bit of register 21 is fed to

0

five

0

five

0

five

0

five

0

five

input to the register 18, allowing 1 reception of a code from the second group of information outputs of switch 1. This signal also goes to the second input of the element I 20, however, a single signal at the output of this element allowing the reception of a code on register 19 with the first group of information outputs of switch 1, It is not formed due to the absence in this mode of operation of the device at the first input of the element I 20 (trigger 7 is set to 1).

At the end of the described actions, the next control signal from the generator 23 enters the sync input register 21, as a result of which its contents shift by 1 bit to the right and the second bit of register 21 is set to 1. The contents of register 21 are added to the left with zeroes.

The control potential from the unit output of the second bit of register 21 is fed to the read input of register 18, as a result of which the code from this register 18 is fed to the first group of information inputs of the switch 29. At the same time, this potential is applied as the first control input of the switch 29, allowing switching code from the register 18 to the information inputs of block 30, and the recording input of block 30, defines the write operation in block 30 on the basis of, At the same time, a single signal from the second bit of register 21 blocks the operation of the encoder 33, register 34 and a decoder 32, being at the same time permitting operation of a signal arriving at the control input of the decoder 31 and the record entry of the register 28 (permission to receive the code). In the absence of an enable signal, the operation of the decoder 31 and register 28 is blocked.

The logically associative drive (memory block) 30 is divided into K + 1 zones of equal length, in the cells of which, beginning with the second, the characters of the computer alphabets and K of the control unit are grouped. The first cell of each zone contains the address of the corresponding slave unit (or computer in the computer zone). There is an unambiguous positional correspondence between the characters in the cells of the computer and the computer zones, i.e. the corresponding characters in the alphabets of the computer and the VU are written in cells, occupying the same position relative to the boundaries of their own. zones.

During the operation, writing to the memory (control signal at the input of the record-block 30) can be recorded into the cell of the block according to the coincidence of information in the cell and the sign received through the information inputs of block 30. When performing an operation read from the memory (control The reading signal of the block 30) is accessed by one of the zones of the block, the choice of which is determined by the coincidence of the sign coming through the information inputs of the block and the information in the first cell of the H-th zone of the block 30. Readable from the H-th zone H -. the cell is determined by

by setting the mask bit register (in this case, register 28), the code from the outputs of which is received in the event of a read operation simultaneously with the code of the attribute to the information inputs of block 30. The number of bits in the mask register (register 28) is equal to the number of cells in any of the zones of the block thirty.

Thus, on the information; the inputs of block 30 in the recording mode receives a character code from the alphabets of the N-th slave. In accordance with the slave logic, the block 30 at the address outputs of block 30 is the absolute cell address of block 30, containing the code of this symbol. This address is fed to the inputs of the controller 31, which implements the following system of functions:

The inputs of the decoder 31 (ltDlog2 (K + 1) (M + 1) D

12

m

M + 2 m + 3

2М + 1 2М + 3 2М + 4

ZM + 2

 - the address code is presented in the 10th number form; M - the number of characters in the alphabets WU, computers; K - the number of slaves.

Codes About, M + 1, 2M + 2, etc. are not considered, since they can not enter the inputs of the decoder 31 due to the fact that the cells with these addresses contain the codes of the signs — the address of the drive or the address code of the computer.

Thus, the decoder 31 is an incomplete decoder. The position of the bit in the code

Decoder Outputs 31 1 tM

0100 ... 00 0010, .. 00

0000 ... 01 0100 ... 00 0010 ... 00

0000 ... 01 0100 ... 00 0010 ... 00

0000 ... 01

formed at the outputs of the decoder 31, determined by e-t the relative position of the cell 5 containing the received symbol, relative to the boundaries of the zone N-th WU. The code from the outputs of the decoder 31 is taken to register 28.

At the end of the described actions on the synchronous register 21 receives a shift signal from the generator 23,

as a result, its contents are shifted by one more digit to the right and the third digit of register 21 is set to 1.

As a result, the second control input of the switch 29 receives a signal determining the switching to the information inputs of the information output section 30 of the register 19 and register 28. The control signal also arrives at the reading input of the block 30, thereby determining the execution of the reading operation on the basis. The input of the record of register 13 receives a signal permitting the reception of a code to this register La, a register reading input 28 and a register input 19 (via the OR 26 element) receive control signals to issue a code. As a result, the codes from register 19 and register 28 through switch 29 are fed to the information inputs of block 30.

In the first cell of the zone, the computer in block 30 contains the code 000 .. D) 0, which is thus a sign of the computer zone. Consequently, under the influence of the described control signals and received at the corresponding inputs of block 30, the codes at the address outputs of block 30 appear cell address of the block containing the character from the alphabet that corresponds to the character from the alphabet of the H-th VU that arrived at the device inputs in this session of its operation.

Due to the absence of a blocking signal at the control inputs of the encoder 33, register 34 and decoder 32, this address is already decrypted to the address inputs of block 30, and as a result, the first information outputs of block 30 receive the character code from the computer alphabet corresponding to the code of the received symbol from the alphabet of the H-th VU, and is accepted on register 13,

Next, the sync input of register 21 receives the next clock signal from generator 23, and 1 sets the fourth bit of this register. As a result, the read input of register 19 sends a signal to issue a code, and a signal is released to enable the microprogram control unit 11, disrupting the operation of the unit, and the input coder 27 also receives a single signal

0

five

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five

0

five

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five

At this step, the control inputs of the switch 29 do not receive any signals, i.e. its operation is blocked and the code from the outputs of the register 19 is fed only to the inputs of block 11,

Block 11 is a firmware control block. The code that arrives at a given device operation cycle for a group of inputs of the logic condition of block 11 is the address of the first microcommand of the microprogram of accessing the computer (in mode II) or in the 11th type of VU (in mode I). The receipt of the code (including the code 000,4.00) simultaneously with the enabling signal at its permitting input initiates the operation of the block

11, and it generates a sequence of control codes, which through the switch 12 enters the control bus of the computer through the outputs 15 of the device. Simultaneously with the first micro-command for implementing the WU-computer dialogue, the symbol code in the computer alphabet corresponding to the character received from the N-th WU is transmitted to the information bus of a computer through the device outputs 17. This occurs as a result of the passage of the control signal through the one-shot 27 to the read input of the register 13, which determines the output of the code from this register to the second group of inputs of the switch

12. At the end of the dialogue, the WU-computer unit 11 generates at its output a control signal arriving at the first input of the AND 10 element and simultaneously through the OR element 8 to the single input of the trigger 7.

By performing the described operations, the synchronous input of the register 21 receives a clock signal from the generator 23, and the fifth bit of the register 21 is set to 1. The signal from the output of this bit goes to the setup input of the register 21, setting it to the state 000., .00, to the control input of the register 19, set it in the state 000 ... 00, and to the zero input of the control trigger 24, set it to O. The signal from the zero output of the trigger 24 goes to the second input of the element 10, the output of which is a single signal enabling switch 1 operation. The event has finished the exchange session: and is ready to service the next request

Consider the mode 1 of the device. In this case, the device operates in the same way as mode I, with the difference that the input of call 6 receives a signal from the computer. Thus, the trigger 7 is set from state 1 to which it was installed at the end of the last session of the device operation, to state O, switch to: switchboard 1 and switch 12 to mode 1, i.e. connect the information bus of the computer to the switch 2 of the device 2 to the switch 1, and the control bus of the device's output 14 to the commutator 12, information information of the bus on the outputs of the device 16).

If all requests for inputs 6 and 4 coincide, then the signal at input 6 forcibly sets trigger 7 to O, thus ensuring priority computer service,

Input 2 receives and sets the character code from the computer alphabet on the second group of information outputs of switch 1, and the address of the slave address accessed by the computer on the first group of outputs of switch 1 (since the inhibit signal from the second control input of switch 1 is absent). Subsequently, the device operates similarly to mode II, however, the register 19 receives the code of the address of the control unit, since through the element 20, the inputs of which are supplied with single signals from the single output of the trigger 7 and the output of the first bit of the register 21, a signal is generated at the input of the record 19 accept code.

As a result of the operation of the device in mode 1, a symbol in the alphabet of the VU is formed on the group of information outputs of the device to which the computer accesses, and on the group of control outputs of the device there is a sequence of microinstructions implementing the dialogue of the computer - VU. At the end of the dialogue, the device, similar to mode II, finishes its work and is ready to service the next request.

Claims (1)

Invention Formula A device for interfacing a computer with external devices, comprising a microprogrammed control unit, two switches, two registers, a shift register, a pulse generator, the first element OR, the first 0 five Q the group of information inputs of the first and first group of information outputs of the second switch form groups of inputs and outputs of the device for connecting respectively to groups of information outputs and inputs of a computer, the second group of information inputs of the first and second groups of information outputs of the second switch form groups of inputs and outputs of the device for connecting respectively to information outlets and informational 5 inputs of external devices, characterized in that, in order to expand functionality by increasing the range of connected external devices, the device has three registers, a switching trigger, a control trigger, a third switch, a memory unit, two decoders, an encoder, two single a vibrator, three AND elements, two OR elements, and a third group of information inputs of the first switch is connected to a group of inputs of the first OR element and forms a group of device inputs for connecting to external x devices (the information input of the first switch is connected to the zero input of the switching trigger, to the input of the first element OR, and is the input of the device for connection to the output of the PC, the first input of the second element OR is the input of the device for connection to the installation computer output, third and fourth groups 0 information outputs of the second switch form a group of device outputs for connecting, respectively, to groups of control inputs of a computer and external devices, while zero 5, the switching trigger output is connected to the first control inputs of the first, second switches and the first inputs of the first element I, the output of which is connected to the recording input of the first register, the group of information inputs of which is connected to the first group of information outputs of the first switch, the second control input of which is connected with the second control input of the second switch and with the single output of the switching trigger, the single input of which is connected to the output of the second OR element, the second input of which 0 0 five eleven connected to the first input of the second element I and to the output of the microprogram control unit, the output group of which is connected to the first group of information inputs of the second switch, the second group of information inputs of which is connected to the group of information outputs of the second register, the group of information inputs of which is connected to the first group of information outputs of the block the memory, the group of information inputs of which is connected to the group of information outputs of the third switch, the first group of information inputs which is connected to the group of information outputs of the third register, the group of information inputs of which is connected to the second group of information outputs of the first switch, the third control input of which is connected to the output of the second element I, the second input of which is connected to the zero output of the control trigger, the single output of which is connected to the first input of the third element And, the output of which is connected to the sync input of the shift register, the output of the first bit of which is connected to the second input of the first element And and the input of the third register entry, the read input of which is connected to the write input of the memory unit, with the first control input of the third switch, with the write input of the fourth one the register, with the enable input of the fifth register, with the control inputs of the encoder, the first and second decoders and with the output of the second bit of the shift register, the output of the third bit of which is connected to the first input of the third OR element, with the input of the fourth register, with the second control input of the third switch, with a read input of block 536392. 12 memory and to the recording input of the second register, the reading input of which is connected to the output of the first one-oscillator; the start input of which is connected to the enable input of the firmware control block, to the second input of the third OR element and to the fourth bit output of the shift register, the output of the fifth bit of which is connected to zero: the control trigger input, to the shift input of the shift register and to the setup input the first registrar, the group of information outputs of which is connected to the group of inputs of the logic block of the firmware control and to the second group of informational. the inputs of the third switch, the third group of information inputs of which are connected to the group of information outputs of the fourth register, the group of information inputs of which are connected to the group of outputs of the first decoder, the group of information inputs of which are connected to the second group of information outputs of the memory block and the group of information The 30 inputs of the encoder, the output group of which is connected to the group of information inputs of the fifth register, the group of information outputs of which is connected to the group of information inputs of the second decoder, the output group of which is connected to the group of address inputs of the memory unit, the read input of the first register is connected to the output third element 40 OR, the output of the pulse generator is connected to the second input of the third element, AND, the output of the first element OR is connected to the start input of the second one-vibrator, the output of which. 45 is connected to a single control trigger input. 35 I