SU1403366A1 - Pulse recurrence rate divider with adjustable pulse duration - Google Patents

Abstract

The invention relates to the field of pulsed technology. A pulse width following frequency divider with adjustable pulse duration contains a pulse counter 1, elements 3, 4, 13 comparison of codes, code buses 5, 6, triggers 7, 12, input and output buses 2 and 8, 9, respectively, element AND 10, element OR 11, the bus 14 control. The frequency divider has enhanced functionality by providing control for incorrect handling. 1 pe.

Description

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The invention relates to a pulse technique and can be used in Automation Devices and Computer to obtain a pulse g sequence with an adjustable Frequency and duration of output pulses.

The purpose of the invention is the extension of functionality by allowing for the control of incorrect processing of | 1eni.

: The drawing shows the electrical (Structurn -circuit of the device. I A pulse-frequency divider with an adjustable pulse duration contains a pulse counter 1, an input bus 2, the first and second) code comparison elements 3 and 4, the second and second code tires 5 and 6, the first trigger 7, the first and second output buses 8 and 9, the element AND 10, the clement OR 11, the second trigger 12 and the third element 13 of the code comparison, the outputs of the counter 1 pulse ijiM with the first groups of inputs of the first k of the second element 3 and 4 comparisons of feuds, the second groups of entries are php, are connected respectively with the first and: the second code 1, 5 and 6, the first trigger 7, the start input of which is so;; inn with the output of the first code equalization element 3, the reset input — from the soda reference comparison element 4 and the reset input of the counter 1 pulses, and the inverse and direct outputs | are connected to the control inputs, respectively, of the first and second element froB 3 and 4 of the comparison codes, and also Respectively with the first and second output buses 8 and 9, the first and second groups of inputs of the third element 13 comparison codes are connected respectively with the first and the second code bus 5 and 6, and the output More - with one of the inputs of the element OR 11, the other inputs of which are connected to the outputs of the pulse counter 1, the output of the element OR 11 is connected to the start input of the second trigger 12, the information and clock inputs of which are connected respectively with common and input bus 2, and direct and inverse forces, respectively, with bus control

Pulse frequency divider with adjustable pulse duration works as follows.

In the initial state, the counter I is reset, set to the zero state at the outputs of elements 3 and 4 - high levels, on bus 2 - low level, triggers 7 and 12 are reset,

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buses 5 and 6 set codes corresponding to the duration and period of the output pulses, with the code value on bus 6 exceeding the code value on bus 5, the output of the More element 13 is high, on bus 14 is low.

The clock pulses arriving at bus 2 pass through element 10 and trigger counter 1, which counts them. When the codes at the output of the counter 1 and on the bus 5 coincide, the element 3 generates a low level, by which the trigger 7 is set to one state. The change of states at the output of trigger 7 leads to the blocking of element 3, at the output of which a high level is established. At the same time, the operation of element 4 is permitted.

At the moment of coincidence of the code value at the output of counter 1 with the code on the bus b, element 4 is triggered, at the output of which a low level is formed, according to which counter 1 and trigger 7 are reset to the initial 5 state. After the trigger 7 has been reset, a low level on the bus 9 blocks element 4, a high level is set at its output, allowing the operation of the counter 1 .-

Thus, on buses 8 and 9, pulses are formed, the period and duration of which are determined by the binary code values on tires 5 and 6, respectively.

When a binary code is set on bus 5 to be equal to or equal to the code on bus 6, a low level is formed at the output of the More element J3, which at the time of counter-1 reset generates a low level at the output of element 11, which sets trigger 12 to one . At the same time on the bus

14 and the first input element AND 10, WTO-55 14 a high level is formed, with a signal input and output of which are connected respectively to the input bus 2 and the counting input of the pulse counter 1.

inflating on the incorrectness of the input code on tires 5 and 6, and a low level from the inverse of the trigger output

12 blocks the supply of clock pulses to the counting input of counter 1.

Claims (1)

Invention Formula Pulse-following frequency divider with adjustable pulse duration, containing a pulse counter whose outputs are connected to a front input of which is connected to a common bus, the start input - to the output of an OR element, the corresponding inputs of which are connected to an output of More than the third element by comparison groups of inputs of the first and second code comparison elements, the second groups of inputs of which are connected respectively to the first and second code buses and respectively to the first and second groups of inputs of the third element This code comparison, the first trigger, the inverse and direct outputs of which are connected respectively to the first and second output buses, the AND element, the OR element and the input bus, characterized in that, in order to expand the functionality, a second trigger and a control bus are introduced into it which is connected to the forward output of the second trigger, the inverse output of which is connected to the first input of the element I, the output of which is connected to the counting input of the pulse counter, the second input to the input bus and the clock input of the second trigger, information bus, the start input - with the output of the OR element, the corresponding inputs of which are connected to the output of More than the third comparison code element and the outputs of the pulse counter, the reset input of which is connected to the output of the second code comparison element and the reset input of the first trigger, the start input of which is connected to the output of the first code comparison element, inverse and direct outputs - with control inputs of the first and second code comparison elements, respectively.