SU1444778A1 - Device for automatic diagnosis of group of standard logical units - Google Patents

Abstract

The invention relates to the field of automation and computer technology and can be used for the technical diagnostics of discrete objects. The aim of the invention is to improve the speed of the device. For this purpose, a device consisting of n majority elements, m groups of n irregularity elements, two groups of n elements are entered into a device containing a test generator, a clock pulse generator, a switch, a group of n switches, a group of n counters and a display unit. And a group of n registers. 3 il. about "(L

Description

four; four

four

00

The invention relates to the field of automation and computer technology and can be used for the technical diagnostics of discrete objects,.

The aim of the invention is to improve the speed of the device.

FIG. 1 is represented; functional diagram of the device; Fig 2 is a switch conversion law; Fig. 3 shows an example of a major element.

The device contains n controlled logical blocks 1,. , 1, generator of 2 tests, generator of 3 clock pulses, m tunable majority elements 4. ,,. 4, switch 5, display unit 6, n switches 7 ,, 7, elements 8 h ,,,. 8 f ,, n counters 9 ,,,, 9f, 5 n additional elements And 10 ... 10 ,, n pa--. 11 registers 11,,,, 11 and PCT elements 12 ,, ,, 12, unequalities.

Switch 5 provides switching in such a way that in the first tunable majority element 4 the output signals of all the first outputs n of the monitored logic blocks 1 are compared, in the second tunable majority element 4 - all the second and m, d, m, e, compare, signals of identical outputs . The indicated switching law is explained in FIG. 2, The simplest switch of this type can be performed on the switching connectors,. response parts (where the switching is actually performed) of which vary depending on the type of control- pyet-aix logical blocks 1,

Tunable Majority Element 4 (FIGURE 3) consists of n-two-twot1

x, x

Xj9i Xj +

.

 Xf +

(X,

0).

where X, - Xj- are the output signals of logic blocks 1 G of the switch 5; |

 - Majority functions. If a signal O comes from some element (for example, from the first) AND 8, then the signals of the first logic block 1 do not pass

W. X2 He # X5 + t-X.

If the signal O (X, X 0) arrives from the two elements AND 8, then the majority function for the three variables Y X; j is implemented: # X4 # Xj, If with a track (X X2. Xe 0), then Y), i.e., rebuilding, of elements 4, depending on the number of diagnosed logical blocks 1.

The device works as follows.

All n counters are set to their original state, for which all n switches 7. ,, 7 are set to a position in which negative potential is supplied to the installation inputs of n counters 9,., 9 | (The test generator 2 is also reset, but for the sake of simplicity, this connection is not shown). Then all the n switches 71 ,,. 7 n are set to provide a positive potential to the first inputs n of the elements 8, 8 , and the installation inputs of the counters 9 .., 9f, thereby preparing the counters 9 ,,,,. 9., to pa

And 12, Cz-three-input bots, C inverse outputs of the resharmonious elements 13 and OR 14 (where n is the number of inputs, that is, objects, C is the number of combinations of 4 to 3), FIG. 3 shows an example of n tivhodovogo tunable majority element 4, in which 5 two-input elements And 12 and 10 three-input majority elements 13,

If the signals from all (five in this case) elements of AND 8 are equal to 1, then the function is realized:

Neni n counters 9. ,,. , 9 y, the positive potential goes to the second inputs of the corresponding elements .., 8 and elements 10.-i, .. 10. , If a

50

in this initial (static state) output signals of the corresponding outputs of logic blocks 1-1. ,, 1 are the same, then the corresponding tunable majority elements 4 ,,,. , 4 (produce a reference signal, which coincides with, the signals of the corresponding outputs of logic blocks 1 ,,. 1 (in the corresponding - Y Xi # X, + X ,,

55

bot, with inverse outputs of overflow n counters 9. ,,. , 9 у, the positive potential goes to the second inputs of the corresponding elements .., 8 and elements 10.-i, .. 10. , If a

12i ... 12.,, With inverse outputs

1 D) X m

which positive potentials are applied to the corresponding inputs of elements 10i ... l6rt, thereby preparing elements 10 ... 10 for operation. After that, the generator of 3 clock pulses is started. Generator 3 starts generating clock signals, which enter the generator of 2 tests directly and through elements 10 ... THEN the corresponding n counters 9 ... 9f | and n parallel registers 11 ... 11. In addition, the same signals through the elements 8., 8, build the work of the tunable majority elements 4, ....

If at the first {e clock cycle the signals of the i-ro logic block on the j-th output do not coincide with the signals jx of identical outputs of the remaining logic blocks 1 ... 1, then through the switch 4, enters the j-th tunable majority element 4j produced a reference signal by the majority, they will trigger the j-ro element 12j of unequalities, from the inverse output of which negative potential will go to the input of the corresponding element 101. As a result, the flow of clock pulses to the corresponding i-th counter 9 and parallel register 11; will stop. Register 11- registers the state of the generator 2 tests, i.e. test signal on which the fault is detected, and therefore, it can be determined. The l number of the optical block 1 and the output number on which a malfunction is detected in this logic block 1 is indicated in the display unit 6, due to the connection of the parallel registers 11, ... 11 elements 10, ... 10 with the block 6 indications.

If a fault in any kM logical block 1 f is detected at an arbitrary i-th cycle, then the corresponding k-th element of inequality 12 is triggered; a negative signal from the output of which is fed to the input of the corresponding element 10. Element 10. is closed and stops the arrival of clock pulses in the k-th counter 9 and the k-th parallel register 11. The state of the register 11 is indicated in block 6

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five

Q 5

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indications. The negative signal from the output of the k-ro element 10 is fed to the third input of the k-ro element 8 (., From the output of which a negative signal is fed to the enable inputs of the tunable element 4,.,. 4, the k-input tunable majority elements 4, .. .4 are rearranged to (n-1) -input, forming further reference signals without taking into account the disconnected k-ro logic block C. Further, the signal from the corresponding output of k-ro logic block 1 will not match in the corresponding element 12 unequalities with the reference signals with perestro ivaemogo majority element 4, resulting in the corresponding element of U is a negative flow signal, confirming the previously recorded state.

Thus, the shutdown of the entire device does not occur, the logical block 1, in which the fault is detected, is automatically detected and does not affect the process of diagnosing the remaining logs of the 1st blocks 1.

If any k-th logical block C does not contain defects, then there is no discrepancy between its output signals and reference signals of tunable major elements 4, ... 4, throughout the test. As a result, negative signals are not generated at the inverse outputs ix; exk − x of the unequality elements 12. The kth element 10j is closed by a negative signal from the inverse overflow output of the k-ro counter 9 ,. This is registered in the k-th parallel register 11. by stopping the supply of clock pulses from the k-ro element 10. and in the display unit 6.

The k-th element 8 also closes. It supplies a negative potential to the control inputs of the tunable majority elements 4, ... 4. In the shortest possible triggering of elements 12 is not; the equivalence associated with the outputs of the k-ro logic unit 1e only confirms the closed state of the k-th element 10.

Thus, the shutdown of ycTpoftCT-va upon detection of a defect in any of the logical blocks 1 does not occur. A block is registered and the output of this block, through which the signal came

cash on the defect. The device does not stop even when the health of any of the diagnosed logical blocks 1 is established, only the block itself is registered. As a result, the process of detecting a malfunction of a logic block (if a defect is detected) and a healthy logic block (if there are no defects in it) from the whole group of logic blocks that are in the diagnostic mode is automated. The time needed to diagnose each logical block depends only on its state (the number of defects), since the process of diagnosing other blocks does not occur (the blocks do not depend on each other).

Claims (1)

Invention Formula A device for automatically diagnosing a group of logic blocks of the same type, containing a test generator, a clock generator, a switch, groups of n switches (where n is the number of logic blocks being diagnosed), a group of n counters, and a display unit, the output of the clock generator connected to the synchronization input of the test generator, the outputs of which are the outputs of the device for connecting to the information inputs of diagnostic logic blocks, the i-group of the switch inputs (1 i 4p) is with the i-th group of interrupters of the device for connecting {from the i-ro outputs of the diagnosed logic block, the inverse overflow outputs of the group counters are connected to the inputs of the first group of the display unit, the setting input of the i-th group counter via the i-th switch five 0 The group is connected to a zero potential bus to a single potential bus, characterized in that it contains a group of m major elements (where m is the number of outputs of the diagnosed logic unit), m groups of n inequality elements, two groups from p. And elements and a group of p registers, while the i-th output of the 1st group of the output of the DON switch (1 j 4p, 1) is connected to the jM information input of the 1st major element of the group and the first j-ro element of the unequal group 1 , the second inputs of the 1st group inequality elements are connected to the output of the 1st majority element of the group, the first, second and third inputs and output of the j-ro element of the AND group of the first group are connected respectively to the inverse output of the overflow of the i-ro group counter, with the setting input i -ro counter; group, the output of the i-ro element of the second group and the i-th permitting inputs of the majority elements of the group, the output of the j-ro element of the 1st group inequality is connected to the 1st input of the J-ro element And the second group, (t + 1) - The inputs of the elements of the second group are connected to the output of the generator. ra clock pulses, (t + 2) -th input of the i-ro element And the second group is connected to the inverted overflow output of the i-ro group counter, the output of the i-ro element And the second group is connected to the counting input of the i-ro group counter Q. and the synchronization input of the i-ro reg-group of the group, the information inputs and outputs of the group registers are connected respectively to the generator outputs of the tests and the inputs of the second group of the display unit. 0 five Phie.-f . 8b /) (one / 1-gob / hash of F-gobbixodbi p-ha . ayaos / los. / y / fff / caf / oh. / fofca i & iaenos og. / fujca / ... to s il  v Canfor. c} (ode / kinform. nep6oii scheme U b / 77oroy schema / cpadneHuff comparisonPhia. 2 ff7 II Y7 Kinfo /. x (am t-oyshemsh cpa eHLisf O / n e / 1e en / po6 S and Phie.Z