SU1138809A1 - Device for checking wiring - Google Patents

Abstract

ELECTRICAL INSTALLATION MONITORING DEVICE containing an indication unit, clock generator connected to clock inputs of the first single pulse generator and control pulse driver unit, four information inputs of which are connected to the corresponding keyboard outputs, address switches connected to information inputs of the address signal generator addresses, and the tires of the type of check — with information inputs of the first buffer register that control inputs The address signal generator, the address register and the first buffer register are connected respectively to the first, second and third outputs of the control pulse shaper unit, the fourth output connected to the first input of the first OR element of the interrupt shaping node, consisting of the first RS trigger, the second OR element and the first And connected by the output to the information input of the first single pulse generator and the second input of the OR element, the output of which is connected to the R input of the first trigger, 8 input connection The output of the second element OR, which is connected to the first input to the first output of the test result analysis node, consisting of a block of elements 2И-OR and the first comparison block, the output of which is connected to the first input of the block of elements 2И-OR, and the first input together with the information the inputs of the switch are connected to the input of the device, the second input of the first comparison unit is connected to you (L of the reference number generator, the control input connected with the output of the first buffer register, and the information input - with the output of address address signal generator, which is the output of the control address of the device, 1c with the address input of the switch and the first input of the second comparison unit, the second input of the address register connected to the DO output, and the output with the 00–00 first input of the first AND element, characterized in that In order to increase the reliability of the control results, a measuring node consisting of an amplifier unit, a comparator and a reference voltage block, a code converter, a test type generating unit consisting of the third and tvertogo element or shaper shift pulses, the shift register forming species and test the first block member and

Description

the check type preparation node, which is connected from the second buffer register, the second block of AND elements, the second and third single pulse shapers, the shift register of the control signals, the second And element, and the second RS are three geres, the polling control signals generating node from the block of elements OR, the third block of elements AND, the shift register of the interrogation and the third element AND, the block of delay and the five element OR connected by the first input to the output of the second single pulse generator and the control input the house of the second buffer register; the second input — with the output of the third single-pulse generator and the first input of the second block of AND elements; the third inputs — with the first group of outputs of the OR block and information outputs of the device; the fourth inputs — with the second group of outputs of the OR block and control the inputs of the switch, and the output with the control input of the delay unit,. the clock input of which is connected to the output of the clock pulse pulse generator, output voltage to the first inputs of the second and third elements AND, and information input to the outputs of the first AND block connected to the first inputs of the third AND block, the first inputs of the display unit, the second inputs the second block of the elements And the third element of the RSHI, the first inputs of the first block of the elements And are connected to the output of the first buffer register, the second inputs to the outputs of the shift register forming the type of check, the output of the last bit It is connected to the third input of the first OR element, and the clock input to the first output of the clock generator, connected to the clock input to the output of the clock generator, and the first and second control inputs to the outputs of the third and fourth elements of the SII, the first input of the fourth (OR element connected to the fourth output of the control pulse shaper unit, and the second to the output of the first single pulse shaper, the second output of the shift pulse shaper is connected to the S input of the second RS flip-flop, The output to the second input of the third element is And, the third input of which is connected with the output of the clock pulse generator, and the output with the clock input of the shift register of control signals connected by the first and second outputs to the control inputs of the second and third drivers of single pulses, clock inputs which are associated with the output of the clock clock, the third output of the shift control register of signals is connected to the R input of the second RS-trigger, a quarter output with the second input of the second element OR, t The second input element I is connected to the output of the conversion of the signal end of the converter of the code converter, the information outputs of which are connected to the second inputs of the display unit, the control input to the second output of the 2K-OR element block, the clock input to the clock pulse output, address inputs c At the inputs of the address signal generator, the output of the first RS flip-flop is connected to the third input of the third element And connected by the output to the clock input of the shift poll connected by the outputs to the second inputs the third block of elements And, and the output of the last bit — with the second input of the first element And; the outputs of the third block of elements AND are connected to the inputs of the block of OR elements, the third output of which is connected to the input of the interrogation of the block of elements 2И-OR, the fourth output with the fourth input of the first the element OR, the fifth output is from the clock input of the address signal generator, the second input of the 2I-Sh1I block is connected to the output of the comparator, the first input connected to the output of the amplifier block, the second input to the first output of the reference voltage block, channeling inputs of amplifiers block and block reference voltages are connected to the output of the second buffer register unit data inputs of the amplifiers connected to the outputs of the switch, and the second output block of reference voltages - a setpoint output switch influences. The invention relates to automation and computer technology, in particular to devices for checking and controlling the integrity of electrical circuits (Measuring their resistance and provarking the functioning of radio elements included in the electronic device being checked. A device for controlling digital blocks is known, which contains an input unit, a control unit, a comparator unit, an indication unit, a switch, a memory unit, five registers, a decoder, and a load master I. The disadvantage of the device is the complexity of the structural and circuit structure. and requiring for the implementation of a significant amount of equipment and high material costs. It is also known a device for controlling assembly connections, comprising a serially connected control unit, a pulse generator, a pulse counter, a decoder and a switch, the output of which is connected to the inputs of the program input and output blocks, the outputs of which connected to the inputs of the control unit, unequalities, some of the inputs of which are connected to the outputs of the block of yes and programs, and the outputs to the inputs of the block of output of the program 2j, I H The balance of this device is the low reliability of control, since it is comparing with the standard, and the incomparability error is not analyzed qualitatively. The closest to the technical essence of the invention is a device for checking electrical installation, containing a communication node with a monitored object, whose inputs are connected to the corresponding outputs of the switch and the corresponding information inputs of the interrogation switch, whose address input is connected to the output of the point counter and the first inputs buffer register and I / O node, address decoder register, circuit counter, number of dots register, comparison circuits, pulse generator connected to the control node, which is connected to a comparison circuit, a point counter, a circuit counter, an address register and an I / O node. A disadvantage of the known device is the inability to check the resistances of the radio elements included in the monitored unit. For example, the presence of resistance in the tested circuit, amounting to ten Ohms, is recorded as a fault, i.e. open circuit. In addition, there is no possibility of testing in the switched on state of the object, which is necessary, for example, to test relay blocks with normally open contacts. These drawbacks lead to a decrease in the reliability of electrical installation checks, an increase in the time of the verification process, since the known device requires development costs and work programs, which is not economically profitable when organizing installation testing of assemblies with a low-capacity installation and a small series of manufacturing. The aim of the invention is to increase the reliability of the results of electrical installation monitoring by checking the monitored unit in the on state. I The above objective is achieved in that a device for controlling electrical installation, comprising a display unit, a clock generator connected to the clock inputs of the first driver. single pulses and a control pulse shaper unit whose information inputs are connected to the corresponding keyboard outputs, address buses connected to the information inputs of the address signal generator and the address register, and test type buses to the information inputs of the first buffer register that control the inputs of the address CHI- the base, the address register and the first buffer register are connected respectively to the first, second and third outputs of the control pulse shaper unit the fourth output of the first OR element connected to the first input of the interrupt shaping node consisting of the first RS trigger, the second OR element and the first AND element connected to the information input of the first single pulse generator and the second input of the first OR element,

 the output of which is connected to the R-input of the first trigger, S-input connected to the output of the second element OR, which is connected to the first input to the first output of the test result analysis node consisting of a block of elements 2И-ШПРand the first comparison block whose output is connected to the first input unit 2I-OR, and the first input, together with the information inputs of the switch, is connected to the input of the device, the second input of the first α-comparison unit is connected to the output of the reference number generator, which controls the input connected to the output of the first the buffer register, and the information register — with the output of the address signal generator, which is the output of the device control address, with the address input of the switch and the first input of the second comparison unit, the second input connected to the (OUTPUT ”address register, and the output with the first, input of the first element, a measurement unit consisting of an amplifier unit, a comparator and a reference voltage unit, a code converter, a test type generating unit consisting of the third and fourth OR elements, a pulse generator have been introduced s of the shift, the shift register of the formation of the check type and the first block of elements And the node of the preparation of the check type consisting of the second buffer register of the second block of the And elements, the second and third formers of single pulses, the shift register of the formation of the control signals, the second And element and the second RS a trigger, a polling signal generating unit consisting of a block of elements SHS of the third block of elements AND, a shift register of the interrogation and the third element AND, a delay unit and the fifth element OR, connected first in with the output of the second single pulse generator and the control input of the second buffer register, the second input — with the output of the third single pulse generator and the first input of the second block of And elements, the third inputs — with the first group of outputs of the OR block of information and information outputs of the device, the fourth inputs - with the second group of outputs of the block of OR elements and the control inputs of the switch.

and the output from the control input of the delay unit, the clock input of which is connected to the output of the clock pulse generator, the output to the first inputs of the second and third And elements, and the information input to the outputs of the first block of And elements connected to the first inputs of the third block of And elements, first the inputs of the display unit, the second inputs of the second block of the AND elements and the third element OR, the first inputs of the first block of the AND elements are connected to the output of the first buffer register, the second inputs - to the outputs of the shift forming register Ida verification, the last bit output of which is connected to the third input of the first element OR, and the clock input to the first output of the shift pulse generator connected by the clock input to the output of the clock generator, and the first and second control inputs to the outputs of the third and fourth elements OR, the first input of the fourth element OR is connected with the fourth output of the control pulse generator, and the second input - with the output of the first single pulse generator, the second output of the shift pulse generator with It is connected to the second input of the third element I, the third input of which is connected to the clock pulse generator, and the output to the clock input of the shift control register connected to the first and second outputs from the control the second and third single pulse drivers, the clock inputs of which are connected to the output of the dc pulse generator, the third output of the shift control register is connected to the R input of the second RS flip-flop, the fourth in move - to a second input of the second OR gate, the third input

the second element AND is connected to the output of the formation of the signal end of the converter of the code converter, the information outputs of which are connected to the second inputs of the display unit, the control input - to the second output of the 2I-OR element block, the clock input - to the output of the clock generator, the address inputs from the address generator 5, the signals, the output of the first RS flip-flop is connected to the third input of the third element And connected to the output to the clock input of the polling shift register connected by the outputs with the second inputs And the output of the last bit is connected to the second input of the first element AND, the outputs of the third block of elements AND are connected to the inputs of the block of elements OR, the third output of which is connected with the input of the interrogation of the block of elements 2I-OR the fourth output to the fourth input of the first the OR element, the fifth output with the clock input of the address signal generator, the second input of the 2I-OR unit block — with the comparator output, the first input associated with the output of the amplifier unit, the second input, the first output of the reference voltage block, which controls the inputs of the amplifier unit and the reference voltage block are connected to the output of the second buffer register, the information inputs of the amplifier block are connected to the switch outputs, and the second output of the reference voltage block to the input of the switch action set.  FIG.  1 shows a diagram of the device; in fig.  2 - diagram of the formation of the body of address signals; in fig.  3 is a comparison block diagram; in fig.  4 shows the reference number generator of FIG.  5 is a switch diagram; in fig.  6 is a diagram of the first buffer register; in fig.  7 is a diagram of the delay unit; in fig.  8 is a block diagram of the analysis of test results; in fig. 9 code converter circuit; in fig.  10 is a diagram of a shear pulse shaping device; in fig.  11 and 12 - diagram of the clock pulses; in fig.  13 is a timing diagram of the clock pulse generator.  I The proposed device contains (FIG.  1) clock pulse shaper 1, keyboard 2, control pulse shaper block 3, address signal shaper A, indication block 5, switch 6, measurement node 7, which contains an amplifier block, comparator 9 and reference voltage block 10, knots. Ate 11 analysis of the test results, which contains the first comparison unit 12 and block 13 2I-OR elements, the driver 09 14 of the reference number, the first buffer register 15-, the second comparison block 16, the address register 17, the code converter 18, the signal generation node 19 check, which contains the driver of the pulse shear 20, the first block 21 of the elements AND, the shift register 22 forming the test type, the third element OR 23 and the fourth element OR 24, the first driver of the single pulse 25, the test type preparation node 26, which contains the second buffer register 27, the block 28 And elements, the second 29 and the third 30 single pulse shapers, the shift register 31 of the formation of control signals, the second element AND 32 and the second RS-flip-flop 33, the polling signal generation unit 34, which contains a blots 35 11PI elements , the third block 36 And elements, the shift register 37 of the survey, the third element 38 And, the node 39 interrupt, which contains the first RS-flip-flop 40, the first 41 and second 42 elements OR and the first element And 43, block 44 delay, the fifth element OR 45, the first output 46, the second output 47 and the input 48 of the device.  Shaper 4 address signals (FIG.  2) contains a block of 49 elements And, the counter 50, the register 51, the block 52 of the elements OR, the blocks 53-55 elements And and the trigger 56.  The first 12 and 26 second comparison blocks (FIG.  3) consist of elements 57-59 of comparison and element AND 60.  The shaper 14 is a reference number (FIG.  4) contains the decoder 61, the block 62 of the elements NOT, the blocks 63 and 64 of the elements And and the block 65 of the elements SH.  Switch 6 (FIG.  5) contains register 66, decoders 67 and 68, power supply bus 69, buses 70 and 71.  The first buffer register 15 (FIG. 6) contains triggers 72-74 and elements 75-77.  Delay unit 44 (FIG.  7) contains the elements And 78-80, the counter 81, the block 82 of the elements AND, the element OR 83, the triggers 84 and 85, the Node 11 of the analysis of the test results (FIG.  B) contains the elements OR 86 and 87, the elements AND 88-91 ,.  elements NOT 92 and 93.  code converter 18 (FIG. 9) contains the element 94 delay, blocks 95 and 96 elements And, counters 97 and 98, triggers 99 and 100, elements And 101-104 and shaper 105 single pulses.  Pulse shaper 20 includes a shift (FIG.  10) triggers 106 and 107 and elements And 108-110, Formers 25, 2. 9 and 30 single pulses contain (FIG.  11) triggers 111 and 112 and the elements And 113 and 114.  Clock driver (FIG.  12) consists of a pulse generator 115 and a shift register 11 which generates four clock pulses T1, T2, TZ and T4.  Switch 6 (FIG.  5) also contains a relay group and a group of corresponding contacts.  Keyboard 2 is made on the switches, for example, type P2K (contains a group of switches for setting the address code on the fifth output, a group of switches for specifying the types of testing on the sixth output, and a group of switches for generating single pulses from the first to fourth outputs).  FIG.  1-12, the power supply circuit of the elements of the device circuit and the circuit for setting the zero state of the memory elements (triggers) are conventionally not shown.  In functional block diagrams, devices with coupling are designed for a group of different signals.  For example, the signals of the test types, combined by the communication link from the output of block 21, are formed different.  elements included in the block containing the number of communication circuits corresponding to the size of the register 15, the device works in the following way.   The types of checks, the starting and ending addresses of the points of the controlled object are set by the corresponding switches on the keyboard 2 and entered into the device blocks by turning on the switches that control the formation of pulses at the inputs of the block 3.  The impulse from the first output of block 3 introduces the starting address of the check into the driver 4.  The impulse 098 from the second output of block 3 into the register 17 enters the address of the last point of the controlled object.  The impulse from the third output of block 3 to register 15 introduces the types of checks to which the controlled object is subject.  Each type of check is conditionally characterized by the inclusion of the corresponding trigger in register 15.  Types of checks in the device, for example, can be checking the presence of a circuit, checking the disconnection of circuits, measuring the resistance of the circuit (resistors, diodes, etc. d. ), with the change of the measuring range considered as a change of the type of test.  Inspection of a controlled object can be performed on all types of inspection and parts of them.  The transition to the next specified type is carried out automatically at the end of the check at the last point of the object being monitored, the specified types of checks are memorized by the enabled 11-1k triggers of register 15.  The signal of one trigger controls only one specific type of test (in FIG.  6 conventionally shown only three, bit).  The type of check is formed when signals are simultaneously received at the two inputs of the corresponding elements AND block 21.  Register 22 provides the advancement of a single signal in bits in a natural, sequential order, and a single signal can be present at the output of only one bit, and a check type signal can be generated at the output of only one of the elements and block 21, at the inputs of which coincidence of single signals from the outputs of the register 15.  The operation of the blocks of the device is synchronized with clock pulses, which are aboard the driver 1.  All four clock pulses are applied to the first input of the imaging unit 20 in order to form the shift pulses in the test generation unit 19.  The shift pulse is formed by element AND 109, which is controlled by one of the inputs by a trigger signal 107, and the second input of the elements 109 is fed by a clock pulse T1.  The trigger 107 is made according to an R-S scheme. Its S input is the second input of a driver 20 connected to the output of the OR element 24, the first input of which is connected to the fourth output of block 3, and the second to the output of the driver 25.  When the corresponding switch is turned on with the Start button in the keyboard, round 2 in block 3, a pulse is generated from the fourth output through the OR element 24 to the second input of the driver 20 and triggers trigger 107, which gives a decision signal to the inputs of the AND 108 109 elements.    At the first cycle T1, at the output of the element I 109 a pulse will be generated, which will go to the input of the register 22 and a signal corresponding to the unit level will be set at the output of its first bit.  If the type of check that corresponds to the first bit of register 15 is not specified, and its trigger is set to zero (initial) state, then the first AND element in block 21 does not generate a pulse.  In this case, the shaper 20 generates the pulses and shifts the single signal in the register 22 until the unit level signal corresponding to the specified test type is generated at the output of the block 21.  Such a work shift process lasts until the trigger's enabled trigger in register 15.  When a single signal appears at the output of block 21, it is fed to the input of an element, OR 23, the output of which is connected to the third input of the former 20, and the second input of the element 108 connected to it.  At the same time with the advent of the impulse on it. the third input on the second cycle T2 includes a trigger 106, which gives permission to pass the third cycle TZ through the element 110, the pulse from the output of which sets the trigger 107 to its original position.  Thus, the shift process in register 22 is terminated, and a signal of a specified type of test is set at the output of block 21.  The trigger 106 sets the starting position with a pulse according to the fourth cycle T4.  Simultaneously with the installation of the trigger 107 to the initial position, a pulse according to the third cycle TK from the output of the element 110 is fed through the second output of the driver 20 to the first input of the trigger 33 of the node 26, which connects the device blocks necessary to perform the verification process of the monitored unit checks.  The preparation process is carried out as follows.  The enabled trigger 33 generates a permission signal to the second input of the element 32, to the third input of which a unit signal from the output of the trigger 85 of the block 44 arrives. In the initial state of the device, the trigger 85 is set to its output, which is the code of the 44 , set to single signal level.  According to a clock cycle T1, which is fed from the output of the imaging unit 1 to the first input of the element 32, an output pulse is generated at its output, which is fed to the input of the four-bit shift register 31, the first output of which controls the imaging unit 29.  The impulse from the output of the imaging unit 29, which arrives at the first input of the register 27, sets the triggers included in its structure, the initial state, and they disconnect the previously switched on amplifiers of the unit 8 and the units 10.  Simultaneously, the pulse from the output of the imaging unit 29 is supplied to the first input of the element SHSh 45, from the output of which the impulse is transmitted to the second input. includes  block 44.  In this case, the trigger 85 is switched and a inhibit signal is set at the third input of the element 32 and a clock pulse T1 is not generated at its output.  The formation of the delay is as follows.  When a pulse arrives, neither the second input of the block 44, the counter 81 is set to the zero state, and the trigger 84 is turned on, which gives permission to the first inputs of the And elements 78 and 79, the second inputs of which receive the clock pulses T2 and TZ, respectively.  Element And 79 is closed at the third input signal from the output element OR 83.  The second cycle T2 generates a pulse at the output of the element And 78, which enters the counter input of the meter-81, the signals from the output of the bits of which arrive at the first inputs of the block 82, the second inputs of which are given the signals of the check type.  When the counter 81 is set to the position at which the code for its output will correspond to the time specified by the included check type on the second inputs of block 82, on. its output will form a ready signal and through the element OR 83 it will give permission to the third input of the element 79 for generating a pulse at the third cycle of the TZ received at its second input, while the trigger 85 will return to the initial state.  Element And 80 on the fourth clock cycle T4 will form a pulse that sets the trigger 84 to its original position, for which the operation of the counter 81 is prohibited.  The output of the trigger 85 is allowed to form a pulse by the second element I 32, which switches the register 31 to the next position, in which the signal from its second output turns on the controller 30, the pulse from the output of which through block 28 turns on the corresponding triggers of the register 27 and switches the corresponding inputs and the outputs in block 8 and in block 10, which are necessary for performing operations on this type of verification.  At the same time, a pulse from the output of the imaging unit 30 is fed to the second input of the OR element 45 and from its output it ensures the formation of a delay of control signals in the block 44.  Formation of time delays during preparatory operations by node 26 is necessary in order to avoid emergency situations in the device that may occur when switching the sources of reference voltage in block 10 and installing voltages unauthorized by this type of test at the output of the device.  After the formation of the time delay, the element 32 is again switched on, the pulses from the output of which reach the input of the register 31, the pulse from the third output of which through the first input of the element OR 42 turns on the trigger 40, and the pulse from the fourth output of the register 31 sets the trigger 33 to the initial one, the zero state and prohibits the formation of pulses by the element AND 32.  This completes the preparation of the device for operation on this type of verification.  0912 The activated trigger 40 sets the enable signal to the third input of the element I 38, the second input of which contains the enable signal from the trigger 85 of the block 44.  With the arrival of the pulse at cycle T1, the unit signal levels at its inputs coincide, the AND 38 element generates a pulse to the input of the register 37, the output of the last bit of which serves to generate a transition signal to the AND 43 element after performing the last operation in the specified check type.  The pulses from the first outputs of the register 37 are fed to the first inputs of the block 36, the second input of which receives signals of the type of check from the output of the block 21.  If the signal at the inputs of the block 36 matches the type of test and the signal from the output of one of the pa. The register of the register 37 at its output forms a signal that is fed to the input of the block 35.  The output of block 36 represents the groups of outputs of elements AND, which are assembled according to functional values and connected to the inputs of the elements OR, which are part of Block 35. On the first output of block 35, control signals are formed to control the object being monitored, and on the second output - signals controlling the switch 6.  The operations on the control signals of the first and second outputs of the block 35 take longer than the time of the shift operation by one bit of register 37, therefore the signals of these outputs switch on the block 44 on the third and fourth inputs of the OR element 45, When the delay is activated the prohibition of the formation of a shift pulse on the first input of the element PI 38, which provides time to perform the operations specified by the signals from the first and second outputs of the block 35.  The fourth output of block 35 generates a signal to interrupt the operation of the device, further. the course of work depends on the results of previous operations.  From the third output of block 35, a signal for polling the result by node 7 and a signal for polling the result of the comparison of codes by block 12 are formed, which are fed to the third input of block 13.  On the downstream output of block 35, control signals are generated, which are fed to the third input of the imaging unit 4, which generate the address pulse, the switching pulses of the trigger 56, which are controlled by the blocks 53 and 55 when generating the address signals from the output of the counter 50 or the register 5. 1 and the signal transfer code addresses from the counter 50 through the block 54 in the register 51.  Interrupting the operation of the device is achieved by stopping the subsequent generation of control signals when switching the first trigger 40 in the node 39, the output of which has a zero signal and closes the input element 38 at the third input, which ensures the formation of a shift pulse at the input of the register 37.  Interrupting the formation of the control signals by the first element OR 41 is carried out in the following cases: on the first V7SDU pulse from the fourth output of unit 3 when the device starts, when no test type signals have been generated yet the device and the monitored unit are protected from emergency situations; the second input signal from the output of the element 43, when its inputs coincide signals of the final verification address from the output of block 16 and the signal from the last bit of register 37, in this case the driver 26 generates a signal that through the second input of the element OR 24 turns on the driver 20 to form the following type of test; at the third input of the OR 4 element, an interrupt signal is generated when a signal is received from the last row of register 22, which signals the end of the check of the monitored object; on the fourth input, a break signal is generated from the fourth output of block 35 to perform a comparison operation.  The operation of all the device shift registers is carried out in a ring mode, in which the unit is written to the first digit by a signal from the output of the last digit.  The initial entry of the unit into the first bit of the shift registers is carried out by the signal of the initial, zero setting, the circuit of which is not shown on the functional circuits.  The formation of the signal of the final address from the output of block 16 is achieved on the basis of a comparison of equivalent address codes, one of which is the current address of the monitored object being scanned to the second input, and the address code that goes to the first input from the output of the register 17, which is entered into it before starting the inspection of the monitored object and characterizes the number of controlled points.  The assessment of the correctness of the installation of the object being monitored is carried out by measuring the parameters of the output signals at the controlled point by node 7 or by comparing codes using block 12.  In the first case, the output points in the monitored object are sequentially connected to the information input of the amplifiers of the block 8 of the node 7 using the switch 6, the address of the point being set by the driver 4.  In the second case, all points with low and high levels of signals established on them are taken as the code of the number at the output of the object being monitored, arriving at the first input of the block 12, the second input of which receives the code of the reference number from the output of the driver 14.  The basis of the former 14 is constituted by a decoder 61, the signals from the output of which in the forward and inverse code arrive through the blocks 63 and 64 into the block 65, the output of which is the output of the former 14.  The formation of the reference number is controlled by the second input of the driver 14 by signals from the outputs of the register 15.  First, the resolution signal is fed to the control input of block 64 from the output of flip-flop 72, which ensures the formation of a reference number in the inverse code, and the enable signal to the formation of a reference number in the forward code comes from flip-flop 73 to the control input of block 63.  The output of block 12 is connected to the first input of block 13 of elements 2И-Ш1И, the second input of which is connected to the output of comparator 9, which compares the levels of input and reference voltages, which are set by block 10 by control signals of the register 27.  When equivalent codes arriving at the first and second inputs of block 12 are compared, or when the comparator 9 compares signals with a level corresponding to the normal rate, which is a sign that there is no error in the installation of the object being monitored, the signals received at the first or second input of block 13 will be generated to the first inputs of the elements And 88 and 89, as well as through the elements HE 92 and 93 to the inputs of the elements 90 and 91, the second inputs of which are gated with pulses of the corresponding control signals from the third output of the block 35 n the third code of block 13 If at the inputs of elements And 88 and 89 of the signals of the absence of mounting errors with the interrogation signals of the comparison of codes or comparison of voltages, a signal will be generated at their output, which through the element OR 86 goes to the second input of the element OR 42 and its output is triggered by a trigger 40, turned off by an interrupt signal.  If the inputs of block 12 contain codes of different values or the measured input signal does not correspond to the norm, then there are no signals on the first or second inputs of block 13.  In this case, a pulse is formed by one of the elements AND 90 or 91, since their first inputs are connected to the output of block 12 and to the output of comparator 9 through the elements HE 92 and 93, which invert the input signal.  Therefore, a signal is formed at the output of the element OR 87, which is the second output of block 13 connected to the second input of the converter 18.  Converter 18 converts the binary code of the address of the incoming to its third input from the output of the driver D to the decimal code, which from its first output goes to the second input of block 5.  When the conversion is completed on the second, the output of the converter 18 forms a trigger switching signal 09 through the 40 element OR 42 to continue the operation terminated by the interrupt signal.  The code conversion is carried out as follows.  The error signal received at the second input of the converter 18, includes a trigger 100, which allows the passage of the first cycle T1 through the element And 101 and the second cycle T2 element And 102.  In the first cycle T1, the counters 97 and 98 are set to the zero state, and in the second cycle T2, through the block -96, the binary code of the error address is entered into the counter 98 and trigger 99 is turned on, which gives permission to the first inputs of the elements And 103 and 104, Clock pulses TZ through the element And 103 arrive at the counting inputs of counters 97 and 98.  The trigger 100 is set to the initial position by the first pulse of the clock cycle.  The clock pulses of the TZ are used to write 1 to a ten counter 97 and 1 to charge off binary counter 98.  After zeroing the counter 98, the counter 97 will record the number in decimal code corresponding to the binary number recorded initially in the counter 98.  The signal to zero the counter 98 with the arrival of the clock pulse T4 element And 104 generates a pulse to the driver.  105, which gives permission to output information from counter 97 through block 95 to block 5, issues a signal to the second output of converter 18 to continue operation and, through element 94, flushes trigger 99.  The continuation of the work occurs when the trigger 40 is turned on, - allowing the passage of clock pulses through the AND 38 element to the register 37.   The test of the monitored object is carried out by connecting the wiring contacts to the input 48 of the device.  At the output 46 of the device, a control action is entered into the monitored block, and at output 47 the address code of the object being monitored is entered.  The entire contact field of the object to be monitored is considered as an N-bit number, in which the unit signal level will be only in the bit represented by the closed contact group.  The reference code of the number is fed to the second input of the block 12 1711 from the driver 14.  The successive change of the address code in the device at output 47 and the change of control signals on the video 46 produces, with alternate switching on and off of the relay in the controlled object.  Along with the change of the address code, the reference number changes.  If there is an error in the installation of the monitored object, the code on its output will not correspond to the reference 98 code, and the Error address will be fixed in block 5.  Thus, the proposed device provides testing of products with electrical installation in an automatic mode according to a rigid program, has high reliability, allows measurements of electrical parameters of radio elements included in the composition of the products under test, while monitoring the state of the object is carried out in the on state.

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Claims (1)

DEVICE FOR MONITORING THE ELECTRICAL INSTALLATION, comprising an indication unit, a clock shaper connected to clock inputs of the first single pulse shaper and a control pulse shaper block, four information inputs of which are connected to the corresponding keyboard outputs, address buses connected to the information inputs of the address signal shaper and address register , and with tires of the type of verification with information inputs of the first buffer register, control inputs of the driver a signals, the address register and the first buffer register are connected respectively to the first, second and third outputs of the control pulse shaper unit, the fourth output connected to the first input of the first OR element of the interrupt generation unit, consisting of the first RS-trigger, the second OR element, and the first AND element connected by the output to the information input of the first shaper of single pulses and the second input of the OR element, the output of which is connected to the R-input of the first trigger, S-input associated with the output the second OR element, which is connected by the first input to the first output of the analysis result analysis node, consisting of a block of 2-OR elements and a first comparison block, the output of which is connected to the first input of the 2-OR element block, and the first input is connected to the information inputs of the switch the input of the device, the second input of the first comparison unit is connected to the output of the shaper of the reference number, controlling the input associated with the output of the first buffer register, and information - with the output of the shaper of the address signals, output device control address | with the address input of the switch and the first input of the second comparison unit, the second input connected to the output of the address register, and the output with the first input of the first AND element, characterized in that, in order to increase the reliability of the control results , a measurement unit consisting of a block of amplifiers, a comparator and a block of reference voltages, a code converter, a signal generation unit of a verification type consisting of the third and fourth OR elements, an impedance shaper, are introduced into the device lars of shift, shift register of forming the type of check and the first block of And elements, the node for preparing the type of verification, consisting of the second buffer register, the second block of elements And, the second and third shapers of single pulses, the shift register of the formation of control signals, the second element And and the second RS- trigger, a node for generating control signals of the survey, consisting of a block of OR elements, a third block of AND elements, a shift register of the survey and a third AND element, a delay unit and a fifth OR element, connected the first input with the output of the second shaper of single pulses and the control input of the second buffer register, the second input with the output of the third shaper of single pulses and the first input of the second block of AND elements, the third inputs with the first group of outputs of the block of OR elements and information outputs of the device, fourth inputs - with the second group of outputs of the block of OR elements and the control inputs of the switch, and the output - with the control input of the delay unit, the clock input of which is connected to the output of the shaper clock pulses, output - to the first inputs of the second and third elements And, and the information input - to the outputs of the first block 'of elements And, connected to the first inputs of the third block of elements And, the first inputs of the display unit, the second inputs of the second block of elements, elements And and of the third OR element, the first inputs of the first block of AND elements are connected to the output of the first buffer register, the second inputs to the outputs of the shift register of the form of verification, the output of the last bit of which is connected with the third input of the first OR element, and input - with the first output of the clock shaper connected to the clock output to the output of the clock shaper, and the first AND second control inputs to the outputs of the third and fourth OR elements, the first input of the fourth> OR element is connected to the fourth output of the control pulse shaper block, and the second with the output of the first single pulse shaper, the second output of the shear pulse shaper is connected to the S-input, the second RS-trigger connected to the second input of the third element And, the third the input of which is connected to the output of the pulse shaper, and the output is to the clock input of the shift register of control signals connected by the first and second outputs to the control inputs of the second and third single pulse shapers, the clock inputs of which are connected to the output of the pulse shaper, the third output of the shift control register signal is connected to the R-input of the second RS-trigger, the fourth output with the second input of the second element OR, the third input of the second element AND is connected to the output of the formation of drove the end of the conversion of the code converter, the information outputs of which are connected to the second inputs of the display unit, the control input with the second output of the 2K-OR element block, the clock input with the output of the pulse shaper, address inputs with the outputs of the address signal shaper, the output of the first RS- the trigger is connected to the third input of the third AND element, connected by the output to the clock input of the shear poll, connected by the outputs to the second inputs of the third block of And elements, and the output of the last discharge - from the second by the first element AND, the outputs of the third block of AND elements are connected to the inputs of the block of OR elements, the third output of which is connected to the polling input of the block of 2I-OR elements, the fourth output is with the fourth input of the first element 'OR, the fifth output is with the clock input of the address signal generator, the second input of the block of elements 2I-OR is connected to the output of the comparator, the first input connected to the output of the amplifier block, the second input to the first output of the block of reference voltages that control the inputs of the block of amplifiers and the block of reference voltages s with the output of the second buffer register data inputs of unit amplifiers connected to the outputs of the switch and the second output of the reference voltage unit - to the output of reference impacts switch.