KR20190026470A - Epitaxial wafer and method for fabricating the same - Google Patents

Abstract

According to an embodiment, disclosed is a manufacturing method for an epitaxial wafer comprising: a preparing step of arranging a wafer on a rotating plate of an epitaxial wafer manufacturing device subjected to epitaxial growth; and an epitaxial growth step of growing an epitaxial wafer by injecting a reaction source including growth gas, doping gas, and diluting gas into the epitaxial wafer manufacturing device. The preparing step of arranging the wafer includes one step selected from a step of baking a chamber, a step of injecting a silicon source, and a step of N-type coating the chamber.

Description

[0001] EPITAXIAL WAFER AND METHOD FOR FABRICATING THE SAME [0002]

An embodiment relates to an epitaxial wafer and a method of manufacturing the epitaxial wafer.

Generally, a technique for forming various thin films on a substrate or a wafer

Chemical Vapor Deposition (CVD) is widely used. The chemical vapor deposition method is a deposition technique involving a chemical reaction, which uses a chemical reaction of a source material to form a semiconductor thin film, an insulating film, and the like on the wafer surface.

Such a chemical vapor deposition method and a vapor deposition apparatus have recently attracted attention as an important technique among thin film forming techniques due to miniaturization of semiconductor devices and development of high efficiency and high output LED. And is currently being used for depositing various thin films on a wafer such as a silicon film, an oxide film, a silicon nitride film or a silicon oxynitride film, a tungsten film, and the like.

In order to deposit a silicon carbide thin film on a substrate or a wafer, a reaction gas capable of reacting with the wafer must be introduced. For example, a raw material such as silane (SiH4), ethylene (C2H4) or methyltrichlorosilane (MTS), which is a standard precursor, is added and the raw material is heated to produce an intermediate compound such as CH3 or SiClx, Such an intermediate compound may be added to the deposition portion to react with the wafer positioned in the susceptor to deposit the silicon carbide epilayer.

When a single crystal silicon wafer is used as a substrate, the silicon is deposited in such a way as to sustain growth of the single crystal structure. At this time, when a substrate having a specific polarity (N-type or P-type) is to be manufactured, a predetermined doping gas is injected together with the epitaxial growth process.

At this time, a memory effect may occur. A memory effect is a phenomenon in which a doping gas introduced in the growth of an epitaxial layer forms a suspension in a low-flow region or a porous material in a chamber, and in the regrowth of an epitaxial layer, Lt; RTI ID = 0.0 > epitaxial < / RTI >

Embodiments provide an epitaxial wafer with improved memory effect and improved quality.

An embodiment provides an epitaxial wafer comprising N / P multiple layers having a desired dopant concentration.

The problems to be solved in the embodiments are not limited to these, and the objects and effects that can be grasped from the solution means and the embodiments of the problems described below are also included.

A method of manufacturing an epitaxial wafer according to an embodiment includes: preparing a wafer on a rotating plate of an epitaxial wafer manufacturing apparatus having epitaxial growth; And a step of epitaxially growing the epitaxial wafer manufacturing apparatus by injecting a reaction source including a growth gas, a doping gas, and a diluting gas into the epitaxial wafer manufacturing apparatus, wherein the step of preparing the wafer includes: Applying a silicon source, and coating the chamber N-type.

The step of bakeing the chamber may add heat to the chamber from 1500 ° C to 1950 ° C.

In the step of introducing the silicon source, silane (SiH ₄ ) may be introduced into the growth gas.

The step of N-type coating the chamber may introduce a growth gas into the chamber.

The growth gas may include a first growth gas and a second growth gas, and the ratio of the amount of the first growth gas to the amount of the second growth gas may be 1: 5.

The first growth gas may be C ₃ H ₈ and the second growth gas may be SiH ₄ .

The step of epitaxial growth includes repeatedly performing epitaxial growth, bake the chamber before the second epitaxial after the first epitaxial growth, inject the silicon source, and coat the chamber N-type can do.

According to the embodiment, an epitaxial wafer with improved memory effect can be manufactured.

Further, an epitaxial wafer including N / P plural layers having a desired dopant concentration can be produced.

The various and advantageous advantages and effects of the present invention are not limited to the above description, and can be more easily understood in the course of describing a specific embodiment of the present invention.

1 is a conceptual diagram of an epitaxial wafer manufacturing apparatus according to an embodiment of the present invention,
2 is a view for explaining another epitaxial wafer manufacturing method according to an embodiment of the present invention,
3 is a plan view of a rotating plate and a wafer,
4 is a conceptual view of a rotating plate,
5 is a graph for explaining the effect according to the embodiment,
6 is a view showing an epitaxial wafer according to an embodiment,
FIG. 7 is a graph showing the concentration according to the thickness of the epitaxial wafer in FIG. 6,
Fig. 8 is a modification of Fig.

The embodiments may be modified in other forms or various embodiments may be combined with each other, and the scope of the present invention is not limited to each embodiment described below.

Although not described in the context of another embodiment, unless otherwise described or contradicted by the description in another embodiment, the description in relation to another embodiment may be understood.

For example, if the features of configuration A are described in a particular embodiment, and the features of configuration B are described in another embodiment, even if the embodiment in which configuration A and configuration B are combined is not explicitly described, It is to be understood that they fall within the scope of the present invention.

In the description of the embodiments, in the case where one element is described as being formed "on or under" another element, the upper (upper) or lower (lower) or under are all such that two elements are in direct contact with each other or one or more other elements are indirectly formed between the two elements. Also, when expressed as "on or under", it may include not only an upward direction but also a downward direction with respect to one element.

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art can easily carry out the present invention.

1 is a conceptual diagram of an epitaxial wafer manufacturing apparatus according to an embodiment of the present invention.

1, an apparatus 100 for manufacturing an epitaxial wafer includes a plurality of rotating plates 120 including a receiving portion in which a wafer 10 is disposed, a main plate 110 supporting a plurality of rotating plates 120, A gas distributor 130 for injecting gas into the chamber 120 and a chamber 150 for receiving the turntable 12 and the plate 110.

The main plate 110 may be a circular plate having a predetermined area and may be rotated. A heater 140 may be disposed outside the main plate 110 to transmit heat to the main plate 110. The main plate 110 may have any structure of a general susceptor.

The plurality of rotary plates 120 are disposed on the main plate 110 and can rotate independently. The rotation plate 120 can receive the heat of the heater 140 through the main plate 110.

The gas distribution apparatus 130 may inject the reaction source onto the wafer 10. [ The reaction source may include a growth gas that is a source of epitaxial growth and a doping gas to perform doping in the growth process.

The doping gas may include a source gas corresponding to an element which is actually doped in the epitaxial layer to be deposited by epitaxial growth and a diluent gas (carrier gas) used for diluting or moving the source gas.

When the wafer 10 is a silicon carbide-based wafer (4H-SiC wafer), SiH ₄ + C ₃ H ₈ + H ₂ and MTS (CH ₃ SiCl ₃ ), TCS (SiHCl ₃ ), Si _x C _x, and the like can be used.

At this time, when the epitaxial layer to be laminated on the wafer is to be doped N-type, the source gas may be a material of a Group 5 element such as nitrogen gas (N ₂ ).

However, the present invention is not limited thereto, and the wafer 10 may be different depending on devices and products to be finally manufactured. Further, the reaction source may be different depending on the material and the type of the wafer to be laminated to the epitaxial layer.

In addition, the source gas to be involved in the actual doping may also be different depending on the type (N type or P type) to be doped. As an example, epitaxial doping growth can be performed on a silicon carbide based wafer using nitrogen gas as a source gas. At this time, hydrogen gas (H2) may be used as the diluent gas (carrier gas), but it is not limited thereto.

The chamber 150 may have a receiving portion where the deposition process of the epitaxial layer is performed. The rotating plate 120 and the main plate 110 may be disposed in the receiving portion. The chamber 150 may include openings at the top for entry and exit of the wafer. The opening of the chamber 150 may be sealed by a lead (not shown).

Generally, because the process within the chamber 150 is performed at a high temperature, the chamber 150 can include various materials and various shapes that can withstand high temperatures. The chamber 150 may include a gas outlet (not shown) for discharging the process gas after the process is finished to the outside. A gas outlet (not shown) may extend from the interior of the chamber 150 through the side or bottom surface and out of the chamber 150. However, the present invention is not limited to such a position. The chamber 150 may further include a pressure regulator (not shown) for regulating the internal pressure. A pressure regulator (not shown) may evacuate the interior of the chamber 150

2 is a view for explaining another epitaxial wafer manufacturing method according to an embodiment of the present invention.

Referring to FIG. 2, the method for manufacturing an epitaxial wafer according to the embodiment includes a preparation step of placing a wafer on a rotating plate of an epitaxial wafer production apparatus, and a step of epitaxial growth by injecting a reaction source into the epitaxial wafer production apparatus can do.

An epitaxial wafer fabrication method according to an embodiment may include any one of bake the chamber in the preparation step, inject the silicon source, and coat the chamber N-type.

First, the step of bakeing the chamber may be a step of applying a high temperature to the chamber before epitaxial growth. Here, the high temperature may be 1500 ° C to 1950 ° C. If it is lower than 1500 ° C, it may be difficult to remove scum, and when the temperature is higher than 1950 ° C, the protective layer formed in the chamber may be deteriorated.

The bake may be from 2 hours to 5 hours. In the case of smaller than 2 hours, the removal of suspended matters is insufficient, and there is a limit in which carbon (C) is excessively discharged when it is larger than 5 hours.

Also, the bake can be applied at a pressure of from 40 mbar to 200 mbar. If the pressure is less than 40 mbar, the removal of the float may be insufficient, and if the pressure is larger than 200 mbar, there is a limitation that the removal of the flotation on the wafer bottom is reduced. The flow can take place from 180l to 240l. The flow can be equally applied in the step before the epitaxial wafer is manufactured, but it is not limited thereto.

In the baking step, the growth gas may not be supplied. Thereby, parasitically grown silicon carbide in the chamber can be removed, and aluminum can be cracked and discharged. As such, the bake step can remove the memory effect by releasing parasitic growth suspended in the chamber.

The step of introducing the silicon source may be a step of injecting silane (SiH ₄ ) in the growth gas. The step of introducing silane (SiH ₄ ) may be performed for 5 minutes to 30 minutes. If the time is less than 5 minutes, the removal of the suspended matters is insufficient, and there is a problem that silane (SiH ₄ ) is overcoated by applying more than 30 minutes.

Further, the step of introducing silane (SiH ₄ ) may be performed at a pressure of 40 mbar to 200 mbar. If the pressure is less than 40 mbar, the removal of the float may be insufficient, and if the pressure is larger than 200 mbar, there is a limitation that the removal of the flotation on the wafer bottom is reduced.

The step of introducing silane (SiH ₄ ) may be performed at a rate of 10 sccm to 50 sccm of silane. If the flow rate is less than 10 sccm, the removal of suspended solids is insufficient, and when the flow rate is greater than 50 sccm, silane (SiH ₄ ) is over coated.

The step of introducing silane (SiH ₄ ) may be performed under the same pressure as in the above baking step.

The N-type coating of the chamber can include the step of introducing a growth gas into the chamber. For example, the step of N-type coating of the chamber may introduce a carbon source and a silicon source (silicon source) into the chamber. The carbon source (e.g., C ₃ H ₈ ) may be within 60 sccm, and the silicon source (e.g., SiH ₄ ) may be 300 sccm.

The step of N-type coating the chamber may be at a temperature of 1500 < 0 > C. A deviation of about 50 ° C may occur in the process. If the deviation is large, there arises a problem that the area where the N-type coating is made is varied and the coated N-type particles are separated.

Also, the step of N-type coating of the chamber may be subjected to a pressure of 200 mbar. A deviation of 20 mbar may occur in the process, and if the deviation is large, a deviation of the region where the N-type coating is formed may occur and the coated N-type particles may be separated.

The epitaxial growth step may include a preheating step S10, a growth step S20, and a cooling step S30. The preheating step S10 may be a primary heating to about 1000 degrees and a secondary heating to about 1500 to 1700 degrees. The primary heating may be a step of removing contaminants on the surface of the wafer 10. [

In the growth step S20, the epitaxial layer can be grown by injecting a reaction source containing a growth gas, a doping gas, and a diluting gas into a chamber adjusted to a temperature of about 1500 to 1700 degrees.

At this time, the concentration of the gas may be relatively low in the center of the wafer 10 due to the high rotation of the rotary plate 120. However, since the center of the wafer 10 contacts the central portion 121a of the bottom surface 121, the temperature may be relatively high.

Conversely, the edge of the wafer 10 may have a high gas concentration due to high-speed rotation. However, since the edge of the wafer 10 is spaced apart from the rim portion 121b of the bottom surface 121, the temperature may be relatively low. Thus, the center of the wafer 10 has a low gas concentration while the temperature is high, and the edge of the wafer 10 may have a high gas concentration and a low temperature. Thus, the edge can be cooled to make the thickness of the epitaxial layer grown at the center and the edge of the wafer 10 uniform. Thereafter, the chamber in which the growth is completed can be cooled to terminate the growth.

3 is a plan view of a rotating plate and a wafer, and Fig. 4 is a conceptual view of a rotating plate.

Referring to FIG. 3, the side wall 122 of the rotating plate 120 may include a plurality of protrusions 122a. The plurality of projections 122a can support the side surface of the wafer 10. [ In this case, since the contact area between the protrusion 122a and the side surface of the wafer 10 is small, the heat transfer efficiency can be reduced. Therefore, the heat applied to the edge of the wafer 10 can be minimized. The gas G1 may flow into the gap H1 between the plurality of projections 122a to cool the rim portion 121b of the bottom surface 121. However, the present invention is not limited thereto.

Referring to FIG. 4, when the rear surface of the wafer 10 is entirely in contact with the bottom of the rotating plate 120 (P1), the entire surface of the wafer 10 may be heated to activate the reaction. However, the concentration of the gas may be higher on the outer side than the center of the rotary plate 120 due to rotation of the rotary plate 120 or the like. Therefore, when the entire surface of the wafer 10 is heated, the thickness of the epitaxial layer 3 becomes thicker at the edge 3a. In this case, as described above, the side wall 122 of the rotation plate 120 may form the protrusion 122a on the side wall.

5 is a graph for explaining an effect according to the embodiment.

In Table 1 below, B to E in FIG. 5 represent the concentrations of the dopants of the respective N-type layers in the epitaxial wafers manufactured according to the first to fourth embodiments, and A is the epitaxial wafer manufactured according to the comparative example The concentration of the dopant in the N-type layer in the wafer. (In FIG. 5, the x-axis represents each time the experiment is performed, and the y-axis represents the doping concentration of the n-type layer)

Minimum dopant concentration Maximum dopant concentration Comparative Example 1 (A) 0.5E10 ¹⁵ 2.9E10 ¹⁵ Example 1 (B) 3.6E10 ¹⁵ 4.3E10 ¹⁵ Example 2 (C) 3.8E10 ¹⁵ 4.5E10 ¹⁵ Example 3 (D) 4.2E10 ¹⁵ 4.8E10 ¹⁵ Example 4 (E) 4.7E10 ¹⁵ 4.9E10 ¹⁵

Comparative Example 1 is a step of bakeing the chamber in the preparation step of the epitaxial wafer fabrication method according to the embodiment, introducing the silicon source, and growing the epitaxial layer without the N-type coating step .

Comparative Example 1 measured the doping concentration of the N-type layer when the epitaxial layer was regrowthed. Before re-growth, a 4H-SiC semiconductor substrate was mounted on a susceptor, and the inside of the chamber was set to a vacuum atmosphere, and 210 L of hydrogen gas was flowed to adjust the pressure to 80 mbar. The temperature of the chamber was raised to 1580 DEG C while maintaining the pressure constant. N 2 growth gas was supplied for 10 seconds, and dopant was supplied from 5 times to 0.1 sccm to 20 sccm. SiH4 of 100 ~ 250 sccm and C / Si ratio of 1.05 were selected. SiC epitaxial films were grown at a growth time of 1 hour. At the end of the growth, the supply of all the gases other than the H2 gas was stopped and the cooling was continued. The resulting SiC epitaxial wafer was measured for film thickness using an FT-IR apparatus and confirmed to be formed to a thickness of 11.8 μm. After the epitaxial layer growth, the dopant concentration of the N-type layer was evaluated by secondary ion mass spectroscopy (SIMS).

Example 1 performed the baking step in the preparation step of the epitaxial wafer manufacturing method. The baking step was performed for 2 hours, the temperature was 1700 占 폚, the pressure was 200 mbar, and the flow was 220 l.

Example 2 performed the step of injecting a silicon source in the preparation step of the epitaxial wafer manufacturing method. In the step of introducing the silicon source, a silicon source was introduced at 40 sccm. The other conditions are the same as those of the first embodiment.

Example 3 performed a step of N-type coating the chamber in the preparation step of the epitaxial wafer manufacturing method. The step of N-type coating of the chamber was carried out with C ₃ H ₈ of 60 sccm as a carbon source and 300 sccm of SiH ₄ as a silicon source.

Example 4 performed both the bake step in the preparation step of the epitaxial wafer manufacturing method, the step of injecting the silicon source, and the step of N-type coating the chamber.

Referring to Table 1, it was confirmed that the dopant concentration of the re-grown N-type layer in Examples 1 to 4 was 3E10 ¹⁵ or more. If contrast, the comparative example was confirmed that the dopant concentration of the N-type layer is minimum 0.5 E10 ^15. Thus, it can be confirmed that the step of bakeing, the step of applying the silicon source, and the step of N-type coating of the chamber in the preparation step of the epitaxial wafer fabrication method are very effective methods of removing the memory effect.

FIG. 6 is a view showing an epitaxial wafer according to the embodiment, FIG. 7 is a view showing the concentration according to the thickness of the epitaxial wafer in FIG. 6, and FIG. 8 is a modification of FIG.

6, the epitaxial wafer manufactured by the epitaxial wafer manufacturing method according to the embodiment includes a semiconductor substrate 11, a buffer layer 12 disposed on the semiconductor substrate 11, and a buffer layer 12 disposed on the buffer layer 12 (13, 14). Hereinafter, the epitaxial layers 13 and 14 are the N-type layer 13 and the P-type layer 14, respectively.

First, the semiconductor substrate 11 may be a silicon carbide type wafer (4H-SiC wafer), so that the epilayers 13 and 14 may also be formed of a doped silicon carbide series.

When the semiconductor substrate 11 is silicon carbide (SiC), the epitaxial layers 13 and 14 may all be formed of an n-type conductive silicon carbide system, that is, silicon carbide nitride (SiCN).

In this case, the growth gas may include a material capable of lattice constant matching with the semiconductor substrate.

As the growth gas, materials including carbon and silicon such as SiH ₄ + C ₃ H ₈ , MTS (CH ₃ SiCl ₃ ), TCS (SiHCl ₃ ), SixCx and the like can be used. The growth gas may be, but is not necessarily limited to, SiH ₄ or C ₃ H ₈ . Illustratively, the growth gas may comprise a first growth gas and a second growth gas, wherein the first growth gas is C ₃ H ₈ and the second growth gas may be SiH ₄ . The first growth gas may be a carbon source, and the second growth gas may be a silicon source.

The doping gas may be a substance of a Group 5 element such as nitrogen gas (N2) when the epitaxial layers 13 and 14 to be laminated on the wafer are to be doped to N type (N type). As the diluent gas (carrier gas), hydrogen gas (H2) may be used, but not always limited thereto.

However, the epitaxial layers 13 and 14 may be formed of p-type conductive silicon carbide type, that is, aluminum silicon carbide (AlSiC).

The off-angle of the semiconductor substrate 11 may be 3 degrees to 10 degrees. Here, the off-angle can be defined as an angle at which the semiconductor substrate 11 is tilted with respect to the (0001) Si plane and the (000-1) C plane.

The doping concentration of the semiconductor substrate 11 is 1 × 10 ¹⁸ cm ^- may be a ³ to 1 × 10 ²⁰ cm ^-3, but not necessarily limited to this. The doping concentration of the semiconductor substrate 11 may be constant in the thickness direction, but is not necessarily limited thereto. Hereinafter, the doping concentration may be the same as the doping concentration of each layer.

The buffer layer 12 may be disposed on the semiconductor substrate 11. The doping concentration of the buffer layer 12 may vary in the thickness direction, but the present invention is not limited thereto. The doping concentration of the buffer layer 12 may vary. For example, the doping concentration of the buffer layer 12 may vary from a minimum concentration to a peak concentration. Here, the minimum concentration may be 5 × 10 ¹⁷ cm ^-3 and the peak concentration may be 7 × 10 ¹⁸ cm ^-3 . If the minimum concentration is smaller than 5 × 10 ¹⁷ cm ^-3 or the peak concentration is larger than 7 × 10 ¹⁸ cm ^-3 , it may be difficult to effectively mitigate the lattice mismatch between the semiconductor substrate 11 and the epilayers 13 and 14 .

The epilayers 13 and 14 may be formed on the buffer layer 12 after the buffer layer 12 is formed and after the annealing process. At this time, the epitaxial layers 13 and 14 may have a uniform doping concentration in the thickness direction, but are not limited thereto. The doping concentration of the epi layers 13 and 14 may be smaller than the doping concentration of the semiconductor substrate 11 and the doping concentration of the buffer layer 12,

The epilayers 13 and 14 may be disposed on the buffer layer 12. The doping concentration of the epitaxial layers 13 and 14 may be 1 x 10 ¹⁵ cm ^-3 to 5 x 10 ¹⁸ cm ^-3 . The doping concentration of the epilayers 13 and 14 may vary in the thickness direction. Illustratively, the doping concentration may increase or decrease in the thickness direction.

At this time, when the epilayers 13 and 14 are formed on the semiconductor substrate 11, the base potential present in the semiconductor substrate can be propagated to the epilayers 13 and 14. [ Therefore, it may be preferable to convert the base surface potential formed on the semiconductor substrate 11 to the blade potential when it propagates to the epilayers 13 and 14. [

A layer (not shown) having a large difference in doping concentration from the semiconductor substrate 11 is formed between the semiconductor substrate 11 and the epi layers 13 and 14 in order to terminate the underlying surface potential present in the semiconductor substrate 11 The base surface potential of the semiconductor substrate can be converted into the blade potential.

And the average doping concentration of the epi layers 13 and 14 may be smaller than the average doping concentration of the buffer layer 12. [ The epilayers 13 and 14 and the buffer layer 12 may have the same composition (SiC).

An epitaxial wafer according to an embodiment may be applied to a metal semiconductor field effect transistor (MESFET). For example, a field effect transistor (MOSFET) can be fabricated by forming an ohmic contact layer comprising a source and a drain over an epitaxial layer according to the present invention. The present invention can be applied to various semiconductor devices.

Referring to FIG. 7, in regrowing the epitaxial layer after the epitaxial layer growth, the epitaxial wafer manufactured by the epitaxial wafer manufacturing method according to the embodiment has a depth of 2 to 13 An n-type (n-type) epitaxial layer can be formed. The N-type epitaxial layer shows that the doping concentration of nitrogen (N) is 5E10 ^15, and the memory effect is removed. However, the length of the N-type epi layer may be varied in various ways. (Where depth means the length from the top layer to the bottom layer of the epitaxial wafer).

8, the epitaxial wafer includes a semiconductor substrate 11, a buffer layer 12 disposed on the semiconductor substrate 11, and first epitaxial layers 13 and 14 disposed on the buffer layer 12, And a second epilayer (15, 16) formed on the first epilayers (13, 14). The first epilayers 13 and 14 are composed of an N-type layer 13 and a P-type layer 14 and the second epilayers 15 and 16 are composed of an N-type layer 15 and a P- 16).

In this case, after the first epilayers 13 and 14 are formed, either the step of bakeing, the step of applying the silicon source and the step of N-coating the chamber are performed, and then the second epilayers 15, 16 can be formed.

Thereby, the memory effect can be removed from the N-type layer 15 in the second epilayers 15, 16 as described above.

While the present invention has been particularly shown and described with reference to exemplary embodiments thereof, it is to be understood that the invention is not limited to the disclosed exemplary embodiments, but, on the contrary, It will be understood that various modifications and applications are possible. For example, each component specifically shown in the embodiments can be modified and implemented. It is to be understood that all changes and modifications that come within the meaning and range of equivalency of the claims are therefore intended to be embraced therein.

Claims (7)

Preparing a wafer on a rotating plate of an epitaxial wafer manufacturing apparatus subjected to epitaxial growth; And
The epitaxial wafer manufacturing apparatus is provided with a growth gas, a doping gas, and a diluting gas
And a step of epitaxially growing the reaction source by injecting the reaction source,
The step of arranging the wafer includes:
A step of bakeing the chamber, a step of introducing a silicon source, and an N-type coating of the chamber.
The method according to claim 1,
Wherein the step of bakeing the chamber applies heat to the chamber at 1500 占 폚 to 1950 占 폚.
The method according to claim 1,
Wherein the step of introducing the silicon source comprises introducing silane (SiH ₄ ) in the growth gas.
The method according to claim 1,
Wherein the N-type coating of the chamber comprises introducing a growth gas into the chamber.
5. The method of claim 4,
The growth gas includes a first growth gas and a second growth gas,
Wherein the ratio of the amount of the first growth gas to the amount of the second growth gas is 1: 5.
6. The method of claim 5,
Wherein the first growth gas is C ₃ H ₈ and the second growth gas is SiH ₄ .
The method according to claim 1,
The epitaxial growth step is a step in which the epitaxial growth is repeatedly performed,
Bake the chamber before the second epitaxial after the first epitaxial growth, inject a silicon source, and perform N-type coating of the chamber.

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