KR20070025715A - Internal clock generating circuit - Google Patents

Abstract

An internal clock generation circuit is provided to prevent unnecessary current consumption due to toggling of an internal clock, by generating the internal clock only in a period requiring the internal clock when a chip selection signal is disabled. An internal clock generation control part(200) receives an external clock and a clock generation control signal, and controls the generation of an internal clock in response to the clock generation control signal. An internal clock generation part(400) is controlled by the internal clock generation control part and generates at least one internal clock. The clock generation control signal is enabled during an enable period of a chip selection signal and during at least an active operation period even when the chip selection signal is disabled, and the internal clock generation part generates at least one internal clock when the clock generation control signal is enabled.

Description

Internal Clock Generating Circuit

1 schematically shows a configuration of an internal clock generation circuit according to the prior art.

2 illustrates a configuration of an internal clock generation circuit according to an embodiment of the present invention.

3 shows a configuration of a control signal generator used in the internal clock generation circuit according to the present embodiment.

4 is a waveform diagram of signals at each node of the periodic signal generator used in the control signal generator according to the present embodiment.

Figure 5 shows a comparison of the simulation results of the internal clock generation circuit according to the prior art and this embodiment.

The present invention relates to an internal clock generation circuit. More specifically, when the chip select signal is disabled, the internal clock is generated only in a section where an actual internal clock is required, such as when the semiconductor device is active. An internal clock generation circuit can reduce current consumption by preventing unnecessary toggling.

In order to further speed up the operation speed of a semiconductor memory device, which has gradually increased in capacity, a synchronous semiconductor memory device which operates in synchronization with a system clock supplied from a memory controller has been proposed. In the case of the asynchronous semiconductor memory device, the internal circuits are enabled according to the row address strobe and the column address strobe to perform read / write operations without requiring the input of the system clock. In the case of the synchronous semiconductor memory device, the system clock is performed. The internal circuits are synchronized with each other to achieve high speed operation more than asynchronous operation. In addition, the ultra-high speed of the central processing unit (CPU) has required more synchronous semiconductor memory device, the development trend is now reaching the ultra-fast synchronous semiconductor memory device such as Double Data Rate (DDR) or Rambus DRAM.

On the other hand, the synchronous semiconductor memory device is operated in synchronization with the system clock, the system clock is used by changing the internal clock to be used in the internal circuits of the semiconductor memory device, the internal clock generator (internal clock generator) is used for this purpose do.

1 schematically shows a configuration of an internal clock generation circuit according to the prior art. As illustrated in FIG. 1, in the internal clock generation circuit of a conventional semiconductor device, an internal clock is applied to the external clock generator 100 to generate a plurality of internal clocks int_clk1, int_clk2, and int_clk3. In this process, the conventional internal clock generation circuit is configured to continuously generate the internal clock regardless of whether it is chip selected or chip deselected. That is, the conventional internal clock generation circuit continuously generates the internal clock regardless of whether the chip select signal (chip select, / cs) indicating whether or not the chip selection state is enabled or disabled. Accordingly, although the clock is not actually needed inside the chip, unnecessary current consumption is continuously generated because the internal clock always toggles. This is a significant disadvantage for devices where current is an important factor in product performance, such as low power DRAMs and mobile DRAMs.

Therefore, the technical problem to be achieved by the present invention is that when the chip select signal is disabled, the internal clock is generated only in a section in which the actual internal clock is required, such as when the semiconductor device is active, and thus the chip select signal is disabled. In the present invention, there is provided an internal clock generation circuit that prevents unnecessary consumption of current generated due to generation and toggling of an internal clock even when the semiconductor device is not in an active operation.

In order to achieve the above technical problem, the present invention includes an internal clock generation control unit for receiving an external clock and a predetermined clock generation control signal, and controls the generation of the internal clock in response to the clock generation control signal; And an internal clock generator configured to be controlled by the internal clock generation controller to generate at least one internal clock, wherein the clock generation control signal includes at least an active operation even when the chip selection signal is enabled and the chip selection signal is disabled. Enabled in the interval, the internal clock generation unit provides an internal clock generation circuit, characterized in that for generating at least one internal clock when the clock generation control signal is enabled.

The internal clock generation controller may control generation of the internal clock by determining whether the external clock is output according to the clock generation control signal.

In the present invention, the internal clock generation control unit includes a first buffer for buffering the external clock; A logic unit configured to logically operate the clock generation control signal and a first voltage having a predetermined level; It is preferably configured to include a second buffer for buffering the output signal of the first buffer in response to the output signal of the logic unit.

In the present invention, the first voltage is a ground voltage, and the logic unit preferably performs a negative logic sum operation.

In the present invention, it is preferable that the first buffer is an inverter, and the second buffer is a tri-state inverter that operates in response to an output signal of the logic unit.

In the present invention, it is preferable that the internal clock generation control unit further includes pull-down means for driving the output terminal of the internal clock generation control unit to a ground voltage level in response to an output signal of the logic unit.

The present invention also provides a control signal generator for receiving a plurality of control signals and outputting a clock generation control signal enabled at least in an active operation section even when the chip select signal is enabled and the chip select signal is disabled. ; An internal clock generation control unit which receives an external clock and the clock generation control signal and controls generation of an internal clock in response to the clock generation control signal; An internal clock generation circuit configured to be controlled by the internal clock generation control unit to generate an internal clock is provided.

In the present invention, the plurality of control signals input to the control signal generation unit may include a first control signal, a chip select signal, and a las idle signal that are enabled for a predetermined period when a read or write command is input to ensure a burst operation It is preferable to include (rasidle).

In the present invention, the control signal generation unit receives the first control signal and the chip select signal, and a first block for enabling the clock generation control signal during at least a burst operation period; When the first control signal, the chip select signal, and the lath idle signal are input, and the chip select signal is disabled in a row, the clock generation control signal is passed after a predetermined interval has elapsed from this time point. A second block for disabling; And a first logic unit configured to perform a logic operation on the signal from the common output terminal of the first block and the second block and the chip select signal to output the clock generation control signal.

In the present invention, the control signal generation unit preferably further includes a latch unit for latching a signal from the common output terminal and simultaneously buffering and supplying the signal to the first logic unit.

In the present invention, the first block is buffered by the chip select signal to buffer the first control signal; And a pull-up means for pull-up driving the common output stage in response to an output signal of the buffer.

In the present invention, the first block preferably further includes potential holding means for maintaining the potential of the output terminal of the buffer at an external voltage level in response to the chip select signal.

In the present invention, the buffer is preferably a tri-state inverter that is controlled and operated by the chip select signal.

In the present invention, the second block is controlled by a lath idle signal, the periodic signal generator for receiving the external clock and outputs a second control signal that is periodically enabled for a predetermined period; A signal transfer unit controlled by the second control signal to transfer the chip selection signal after a predetermined period has passed; A first buffer for buffering the lath idle signal; A second buffer controlled by the output signal of the signal transfer unit and buffering the output signal of the first buffer; And a pull-down means for pull-down driving the common output terminal in response to the output signal of the second buffer.

In the present invention, the periodic signal generation unit and a third buffer for buffering the external clock; A tree state buffer controlled by the lath idle signal to buffer an output signal of the third buffer; A delay unit delaying an output signal of the tristate buffer by a predetermined period; And a second logic unit for performing a logic operation on the output signal of the tristate buffer and the output signal of the delayer.

In the present invention, the second logic unit preferably performs a negative AND operation.

In the present invention, the signal transfer unit is controlled by the second control signal and the first tri-state buffer for buffering the chip select signal; And a second tree state buffer controlled by the second control signal to buffer the output signal of the first tree state buffer, wherein the second tree state buffer is turned on when the first tree state buffer is turned on. It is characterized in that the off.

In the present invention, the signal transfer unit is controlled by the second control signal and a third tree state buffer for buffering the output signal of the second tree state buffer; And a fourth tree state buffer controlled by the second control signal to buffer the output signal of the third tree state buffer, wherein the fourth tree state buffer is turned on when the third tree state buffer is turned on. -Off.

In the present invention, it is preferable that the signal transmission unit further includes a potential holding means for maintaining the output terminal of the first tristate buffer at a predetermined voltage level in response to the lath idle signal.

In the present invention, the first buffer and the second buffer is preferably a tristate inverter.

In the present invention, it is preferable that the second block further includes a potential holding means that is controlled by an output signal of the signal transfer unit to maintain the output terminal of the second buffer at a predetermined voltage level.

In the present invention, it is preferable that the second block further includes pull-down means for pull-down driving the output terminal of the first buffer in response to the lath idle signal.

In the present invention, the first logic unit preferably performs an AND operation.

The internal clock generation controller may control generation of the internal clock by determining whether the external clock is output according to the clock generation control signal.

In the present invention, the internal clock generation control unit includes a first buffer for buffering the external clock; A logic unit configured to logically operate the clock generation control signal and a first voltage having a predetermined level; It is preferably configured to include a second buffer for buffering the output signal of the first buffer in response to the output signal of the logic unit.

In the present invention, the first voltage is a ground voltage, and the logic unit preferably performs a negative logic sum operation.

In the present invention, it is preferable that the first buffer is an inverter, and the second buffer is a tree state inverter that operates in response to an output signal of the logic unit.

In the present invention, it is preferable that the internal clock generation control unit further includes pull-down means for driving the output terminal of the internal clock generation control unit to a ground voltage level in response to an output signal of the logic unit.

Hereinafter, the present invention will be described in more detail with reference to Examples. These examples are only for illustrating the present invention, and the scope of protection of the present invention is not limited by these examples.

2 illustrates a configuration of an internal clock generation circuit according to an embodiment of the present invention, and FIG. 3 illustrates a configuration of a control signal generation unit used in the internal clock generation circuit according to the present embodiment. The present invention will be described as follows.

As shown, the internal clock generation circuit according to the present embodiment receives a plurality of control signals (/ cs, rasidle, casp6), the section and the chip select signal (/ cs) enabled the chip select signal (/ cs) A control signal generator 300 for outputting a clock generation control signal en_csb that is enabled in at least an active operation period, even if? An internal clock generation control unit 200 which receives an external clock ext_clk and the clock generation control signal en_csb and controls generation of an internal clock in response to the clock generation control signal en_csb; And an internal clock generation unit 400 controlled by the internal clock generation control unit 200 to generate internal clocks int_clk1, int_clk2, and int_clk3.

The control signal generation unit 300 receives a control signal casp6 and a chip selection signal / cs and receives the first block 310 for enabling the clock generation control signal en_csb for at least a burst operation period; When a control signal casp6 and a ras idle signal are received and the ras idle signal is enabled at a high level while the chip select signal / cs is disabled, a predetermined section passes from this point in time. A second block 320 for disabling the clock generation control signal en_csb; A latch unit 330 for latching a signal from the common output terminal A of the first block 310 and the second block 320 and inverting and outputting the buffer; And a logic unit 340 for performing an AND operation on the signal from the latch unit 330 and the chip select signal / cs to output a clock generation control signal en_csb.

The first block 310 includes: a tristate inverter TSI21 controlled by the chip select signal / cs to invert a buffered control signal casp6; And a PMOS P22 for pull-up driving the common output terminal A in response to the output signal of the tristate inverter TSI21.

The second block 320 is operated by a ras idle signal rasidle, but receives the external clock ext_clk and outputs a control signal pclk periodically enabled for a predetermined period (a periodic signal generator) 321; A signal transfer unit 323 controlled by a control signal pclk to transfer the chip selection signal / cs after a predetermined period has elapsed; A tri-state inverter (TSI31) controlled by a control signal (casp6) to invert the buffered ras idle signal (rasidle); A tri-state inverter (TSI32) controlled by the output signal of the signal transfer unit (323) to invert the buffered output signal of the tri-state inverter (TSI31); And a NMOS N33 for pull-down driving the common output terminal A in response to the output signal of the tristate inverter TSI32.

The internal clock generation control unit 200 includes an inverter IV11 for inverting and buffering the external clock ext_clk; A NOR gate NR11 for performing a negative logic sum operation on the clock generation control signal en_csb and the ground voltage; And a tristate inverter TSI11 which inverts the output signal of the inverter IV11 in response to the output signal of the NOR gate NR11.

The operation of the internal clock generation circuit according to the present embodiment configured as described above will be described in detail according to each operation mode of the semiconductor device.

First, the operation in the chip seleted state will be described. At this time, the chip select signal / cs is enabled at a low level. Therefore, since the low level chip select signal / cs is input from the control signal generator 300 of FIG. 3 to one end of the logic unit 340, the clock generation control signal en_csb is low by the AND operation. Level. At this time, since the tree state inverter TSI51 of the logic unit 340 operates in synchronization with the external clock ext_clk, the clock generation control signal en_csb is output in synchronization with it.

The NOR gate NR11 of the internal clock generation control unit 200 of FIG. 2 receives a low level clock generation control signal en_csb and a ground voltage and performs a negative logic sum operation to output a high level signal. Accordingly, the tristate inverter TSI11 is turned on and the external clock ext_clk is buffered and input to the internal clock generator 400, and the internal clock generator 400 receives the plurality of internal clocks int_clk1,. Create and output int_clk2, int_clk3). As described above, when the chip select signal is in a chip seleted state, that is, when the chip select signal / cs is enabled at a low level, the internal clock generation circuit according to the present embodiment receives an external clock ext_clk. Generate a plurality of internal clocks (int_clk1, int_clk2, int_clk3).

Next, referring to the operation of the internal clock generation circuit in the chip deselected state, the internal clock generation circuit according to the embodiment of the present invention has at least an internal clock in the active operation period even if the chip select signal is disabled. Since the internal clock is not generated in other cases, the semiconductor device such as DRAM can perform a normal operation and reduce current consumption due to internal clock generation. This will be described below.

In the chip deseleted state, the chip select signal / cs is disabled to a high level. Accordingly, since the high level chip select signal / cs is input from the control signal generator 300 of FIG. 3 to one side of the logic unit 340, the clock generation control signal en_csb is received from the latch unit 330. Whether to enable or disable depends on the level of the input signal.

First, even in a chip deseleted state, an internal clock is required to perform a normal burst operation such as burst read or burst write in the active operation period. Here, the active operation refers to an operation section in which a substantial operation is performed in the semiconductor device such as a data read or write operation and an auto precharge operation.

In order to perform the normal burst operation in the active operation period, the first block 310 of the control signal generator 300 enables the clock generation control signal en_csb to be enabled at least during the burst operation period. That is, when the chip select signal / cs becomes high level, the tree state inverter TSI21 is turned on, and the control signal casp6 is buffered by the inverter IV22 and the inverter IV23 and then the tristate inverter ( It is inverted by the TSI21 and input to the gate of the PMOS P22. Here, the control signal casp6 is a signal that is enabled at a high level for a predetermined period to secure a burst operation when a read or write command is input, and is a signal that enables data read or write during the burst operation period.

Therefore, when the chip select signal / cs is at the high level and the tree state inverter TSI21 is turned on, when the control signal casp6 is enabled at the high level to secure the burst operation, the PMOS P22 is enabled. The low level signal is applied to the gate and turned on. Accordingly, since the node A is driven at a high level and the signal output from the latch unit 330 is at a low level, the clock generation control signal en_csb output from the logic unit 340 is low as in the chip selection state. The level is enabled. In addition, since the tristate inverter TSI11 of the internal clock generation control unit 200 is in a turn-on state, the internal clock generation unit 400 generates the internal clocks int_clk1, int_clk2, and int_clk3. Here, the latch unit 330 keeps the node A at the high level in the previous state even if the control signal casp6 is subsequently disabled to the low level and the PMOS P22 is turned off. The clock generation control signal en_csb is kept at a low level until the internal clock generation unit 400 continuously outputs the internal clocks int_clk1, int_clk2, and int_clk3.

Subsequently, when the radar idle signal rasdle is transitioned from the low level to the high level, the tri-state inverter TSI41 is turned on and the external clock ext_clk is turned on by the periodic signal generator 321 of FIG. 3. And buffered by the tri-state inverter TSI41 so that the signal of the node B1 becomes as shown in FIG. In addition, the signal of the node B2 by the delay 322 is as shown in FIG. The NAND gate ND41 negatively combines the signal of the node B1 with the signal of the node B2 and outputs a control signal pclk. The control signal pclk is delayed as shown in FIG. 4. It is enabled to the low level periodically during the period corresponding to the delay period by the device 322. In the above, the ras idle signal is a signal that is activated at a low deactivation command and is enabled at a high level.

The signal transfer unit 323 is controlled by the control signal pclk and transmits the chip select signal / cs to the tristate inverter TSI32 after a predetermined period has elapsed. In detail, the PMOS P41 and the PMOS 42 which hold the node C1 and the node C2 at the high level when the radar idle signal is enabled at the low level are connected to the raid signal. rasidle) is turned off as high level is disabled. When the control signal pclk is first transitioned to the low level after the rasidle signal has been transitioned to the high level, the tristate inverter TSI42 and the tristate inverter TSI44 are turned on and the tristate inverter ( The TSI43 and the tristate inverter TSI45 are turned off. Accordingly, the chip select signal / cs is transmitted to the input terminal of the tristate inverter TSI43 via the tristate inverter TSI42 and the inverter IV45. Subsequently, when the control signal pclk transitions from the low level to the high level, the tristate inverter TSI42 and the tristate inverter TSI44 are turned off and the tristate inverter TSI43 and the tristate inverter TSI45 are turned off. -On. Accordingly, the chip select signal / cs is transmitted to the input terminal of the tristate inverter TSI44 via the tristate inverter TSI43 and the inverter IV46.

When the control signal pclk transitions to the second low level again, the tristate inverter TSI42 and the tristate inverter TSI44 are turned on, and the tristate inverter TSI43 and the tristate inverter TSI45 are turned off. do. Accordingly, the chip select signal / cs is transmitted to the input terminal of the tristate inverter TSI45 via the tristate inverter TSI44 and the inverter IV47.

Finally, when the control signal pclk transitions back to the high level, the tristate inverter TSI42 and the tristate inverter TSI44 are turned off, and the tristate inverter TSI43 and the tristate inverter TSI45 are turned off. Is on. Accordingly, the chip select signal / cs is input to the control terminal of the tristate inverter TSI32 via the tristate inverter TSI45 and the inverter IV48. At this time, since the chip select signal / cs is at a high level, the tristate inverter TSI32 is turned on.

On the other hand, at this time, since the ras idle signal is high level, the NMOS N31 is turned on and the node D1 becomes low level, so the output signal of the tristate inverter TSI32 becomes high level. Accordingly, since the NMOS N33 is turned on and the node A is at a low level, and the signal output from the latch unit 330 is at a high level, the clock generation control signal output from the logic unit 340 ( en_csb) goes high level. Next, since the NOR gate NR11 of the internal clock generation control unit 200 of FIG. 2 outputs a low level signal, the tristate inverter TSI11 is turned off so that the external clock ext_clk is the internal clock generation unit 400. Do not supply Accordingly, the internal clock generator 400 does not receive the external clock ext_clk and stops generating the internal clock. At this time, the NMOS N11 is turned on in response to the high level signal from the inverter IV12 to drive the node X to the ground level.

As a result, in the internal clock generation circuit according to the present embodiment, the control signal generator 300 deactivates the row while the chip select signal / cs is disabled, that is, the ras idle signal is raised to a high level. When enabled, the internal clock is generated until a time of about 2 clk has elapsed from this point, so that the auto precharge operation can be performed smoothly, and data after the read or write operation is sufficient at the input / output terminal (DQ stage). Allow input and output processing. In addition, the internal clock generation circuit according to the present embodiment prevents the internal clock from being generated after the interval has elapsed in the chip deselect state, thereby preventing unnecessary current consumption due to toggling of the internal clock. . FIG. 5 is a comparison of simulation results of the internal clock generation circuit according to the prior art and the present embodiment. As illustrated, the internal clock generation circuit according to the present embodiment has an internal clock for a section in which the internal clock is not actually required. It is not generated, reducing current consumption.

As described above, the internal clock generation circuit according to the present embodiment basically prevents the internal clock from being generated when the chip select signal is disabled, thereby preventing unnecessary current consumption due to toggling of the internal clock. Of course, the internal clock generation circuit according to the present embodiment requires an internal clock at least in an active operation section even if the chip select signal is disabled. Allow normal operation.

As described above, in the internal clock generation circuit according to the present invention, when the chip selection signal is disabled, the internal clock is generated only in a section in which the actual internal clock is required, such as when the semiconductor device is active. Although the semiconductor device is not in an active operation in the disabled state, it is possible to prevent unnecessary consumption of current generated due to the generation of the internal clock and toggling.

Claims (28)

An internal clock generation control unit which receives an external clock and a predetermined clock generation control signal and controls generation of an internal clock in response to the clock generation control signal; And an internal clock generation unit controlled by the internal clock generation control unit to generate at least one internal clock. The clock generation control signal is enabled in at least an active operation period even when the chip select signal is enabled and the chip select signal is disabled, and the internal clock generator is at least one internally generated when the clock generation control signal is enabled. And an internal clock generating circuit which generates a clock. The method of claim 1, And the internal clock generation control unit controls generation of the internal clock by determining whether the external clock is output according to the clock generation control signal. The method of claim 2, The internal clock generation control unit A first buffer buffering the external clock; A logic unit configured to logically operate the clock generation control signal and a first voltage having a predetermined level; And a second buffer configured to buffer an output signal of the first buffer in response to an output signal of the logic unit. The method of claim 3, wherein And the first voltage is a ground voltage, and the logic unit performs a negative logic sum operation. The method of claim 3, wherein The first buffer is an inverter, and the second buffer is a tri-state inverter that operates in response to an output signal of the logic unit. The method of claim 3, wherein The internal clock generation controller And a pull-down means for driving an output terminal of the internal clock generation control unit to a ground voltage level in response to an output signal of the logic unit. A control signal generator which receives a plurality of control signals and outputs a clock generation control signal enabled in at least an active operation section even when the chip select signal is enabled and the chip select signal is disabled; An internal clock generation control unit which receives an external clock and the clock generation control signal and controls generation of an internal clock in response to the clock generation control signal; And an internal clock generation unit controlled by the internal clock generation control unit to generate an internal clock. The method of claim 7, wherein The plurality of control signals input to the control signal generator may include a first control signal, a chip selection signal, and a ras idle signal that are enabled for a predetermined period when a read or write command is input to secure a burst operation. Internal clock generation circuit comprising. The method of claim 8, The control signal generator A first block receiving the first control signal and the chip selection signal and enabling the clock generation control signal for at least a burst operation period; When the first control signal, the chip select signal, and the las idle signal are input, and the row select is disabled while the chip select signal is disabled, the clock generation control signal is removed after a predetermined period has elapsed from this point in time. A second block to enable; And a first logic unit configured to perform a logic operation on a signal from a common output terminal of the first block and the second block and the chip select signal to output the clock generation control signal. The method of claim 9, And the control signal generator further includes a latch unit for latching a signal from the common output terminal and simultaneously buffering and supplying the signal to the first logic unit. The method of claim 9, The first block is A buffer controlled by the chip select signal to buffer the first control signal; And pull-up means for pull-up driving the common output terminal in response to an output signal of the buffer. The method of claim 11, wherein And the first block further comprises potential holding means for maintaining the potential of the output terminal of the buffer at an external voltage level in response to the chip select signal. The method of claim 11, wherein And the buffer is a tree state inverter that is controlled and controlled by the chip select signal. The method of claim 9, The second block is A periodic signal generator configured to be controlled by a lath idle signal and to receive the external clock and output a second control signal that is periodically enabled for a predetermined period; A signal transfer unit controlled by the second control signal to transfer the chip selection signal after a predetermined period passes; A first buffer for buffering the lath idle signal; A second buffer controlled by an output signal of the signal transfer unit to buffer an output signal of the first buffer; And pull-down means for pull-down driving the common output terminal in response to an output signal of the second buffer. The method of claim 14, The periodic signal generation unit A third buffer buffering the external clock; A tree state buffer controlled by the lath idle signal to buffer an output signal of the third buffer; A delay unit delaying an output signal of the tristate buffer by a predetermined period; And a second logic unit configured to logically output the output signal of the tristate buffer and the output signal of the delayer. The method of claim 15, And the second logic unit performs an AND logic operation. The method of claim 14, The signal transmission unit A first tristate buffer controlled by the second control signal to buffer the chip select signal; A second tree state buffer controlled by the second control signal to buffer an output signal of the first tree state buffer, And the second tristate buffer is turned off when the first tristate buffer is turned on. The method of claim 17, The signal transmission unit A third tree state buffer controlled by the second control signal to buffer an output signal of the second tree state buffer; And a fourth tree state buffer controlled by the second control signal to buffer the output signal of the third tree state buffer. And the fourth tristate buffer is turned off when the third tristate buffer is turned on. The method of claim 17, The signal transmission unit And potential holding means for maintaining an output terminal of the first tristate buffer at a predetermined voltage level in response to the lath idle signal. The method of claim 14, And the first buffer and the second buffer are tree state inverters. The method of claim 14, And the second block further includes a potential holding means for controlling the output terminal of the second buffer at a predetermined voltage level by being controlled by an output signal of the signal transfer unit. The method of claim 14, And the second block further comprises pull-down means for pull-down driving the output stage of the first buffer in response to the lath idle signal. The method of claim 9, And the first logic unit performs an AND operation. The method of claim 7, wherein And the internal clock generation control unit controls generation of the internal clock by determining whether the external clock is output according to the clock generation control signal. The method of claim 24, The internal clock generation control unit A first buffer buffering the external clock; A logic unit configured to logically operate the clock generation control signal and a first voltage having a predetermined level; And a second buffer configured to buffer an output signal of the first buffer in response to an output signal of the logic unit. The method of claim 25, And the first voltage is a ground voltage, and the logic unit performs a negative logic sum operation. The method of claim 25, The first buffer is an inverter, and the second buffer is a tree state inverter operating in response to an output signal of the logic unit. The method of claim 25, The internal clock generation controller And a pull-down means for driving an output terminal of the internal clock generation control unit to a ground voltage level in response to an output signal of the logic unit.

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