KR20000061550A - Data Transmission and Reception Device for channel capacity increase(Trubitsin's scheme for channel capacity increase) - Google Patents

Abstract

The present invention relates to a data transmission / reception apparatus for use in transmitting a digital message over a channel with limited bandwidth and signal power.

The channel capacity can be increased by temporarily overlapping the amplitude, frequency and time of the transmission pulse.

The overlapping pulses have frequency overlapping spectra, and as a result, the channel bandwidth cannot be extended. According to an exponential law, the use of intra impulse modulation of each superimposed pulse prevents an increase in the dynamic range for the channel signal.

Constant components appearing as a result of overlap do not propagate through the channel, but only at the channel end.

Description

Data Transmission and Reception Device for channel capacity increase (Trubitsin's scheme for channel capacity increase)

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data transmission / reception apparatus, and more particularly, to a data transmission / reception apparatus that increases channel capacity by transmitting digital data through a channel with limited bandwidth and signal power by overlapping amplitude, frequency, and time of a transmission pulse. It is about.

In general, when digital data is transmitted through a communication channel such as a ground line channel, a wireless channel, or an optical channel, it is necessary to increase the accuracy of data transmission in order to transmit the data without loss.

As such, various techniques have been proposed to increase the accuracy of data transmission. As an example, the USSR 131325718 patent proposes a "binary code transmitter", which has the disadvantage of sharply increasing signal power to accelerate data transmission.

In addition, the USSR patent No. 1511865 proposes an invention called "binary code transmission device" for increasing the accuracy of data transmission by optimizing the value of the transmission code signal. There are disadvantages.

Shannon's Limit is known as a theory of channel capacity, which is represented by the following equation (1) defined by the bandwidth and the allowed signal power.

C = ΔFlog ₂ (1 + P _s / P _n ), Bps

Where ΔF is the channel bandwidth (Hz) and P _s / P _n is the signal-to-noise power ratio of the channel.

This limitation is considered to be insurmountable for any transmission mode unless the channel characteristics are changed. The channel characteristic based on Equation 1 means the allowable dynamic range and bandwidth ΔF of the signal power P _s divided by the noise power P _n , and the channel characteristic changes the previous state according to the input information. In other words, the state of the channel must change every time T under the condition of limited wave range and signal dynamic range, and if there is no change in the state of the channel, no data transmission is possible.

For example, suppose that information is transmitted through a limited 3 kHz wave region channel. The channel capacity according to Equation 1 is determined by the signal-to-noise ratio. Further, assuming that the noise power of the channel is limited by a certain amount that is not affected by the transmission information, the maximum amount of information (capacity of the channel) is determined only by the signal power P _s value. In addition, according to the channel characteristic definition, the signal power P _s should be changed at every moment according to the input information, and the change should be regarded as being made in the 3 kHz wave region. At this time, for example, when transmitting data at a maximum speed of 150 kbit / s and a maximum noise power of 100 pW (noise voltage meter noise power of a subscriber telephone line), a signal power of about 112 kW is required.

In general, the signal power on the channel is limited and is much smaller than the above values. For example, the data transmission signal power of the VF channel is about 32 μW, and the channel capacity according to Equation 1 is about 57 kbit / s. In order to increase the capacity to 150kbit / s under the condition that the signal-to-noise power values are 32μW and 10pW, respectively, a wave range of 7kHz and 8kHz is required.

As described above, in order to increase the channel capacity according to Equation 1, there is a problem in that the bandwidth and the signal / noise power ratio need to be increased.

The present invention is to solve the problems of the prior art as described above, an object of the present invention, when increasing the channel capacity according to the equation (1) by overlapping the amplitude, frequency and time of the transmission pulse (limited bandwidth) The present invention provides a data transmitting / receiving apparatus for increasing channel capacity without increasing bandwidth and signal / noise power ratio by transmitting digital data through a channel with over signal power.

1 is a spectrum showing superimposed pulses in time, frequency and amplitude,

Fig. 2 is a waveform diagram showing the resultant shape of a signal in a channel when superimposing pulses;

Fig. 3 is a diagram showing signals in a channel and its spectrum for a condition having ΔF = 100 Hz to 3 kHz, a peak-to-noise power ratio of approximately 55 dB, an error probability of 10 to ¹⁰ , and a data rate of 150 kbit / s when overlapping pulses. ,

4 is a block diagram of a data transmission apparatus according to the present invention;

5 is a block diagram of a data receiving apparatus according to the present invention;

FIG. 6 is a diagram illustrating a configuration of the counter unit shown in FIG. 5; FIG.

Explanation of symbols on the main parts of the drawings

1: parallel-serial shift block 2, 3: parallel register

4: ROM5: Address register

6 multiplier 7 adder

8: Digital-to-Analog Converter (DAC) 9: Low Pass Filter (LPF)

10: analog-to-digital converter (ADC) 11: subtractor

12 decoding unit 13 counter unit

14: code determiner 15: encoder

16: decoder 17: counter

20: encoder

A feature of the present invention for achieving the above object is, in the data transmission apparatus for increasing the channel capacity, multiply the values of the basis function which is a coding function according to the parallel binary code while shifting a plurality of parallel binary codes at regular intervals. Encoding means for encoding a binary code by adding up all products during a predetermined period; Digital-analog converting means for converting a code supplied from said encoding means into an analog signal; And low-pass filter means for low-passing the analog signal supplied from the digital-to-analog conversion means and transmitting it to the channel.

Further, the encoding means may include: parallel-serial shift means for shifting a plurality of parallel binary codes input at a predetermined period; A plurality of address registers for storing a first code input from said parallel-serial shift means and outputting it as an address; A plurality of memory means for outputting prestored basis function values in accordance with an address applied from said address register; A plurality of multiplication means for multiplying the output of said memory means and a second code input from said parallel-serial shift means; And an adding means for adding the output of the memory means for the total time shifted in the parallel-serial shift means to the output of the multiplication means and outputting the output to the digital-analog converting means.

On the other hand, another aspect of the present invention provides a data receiving apparatus for increasing channel capacity, comprising: analog-to-digital conversion means for digitally converting an encoded analog code transmitted from a channel; Subtraction means for subtracting a model value code from the digitally converted signal; Decoding means for inputting a result of the subtraction means and outputting a binary code with reference to a decoding table; Counter means for copying a binary code output from said decoding means and outputting it at a predetermined time period; Code determining means for determining and outputting a binary code according to a value applied from said counter means; And encoding means for generating a model value code according to the binary code applied from the code determining means and outputting the model value code to the subtraction means.

And the counter means comprises: a plurality of decoders for decoding a binary code applied from the encoding means; And a plurality of counters connected corresponding to the decoders for copying and shifting codes applied from the decoders.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

The demonstration of overcoming Shannon's limitations on the capacity of the communication channel is based on the following first and second statements.

First technology. In order to avoid an increase in bandwidth when accelerating the input of information, pulses must overlap in time, amplitude and frequency. The data transmission pulses at that time are calculated such that the spectra overlap in frequency, and according to the spectral sum law, the spectral sum of a single pulse will be equal to the spectral sum of these pulses.

Second technology. Using a frequency-integrated Gaussian pulse as a data transfer pulse, the resulting signal in the channel is represented by the Laplace function, whose constant component is used only at the channel end and is not input to the channel, which does not contain useful information.

1 shows an implementation of the first technique, and FIG. 2 shows an implementation of the second technique. Fig. 3 shows a signal of a channel and spectrum in an environment with a binary code transmission rate of 150 kbit / s, a channel bandwidth of 100 Hz to 3 kHz, a channel signal-to-noise power ratio of approximately 32 μW / 100 pW, and a decoding error rate of 10 ^-10 . It is shown.

4 is a block diagram of a data transmission apparatus according to the present invention.

The data transmitting and receiving apparatus according to the present invention shown in FIG. 4 includes an encoder 20, a DAC 8, and an LPF 9. As shown in FIG. The encoding unit 20 multiplies the parallel binary code with the values of the basis function, which is an encoding function, and encodes the sum of all the products for a predetermined period and outputs the binary code to the DAC 8 side. The DAC 8 converts the code supplied from the encoder 20 into an analog signal and outputs it to the LPF 9 side. The LPF 9 low-passes the analog signal supplied from the DAC 8 to pass the channel. To the side.

On the other hand, the encoder 20 is configured with a parallel-serial shift block 1, a plurality of address registers 5, a plurality of ROMs 4, a plurality of multipliers 6 and an adder 7. The parallel-serial shift block 1 is composed of a plurality of pairs of parallel registers 2 and 3, and receives two parallel binary codes X _{i and} Z _i into the parallel registers 2 and 3 during a predetermined time period. In this way, the parallel binary codes inputted in this way are shifted along the adjacent parallel register at predetermined time intervals.

The parallel binary code Z _i is input to the address register 5 and outputs a base function value which is an encoding function which is data stored in the ROM 4. The ROM 4 stores a basis function value output in accordance with an address corresponding to a parallel binary code.

The first multiplier 6 multiplies the basis function value applied from the ROM 4 to the first input and the parallel binary code X _i applied from the parallel register 2 to the second input.

In order to add the processing results for a predetermined time, the adder 7 adds the results from the first multiplier to the Q multiplier.

The summed value is converted into an analog signal by the DAC 8 and transmitted to the channel via the LPF 9.

5 is a block diagram of a data receiving apparatus according to the present invention, and FIG. 6 is a diagram illustrating a configuration of a counter unit shown in FIG.

As shown in FIG. 5, the data receiving apparatus includes an ADC 10, a subtractor 11, a decoder 12, a counter 13, a code determiner 14, and an encoder 15. .

The encoded analog code transmitted from the communication channel is converted into a digital code encoded by the ADC 10. Since this code is a sum of values for a predetermined time, the value obtained from the decoded binary code must first be subtracted. To this end, first, a model value code to be subtracted from the decoded binary code is obtained by the encoder 15 encoding in the same manner as the encoding method using the encoder 20 shown in FIG.

The subtractor 11 subtracts the model value code from the encoder 15 from the code input through the ADC 10. The output of the subtractor 11 is input to the decoder 12, and the decoder 12, which stores the decoding table, refers to the decoding table and outputs a binary code corresponding to the input code value.

At this time, the binary code output from the decoding unit 12 is input to the counter unit 13 having a plurality of counters C1 to CL. In the counter section 13, the value of the counter on the right is copied to the value of the counter on the left on a predetermined time period. After a predetermined time, the count value is outputted to the code determination unit 14 via the leftmost counter CL.

The code determiner 14 determines the binary code according to the value applied from the counter 13 and applies it to the encoder 15 and the receiver output.

The encoder 15 operates in the same configuration as the encoder 20 of FIG. 4, and outputs the coded model value code to the subtractor 11.

6 shows the configuration of the counter unit 13 for the case where X = 1 ÷ M and Z = 0. The counter unit 13 includes a plurality of decoders 16 and a plurality of binary counters 17. It includes.

The data transmitting and receiving apparatus of the present invention configured as described above operates as follows.

Information is transmitted over the communication channel and converted into Xi and Zi formats and input to the first pair of parallel registers 2 and 3 in the parallel-serial shift block 1. In the parallel-serial shift block 1, each pair of parallel registers 2 and 3 shifts the corresponding information Xi and Zi by a T time interval. The information codes outputted from the parallel register 3 of the parallel-serial shift block 1 are outputted through the address register 5, and the basis function values are read from the ROM 4 according to these address codes, so that the multiplier ( The Xi code value applied to the first input of 6) and output from the parallel register 2 is applied to the second input of the multiplier 6. As a result, the basis function value Y (t) output from the ROM 4 is logically multiplied by the corresponding Xi code in the multiplier 6. The adder 7 adds to the output of the multiplier 6 during every period of the T interval time. The added code is converted into voltage and current levels by analog conversion in the DAC 8, low pass through the LPF 9, and applied as a signal U _{ch, i} to the communication channel.

The U _{ch, i} signal _{arrives at} the data receiving apparatus of FIG. 5 and is input to the ADC 10. The digitally converted signal output from the ADC 10 is applied to the first input of the subtractor 11, and at the same time, the model value code is input from the encoder 15 to the second input of the subtractor 11. . As a result, the subtractor 11 outputs a code every T time, and the code is used as an address of Xi and Zi tables for the decoding lookup table included in the decoder 12, and is decoded by the corresponding address. ) Outputs a code relating to the definition of Xi and Zi to the counter unit 13. At this time, with the aid of the decoder 16, the code value from the decoder 12 is added to the corresponding counter 17 if " 1 ", and not added if " 0 ".

Thus, the contents of all counters 17 are shifted to the left counter. Therefore, Xi and Zi are defined by the value of the left group counter 17 according to the majority vote principle after the L, T cycles. Every counter from 0 to M-1 contains numbers for defining Xi and Zi. The Xi and Zi decoding values output from the code determiner 14 reach the receiver output and are simultaneously applied to the input of the encoder 15. The operation of the encoder 15 is configured and operates in the same manner as the encoder 20 of FIG. 4.

As described above, in the data transmitting and receiving apparatus according to the present invention, by transmitting the digital data through the channel with limited bandwidth and signal power by overlapping the amplitude, frequency and time of the transmission pulse, the bandwidth and signal / noise power ratio are increased. There is an advantage to increase the channel capacity without.

Claims (4)

In the data transmission apparatus for increasing the channel capacity, Encoding means for encoding a binary code by multiplying values of a basis function which is a coding function according to the parallel binary code while shifting a plurality of parallel binary codes at a constant period, and adding all the products for a predetermined period; Digital-analog converting means for converting a code supplied from said encoding means into an analog signal; And low-pass filter means for low-passing the analog signal supplied from the digital-to-analog converting means and transmitting it to the channel. 2. The apparatus of claim 1, wherein the encoding means comprises: parallel-serial shift means for shifting a plurality of parallel binary codes input at a predetermined period; A plurality of address registers for storing a first code input from said parallel-serial shift means and outputting it as an address; A plurality of memory means for outputting prestored basis function values in accordance with an address applied from said address register; A plurality of multiplication means for multiplying the output of said memory means and a second code input from said parallel-serial shift means; And adding means for adding the output of the memory means for the total time shifted in the parallel-serial shift means to the output of the multiplication means and outputting the output to the digital-analog converting means. Data transmission device for. In the data receiving apparatus for increasing the channel capacity, Analog-to-digital conversion means for digitally converting the encoded analog code transmitted from the channel; Subtraction means for subtracting a model value code from the digitally converted signal; Decoding means for inputting a result of the subtraction means and outputting a binary code with reference to a decoding table; Counter means for copying a binary code output from said decoding means and outputting it at a predetermined time period; Code determining means for determining and outputting a binary code according to a value applied from said counter means; And encoding means for generating a model value code according to the binary code applied from the code determining means and outputting the model value code to the subtracting means. 4. The apparatus of claim 3, wherein the counter means comprises: a plurality of decoders for decoding a binary code applied from the encoding means; And a plurality of counters connected corresponding to the decoders for copying and shifting codes applied from the decoders.