KR19980045339A - Metal wiring formation method of semiconductor device - Google Patents
Metal wiring formation method of semiconductor device Download PDFInfo
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- KR19980045339A KR19980045339A KR1019960063521A KR19960063521A KR19980045339A KR 19980045339 A KR19980045339 A KR 19980045339A KR 1019960063521 A KR1019960063521 A KR 1019960063521A KR 19960063521 A KR19960063521 A KR 19960063521A KR 19980045339 A KR19980045339 A KR 19980045339A
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- film
- aluminum alloy
- oxide film
- metal wiring
- alloy film
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- 229910052751 metal Inorganic materials 0.000 title claims abstract description 29
- 239000002184 metal Substances 0.000 title claims abstract description 29
- 239000004065 semiconductor Substances 0.000 title claims abstract description 25
- 238000000034 method Methods 0.000 title claims abstract description 20
- 230000015572 biosynthetic process Effects 0.000 title description 4
- 229910000838 Al alloy Inorganic materials 0.000 claims abstract description 30
- 239000000758 substrate Substances 0.000 claims abstract description 10
- 238000005530 etching Methods 0.000 claims abstract description 6
- 238000007598 dipping method Methods 0.000 claims abstract description 4
- CBENFWSGALASAD-UHFFFAOYSA-N Ozone Chemical compound [O-][O+]=O CBENFWSGALASAD-UHFFFAOYSA-N 0.000 claims description 2
- 229920006395 saturated elastomer Polymers 0.000 claims 1
- 239000010408 film Substances 0.000 description 61
- 229910018072 Al 2 O 3 Inorganic materials 0.000 description 9
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 5
- 229920002120 photoresistant polymer Polymers 0.000 description 5
- 229910018594 Si-Cu Inorganic materials 0.000 description 2
- 229910008465 Si—Cu Inorganic materials 0.000 description 2
- 239000007789 gas Substances 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 229910045601 alloy Inorganic materials 0.000 description 1
- 239000000956 alloy Substances 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 230000001681 protective effect Effects 0.000 description 1
- 230000008054 signal transmission Effects 0.000 description 1
- 238000002791 soaking Methods 0.000 description 1
- 239000010409 thin film Substances 0.000 description 1
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- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
본 발명은 반도체 소자의 금속 배선 형성 방법에 관한 것으로, 특히, 반사 방지막으로서 산화막을 사용하는 반도체 소자의 금속 배선 형성 방법에 관한 것이다. 본 발명의 반도체 소자의 금속 배선 형성 방법은 반도체 기판 상에 절연용 산화막 및 알루미늄 합금막을 순차적으로 형성하는 단계; 상기 알루미늄 합금막 표면에 산화막을 성장시키기 위하여 상기 알루미늄 합금막이 형성된 반도체 기판을 소정 용액에 디핑하는 단계; 및 상기 산화막 및 알루미늄 합금막을 식각하여 금속 배선을 형성하는 단계를 포함하는 것을 특징으로 한다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for forming metal wirings in semiconductor devices, and more particularly, to a method for forming metal wirings in semiconductor devices using an oxide film as an antireflection film. A method of forming a metal wiring of a semiconductor device of the present invention comprises the steps of sequentially forming an insulating oxide film and an aluminum alloy film on a semiconductor substrate; Dipping the semiconductor substrate on which the aluminum alloy film is formed in a predetermined solution to grow an oxide film on the surface of the aluminum alloy film; And etching the oxide film and the aluminum alloy film to form metal wires.
Description
본 발명은 반도체 소자의 금속 배선 형성 방법에 관한 것으로, 보다 상세하게는, 반사방지막으로서 산화막을 사용하는 반도체 소자의 금속 배선 형성 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for forming metal wirings in semiconductor devices, and more particularly, to a method for forming metal wirings in semiconductor devices using an oxide film as an antireflection film.
현재, 반도체 장치에 있어서, 신호 전달 및 전원 인가 등의 목적으로 사용되는 금속 배선용 박막은 소자의 집적도 증가로 인하여 배선 자체의 선폭 감소 및 배선간의 간격이 점점 좁아지게 된다.Currently, in the semiconductor device, the thin film for metal wiring, which is used for the purpose of signal transmission, power supply, and the like, the line width of the wiring itself decreases and the spacing between wirings becomes narrower due to the increase in the degree of integration of the devices.
이러한 추세에 따라, 배선 설계가 자유롭고 용이하며 배선 저항 및 전류 용량 등의 설정을 여유있게 할 수 있는 금속 배선 기술에 관한 연구가 활발하게 진행되고 있으며, 반도체 소자의 금속 배선 재료로서 낮은 저항을 가지고 있는 알루미늄 합금막이 널리 이용되고 있음은 주지의 사실이다. 한편, 이러한 금속 배선막의 형성 후에는 반사방지막으로 주로 TiN 막을 형성한다.In accordance with this trend, research on metal wiring technology that enables free and easy wiring design and allows setting of wiring resistance and current capacity is being actively conducted, and has a low resistance as a metal wiring material for semiconductor devices. It is well known that aluminum alloy films are widely used. On the other hand, after formation of such a metal wiring film, a TiN film is mainly formed as an antireflection film.
상기와 같이 반사방지막으로서 TiN 막을 사용하는 종래 기술에 따른 반도체 소자의 금속 배선 형성 방법을 도 1 을 참조하여 설명하면 다음과 같다.A method of forming a metal wiring of a semiconductor device according to the prior art using a TiN film as an antireflection film as described above will be described with reference to FIG. 1.
소정의 트랜지스터가 구비된 반도체 기판(1) 상에 절연용 산화막(2)을 형성하고, 그 상부에 Al-Si-Cu로 구성된 알루미늄 합금막(3) 및 TiN 으로 형성된 반사방지막(4)을 적층한다. 그리고 나서, 반사방지막(4) 상에 감광막 패턴(도시되지 않음)을 형성하고, 감광막 패턴의 형태로 하부의 반사방지막(4) 및 알루미늄 합금막(3)을 식각하여 금속 배선을 형성한다. 이후, 감광막 패턴을 제거한다.An insulating oxide film 2 is formed on the semiconductor substrate 1 provided with a predetermined transistor, and an aluminum alloy film 3 made of Al-Si-Cu and an antireflection film 4 made of TiN are stacked thereon. do. Then, a photoresist pattern (not shown) is formed on the antireflection film 4, and the lower antireflection film 4 and the aluminum alloy film 3 are etched in the form of the photoresist pattern to form metal wirings. Thereafter, the photoresist pattern is removed.
그러나, 상기와 같은 종래 기술은, 반사방지막인 TiN 막과 알루미늄 합금막 사이의 스트레스(stress)로 인하여 TiN 막에 미세한 틈(crack)이 발생되고, 이 틈을 통하여 감광막 패턴 형성시 사용된 현상액이 스며들게 됨으로써, 스며든 현상액과 알루미늄 합금막이 화학 반응을 일으켜 Al2O3와 같은 산화막이 형성된다. 이때, 이러한 산화막이 알루미늄 합금막의 식각식 보호막의 역할을 하여 결국에는 절연용 산화막 상에 원하지 않는 금속 잔류물(5)을 남기게 됨으로써, 반도체 소자의 신뢰성 및 제조 수율을 저하시키는 문제점이 있었다.However, in the prior art as described above, a fine crack is generated in the TiN film due to the stress between the anti-reflection film TiN film and the aluminum alloy film, through which the developer used to form the photoresist pattern is formed. By soaking, the soaked developer and the aluminum alloy film undergo a chemical reaction to form an oxide film such as Al 2 O 3 . At this time, such an oxide film serves as an etch protective film of the aluminum alloy film, and eventually leaves unwanted metal residues 5 on the insulating oxide film, thereby lowering the reliability and manufacturing yield of the semiconductor device.
따라서, 본 발명은 상기와 같은 문제점을 해결하기 위하여, 알루미늄 합금막과 스트레스를 야기하지 않는 산화막을 알루미늄 합금막 표면에 성장시켜 반사방지막으로 이용하는 반도체 소자의 금속 배선 형성 방법을 제공하는 것을 목적으로 한다.Accordingly, an object of the present invention is to provide a method for forming a metal wiring of a semiconductor device in which an aluminum alloy film and an oxide film not causing stress are grown on an aluminum alloy film surface and used as an antireflection film.
도 1 은 종래 기술에 따른 반도체 소자의 금속 배선 형성 방법을 설명하기 위한 단면도.1 is a cross-sectional view for explaining a metal wiring forming method of a semiconductor device according to the prior art.
도 2A 및 도 2B 는 본 발명에 따른 반도체 소자의 금속 배선 형성 방법을 설명하기 위한 단면도.2A and 2B are cross-sectional views for explaining a metal wiring formation method of a semiconductor device according to the present invention.
*도면의 주요부분에 대한 부호의 설명** Description of the symbols for the main parts of the drawings *
11 : 반도체 기판12 : 절연용 산화막11: semiconductor substrate 12: oxide film for insulation
13 : 알루미늄 합금막14 : Al2O3산화막13: aluminum alloy film 14: Al 2 O 3 oxide film
상기와 같은 목적은, 반도체 기판 상에 절연용 산화막 및 알루미늄 합금막을 순차적으로 형성하는 단계; 상기 알루미늄 합금막 표면에 산화막을 성장시키기 위하여 상기 알루미늄 합금막이 형성된 반도체 기판을 소정 용액에 디핑하는 단계; 및 상기 산화막 및 알루미늄 합금막을 식각하여 금속 배선을 형성하는 단계를 포함하는 것을 특징으로 하는 본 발명에 따른 반도체 소자의 금속 배선 형성 방법에 의하여 달성된다.The above object is a step of sequentially forming an insulating oxide film and an aluminum alloy film on a semiconductor substrate; Dipping the semiconductor substrate on which the aluminum alloy film is formed in a predetermined solution to grow an oxide film on the surface of the aluminum alloy film; And etching the oxide film and the aluminum alloy film to form a metal wiring, thereby forming the metal wiring of the semiconductor device according to the present invention.
본 발명에 따르면, 알루미늄 합금막과 스트레스가 야기되지 않는 산화막을 반사방지막으로 사용함으로써, 이후의 금속 배선을 형성하기 위한 식각 공정시, 금속 잔류물이 전혀 남지 않는 양호한 금속 배선을 얻을 수 있다.According to the present invention, by using an aluminum alloy film and an oxide film which does not cause stress as an antireflection film, it is possible to obtain good metal wirings in which no metal residues remain in the subsequent etching process for forming metal wirings.
[실시예]EXAMPLE
이하, 도 2A 및 도 2B 를 참조하여 본 발명의 바람직한 실시예를 보다 상세하게 설명한다.Hereinafter, preferred embodiments of the present invention will be described in more detail with reference to FIGS. 2A and 2B.
도 2A를 참조하면, 소정의 트랜지스터(도시되지 않음)가 구비된 반도체 기판(11)상에 절연용 산화막(12) 및 Al-Si-Cu로 구성된 알루미늄 합금막(13)을 형성하고, 상기 알루미늄 합금막(13)이 형성된 반도체 기판(11)을 포화 상태의 오존(O3)이 용해되어 있는 약 50 내지 90℃의 고온 H2O에 약 1분 내지 5분 동안 디핑(dipping)한다. 이때, 알루미늄 합금막(13)의 표면에 약 500 내지 1,500Å 두께의 Al2O3산화막(14)이 성장하게 되고, Al2O3산화막(14)은 반사방지막의 역할을 한다.Referring to FIG. 2A, an insulating oxide film 12 and an aluminum alloy film 13 made of Al-Si-Cu are formed on a semiconductor substrate 11 provided with a predetermined transistor (not shown). The semiconductor substrate 11 on which the alloy film 13 is formed is dipped in hot H 2 O at about 50 to 90 ° C. in which saturated ozone (O 3 ) is dissolved for about 1 to 5 minutes. At this time, the Al 2 O 3 oxide film 14 having a thickness of about 500 to 1,500 Å grows on the surface of the aluminum alloy film 13, and the Al 2 O 3 oxide film 14 serves as an antireflection film.
도 2B 를 참조하면, Al2O3산화막(14) 상에 감광막 패턴(도시되지 않음)을 형성하고, 감광막의 형태로 하부의 Al2O3산화막(14) 및 알루미늄 합금막(13)을 식각하여 금속 배선을 형성한다. 이때, Al2O3산화막(14)을 노광시의 반사방지막으로 하여 알루미늄 합금막(13)을 식각하면, 금속 잔류물이 전혀 남지 않은 양호한 금속 배선을 얻을 수 있다. 한편, Al2O3산화막(14) 및 알루미늄 합금막(13)의 식각 공정에서 Al2O3산화막(14)은 CF4가스를 사용하여 식각하고, 알루미늄 합금막(13)은 Cl2/BCl3가스를 사용하여 식각한다.Referring to Figure 2B, Al 2 O 3 oxide film (not shown) photoresist pattern for the 14 formation and the bottom in the form of a photosensitive film Al 2 O 3 oxide film 14 and aluminum alloy etching the film 13 To form a metal wiring. At this time, when the aluminum alloy film 13 is etched by using the Al 2 O 3 oxide film 14 as an antireflection film during exposure, good metal wiring with no metal residue at all can be obtained. On the other hand, Al 2 O 3 oxide film 14 and in the etching process of the aluminum alloy layer 13 Al 2 O 3 oxide film 14 is etched using a CF 4 gas, the aluminum alloy layer 13 is Cl 2 / BCl Etch using 3 gases.
이상에서와 같이, 본 발명의 반도체 소자의 금속 배선 형성 방법은 알루미늄 합금막의 표면에 성장시킨 산화막을 반사방지막으로 이용하여 필름 스트레스를 최소화함으로서, 금속 배선용 사진식각시 금속 잔류물을 남기지 않게 되어 반도체 소자의 신뢰성 및 제조 수율을 향상시킬 수 있다.As described above, in the method of forming a metal wiring of the semiconductor device of the present invention, the film stress is minimized by using an oxide film grown on the surface of the aluminum alloy film as an anti-reflection film, thereby leaving no metal residue during the photolithography for metal wiring. It can improve the reliability and manufacturing yield.
한편, 여기에서는 본 발명의 특정 실시예에 대하여 설명하고 도시하였지만, 당업자에 의하면 이에 대한 수정과 변형을 할 수 있다. 따라서, 이하, 특허청구의 범위는 본 발명의 진정한 사상과 범위에 속하는 한 모든 수정과 변형을 포함하는 것으로 이해할 수 있다.Meanwhile, although specific embodiments of the present invention have been described and illustrated herein, those skilled in the art may make modifications and variations. Accordingly, the following claims are to be understood as including all modifications and variations as long as they fall within the true spirit and scope of the present invention.
Claims (7)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019960063521A KR19980045339A (en) | 1996-12-10 | 1996-12-10 | Metal wiring formation method of semiconductor device |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019960063521A KR19980045339A (en) | 1996-12-10 | 1996-12-10 | Metal wiring formation method of semiconductor device |
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| Publication Number | Publication Date |
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| KR19980045339A true KR19980045339A (en) | 1998-09-15 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| KR1019960063521A Withdrawn KR19980045339A (en) | 1996-12-10 | 1996-12-10 | Metal wiring formation method of semiconductor device |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100587598B1 (en) * | 2002-11-19 | 2006-06-08 | 매그나칩 반도체 유한회사 | How to Form Metal Wiring |
| KR101146486B1 (en) * | 2005-06-29 | 2012-05-21 | 엘지디스플레이 주식회사 | metal line fabrication method and the array substrate for LCD by using it |
-
1996
- 1996-12-10 KR KR1019960063521A patent/KR19980045339A/en not_active Withdrawn
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100587598B1 (en) * | 2002-11-19 | 2006-06-08 | 매그나칩 반도체 유한회사 | How to Form Metal Wiring |
| KR101146486B1 (en) * | 2005-06-29 | 2012-05-21 | 엘지디스플레이 주식회사 | metal line fabrication method and the array substrate for LCD by using it |
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Patent event code: PA01091R01D Comment text: Patent Application Patent event date: 19961210 |
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