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KR102223708B1 - 유기 멘드렐 보호 공정 - Google Patents

유기 멘드렐 보호 공정 Download PDF

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Publication number
KR102223708B1
KR102223708B1 KR1020197000427A KR20197000427A KR102223708B1 KR 102223708 B1 KR102223708 B1 KR 102223708B1 KR 1020197000427 A KR1020197000427 A KR 1020197000427A KR 20197000427 A KR20197000427 A KR 20197000427A KR 102223708 B1 KR102223708 B1 KR 102223708B1
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KR
South Korea
Prior art keywords
patterned structure
dcs
range
substrate
spacer
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KR1020197000427A
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English (en)
Korean (ko)
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KR20190006205A (ko
Inventor
아키테루 코
안젤리크 레일리
소피 티보
사토루 나카무라
니하르 모한티
Original Assignee
도쿄엘렉트론가부시키가이샤
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Publication of KR20190006205A publication Critical patent/KR20190006205A/ko
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/033—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
    • H01L21/0334—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
    • H01L21/0337—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane characterised by the process involved to create the mask, e.g. lift-off masks, sidewalls, or to modify the mask, e.g. pre-treatment, post-treatment
    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
    • G03F7/20—Exposure; Apparatus therefor
    • G03F7/2022—Multi-step exposure, e.g. hybrid; backside exposure; blanket exposure, e.g. for image reversal; edge exposure, e.g. for edge bead removal; corrective exposure
    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F1/00—Originals for photomechanical production of textured or patterned surfaces, e.g., masks, photo-masks, reticles; Mask blanks or pellicles therefor; Containers specially adapted therefor; Preparation thereof
    • G03F1/68—Preparation processes not covered by groups G03F1/20 - G03F1/50
    • G03F1/80—Etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
    • H01L21/02263—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
    • H01L21/02271—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
    • H01L21/0228—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition deposition by cyclic CVD, e.g. ALD, ALE, pulsed CVD
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/0271—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers
    • H01L21/0273—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers characterised by the treatment of photoresist layers
    • H01L21/0274—Photolithographic processes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31127—Etching organic layers

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  • Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • Inorganic Chemistry (AREA)
  • Drying Of Semiconductors (AREA)
  • Chemical Vapour Deposition (AREA)
KR1020197000427A 2016-06-08 2017-05-18 유기 멘드렐 보호 공정 Active KR102223708B1 (ko)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US201662347460P 2016-06-08 2016-06-08
US62/347,460 2016-06-08
PCT/US2017/033242 WO2017213817A1 (en) 2016-06-08 2017-05-18 Organic mandrel protection process

Publications (2)

Publication Number Publication Date
KR20190006205A KR20190006205A (ko) 2019-01-17
KR102223708B1 true KR102223708B1 (ko) 2021-03-04

Family

ID=60578892

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1020197000427A Active KR102223708B1 (ko) 2016-06-08 2017-05-18 유기 멘드렐 보호 공정

Country Status (3)

Country Link
KR (1) KR102223708B1 (zh)
CN (1) CN109478022B (zh)
WO (1) WO2017213817A1 (zh)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN112309835B (zh) * 2019-07-31 2023-11-10 中芯国际集成电路制造(上海)有限公司 半导体结构及其形成方法
CN112928165B (zh) * 2019-12-05 2024-06-18 中芯国际集成电路制造(上海)有限公司 半导体结构及其形成方法
CN112086348B (zh) * 2020-08-31 2022-11-29 上海华力微电子有限公司 双重图形氧化硅芯轴制备方法
KR20240177550A (ko) 2023-06-20 2024-12-27 남기은 자유자재 손잡이

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20100227276A1 (en) 2009-03-09 2010-09-09 Hitachi-Kokusai Electric Inc. Method of manufacturing semiconductor device
US20150072527A1 (en) 2012-02-09 2015-03-12 Taiwan Semiconductor Manufacturing Company, Ltd. Method for patterning a plurality of features for fin-like field-effect transistor (finfet) devices
US20150160557A1 (en) 2013-12-05 2015-06-11 Tokyo Electron Limited Direct Current Superposition Freeze
US20150287612A1 (en) 2014-04-07 2015-10-08 Applied Materials, Inc. Spacer formation

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2013101107A1 (en) * 2011-12-29 2013-07-04 Intel Corporation Double patterning lithography techniques
US9466486B2 (en) * 2013-08-30 2016-10-11 Taiwan Semiconductor Manufacturing Company, Ltd. Method for integrated circuit patterning
US9490182B2 (en) * 2013-12-23 2016-11-08 Kla-Tencor Corporation Measurement of multiple patterning parameters
US20160049307A1 (en) * 2014-08-15 2016-02-18 Yijian Chen Patterning method for IC fabrication using 2-D layout decomposition and synthesis techniques

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20100227276A1 (en) 2009-03-09 2010-09-09 Hitachi-Kokusai Electric Inc. Method of manufacturing semiconductor device
US20150072527A1 (en) 2012-02-09 2015-03-12 Taiwan Semiconductor Manufacturing Company, Ltd. Method for patterning a plurality of features for fin-like field-effect transistor (finfet) devices
US20150160557A1 (en) 2013-12-05 2015-06-11 Tokyo Electron Limited Direct Current Superposition Freeze
US20150287612A1 (en) 2014-04-07 2015-10-08 Applied Materials, Inc. Spacer formation

Also Published As

Publication number Publication date
CN109478022B (zh) 2021-12-28
KR20190006205A (ko) 2019-01-17
WO2017213817A1 (en) 2017-12-14
CN109478022A (zh) 2019-03-15

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