KR101232172B1 - Analog buffer and method for driving the same and display device using the same - Google Patents

Abstract

The present invention relates to an analog buffer, a driving method thereof, and a display device using the same, which can prevent distortion of a displayed data signal by generating a precharge voltage according to an input voltage and supplying the same to a display panel. At least one operational amplifier configured to compare an input voltage input to an output voltage fed back to a second input terminal and output an output voltage converged to the input voltage to an output line, and the output voltage from the at least one operational amplifier; It characterized in that it comprises at least one charging unit for generating a pre-charge voltage used to supply to the output line.

Analog buffer, precharge voltage, op amp, live part

Description

Analog buffer and method for driving the same and display device using the same}

1 is an equivalent circuit diagram showing a conventional analog buffer.

FIG. 2 is a waveform diagram illustrating input / output signals of the analog buffer shown in FIG. 1. FIG.

3 is an equivalent circuit diagram illustrating an analog buffer according to an embodiment of the present invention.

4 is a waveform diagram illustrating input / output signals of the analog buffer shown in FIG. 3;

FIG. 5 is an equivalent circuit diagram illustrating an analog buffer in the first driving section shown in FIG. 4. FIG.

6 is a block diagram of a liquid crystal display device having an analog buffer according to an embodiment of the present invention.

＊ Explanation of symbols for main parts of drawing *

21: first charging unit 22: second charging unit

31: first operational amplifier 32: second operational amplifier

33: first controller 34: second controller

SW1 to SW8: first to eighth switches

nR and R: first and second voltage divider resistors

nR 'and R': third and fourth voltage divider resistors

The present invention relates to an analog buffer, a driving method thereof, and a display device using the same, which can prevent distortion of a displayed data signal by generating a precharge voltage according to an input voltage and supplying the same to a display panel.

Conventional liquid crystal displays display images by adjusting the light transmittance of liquid crystals having dielectric anisotropy using an electric field. To this end, the liquid crystal display includes a liquid crystal panel in which pixel regions are arranged in a matrix, and a driving circuit for driving the liquid crystal panel.

In the liquid crystal panel, a plurality of gate lines and a plurality of data lines are arranged to cross each other, and a pixel region is positioned in an area defined by vertical crossings of the gate lines and the data lines. Pixel electrodes and a common electrode for applying an electric field to each of the pixel regions are formed. Each of the pixel electrodes is connected to a thin film transistor (TFT) which is a switching element. The thin film transistor is turned on by the scan pulse of the gate line, so that the data signal of the data line is charged to the pixel electrode.

The driving circuit includes a gate driver for driving the gate lines, a data driver for driving the data lines, a timing controller for supplying control signals for controlling the gate driver and the data driver, and various driving voltages used in the liquid crystal display. It has a power supply for supplying them.

The data driver converts the digital image data input from the timing controller into analog image data, and supplies one horizontal line of analog image data to the data line every horizontal period in which a scan pulse is supplied to the gate line. Here, the data driver includes an analog buffer for preventing the analog image data supplied to the data line from being distorted according to the RC load amount of the data line. At this time, an operational amplifier and an inverter etc. are mainly used as an analog buffer.

In general, a method of driving an analog buffer included in a data driver includes charging an offset voltage of an analog buffer, and driving a data line by outputting a voltage equal to an input voltage while compensating for the charged offset voltage.

1 is an equivalent circuit diagram showing a conventional analog buffer.

1 illustrates a first operational amplifier 11 for outputting an output voltage Converging to a positive input voltage Input according to a first high control signal CSS1 from a first controller 13. ), A second operational amplifier 12 that outputs an output voltage Converging to the negative input voltage Input according to the first row control signal CSL1 from the first controller 13, and a first operational amplifier 12. And first and second switches SW1 and SW2 for switching the output voltage Output from the second operational amplifiers 11 and 12, and a second high control signal VCS2 from the second controller 14. And first and second switching elements Tr1 and Tr2 for switching the first constant voltage VDD and the second constant voltage GND outputs according to the second row control signal GCS2.

Here, the first and second operational amplifiers 11 and 12 compare the input voltage Input input to the first input terminal (+) and the data voltage Output fed back to the second input terminal (−) and input the same. Outputs an output voltage that converges with the voltage input.

The first operational amplifier 11 is a P-type operational amplifier and the second operational amplifier 12 is an N-type operational amplifier. Accordingly, the first operational amplifier 11 compensates for the offset voltage and outputs the positive input voltage Input and the second operational amplifier 12 responds to the negative input voltage Input, respectively. In addition, the first switching element Tr1 may be formed of a P-type transistor, and the second switching element Tr2 may be formed of an N-type transistor.

FIG. 2 is a waveform diagram illustrating input / output signals of the analog buffer shown in FIG. 1.

After the first constant voltage VDD is output in the charging section, the output signal of the analog buffer shown in FIG. 2 is output in the driving section, and the output voltage Converging with the input voltage is output. 2 shows the waveform on which the constant voltage GND is output.

The driving method of the analog buffer shown in FIG. 1 will be described with reference to FIGS. 1 and 2 as follows.

First, the first and second switches SW1 and SW2 are turned off in the charging section shown in FIG. As the second high control signal VCS2 from the second controller 14 is supplied to the first switching element Tr1, the first positive voltage VDD is output. Accordingly, the first positive voltage VDD is supplied to the data line connected to the output line of the analog buffer.

Next, in the driving section shown in FIG. 2, the supply of the second high control signal VCS2 from the second controller 14 is stopped, and the first switch SW1 is turned on. Accordingly, an output voltage Output that converges from the first operational amplifier 11 to the input voltage Input is supplied to the data line through the output line.

Thereafter, the operation process at the time of outputting the negative input voltage Input is performed in the same operation as described above by using the second constant voltage GND and the output voltage Output of the second operational amplifier 12.

The analog buffer driven as described above may be driven at a high speed in an enlarged and high resolution liquid crystal panel.

However, the conventional analog buffer driven as described above has the following problems.

In the charging section of the analog buffer, the first constant voltage VDD or the second constant voltage GND is connected to the output line according to the second high control signal VCS2 or the second low control signal GCS2 from the second controller 14. Through the data line. That is, the first constant voltage VDD is provided by the time when the second high control signal VCS2 or the second low control signal GCS2 is supplied from the second controller 14 to the first and second switching elements Tr1 and Tr2. Alternatively, the second constant voltage GND is charged in the output line.

As the first constant voltage VDD or the second constant voltage GND having a fixed level as described above is supplied to the output line in the charging section, the output voltage for displaying data does not reach the level for displaying an image. This happens. That is, when the output voltage OutPut having a large difference from the first constant voltage VDD or the second constant voltage GND is supplied to the output line, the liquid crystal panel in which the output voltage Output does not reach the gradation level of the image to be displayed Is displayed. As described above, a problem occurs that the output voltage Output supplied to the liquid crystal panel is distorted during the driving period due to the fixed level of the first and second constant voltages VDD and GND.

This problem may also occur in the analog buffer included in the output terminal of the gate driver and the common voltage generator.

SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and by generating a pre-charge voltage according to an input voltage and supplying the same to a display panel, an analog buffer, a driving method thereof, and a display using the same which can prevent distortion of a displayed data signal. The purpose is to provide a device.

The analog buffer according to the embodiment of the present invention for achieving the above object outputs an output voltage converged to the input voltage by comparing the input voltage input to the first input terminal and the output voltage fed back to the second input terminal. At least one operational amplifier for outputting a line, and at least one charging unit for generating a pre-charge voltage using the output voltage from the at least one operational amplifier to supply to the output line.

In addition, a display device having an analog buffer according to an embodiment of the present invention for achieving the above object is a display panel for displaying an image, a data driver for supplying an image signal to the display panel, the scan pulse to the display panel A gate driver for supplying a voltage source, a timing controller controlling the data driver and the gate driver, a common voltage generator supplying a common voltage to the display panel, and at least one of the data driver, the gate driver, and the common voltage generator. It is characterized in that it comprises an analog buffer for generating a pre-charge voltage using the output voltage converged to the input voltage and supplied to the output line.

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Hereinafter, an analog buffer, a driving method thereof, and a liquid crystal display using the same according to an exemplary embodiment of the present invention having the above characteristics will be described in detail with reference to the accompanying drawings.

3 is an equivalent circuit diagram illustrating an analog buffer according to an embodiment of the present invention.

The analog buffer shown in FIG. 3 outputs a first operational amplifier 31 that outputs a data voltage Output that converges with the positive input voltage Input according to the first high control signal CSH1 from the first controller 33. ), A second operational amplifier 32 that outputs a data voltage Output that converges with the negative input voltage Input according to the first row control signal CSL1 from the first controller 33, and Generates a pre-charge voltage according to the data voltage (Output) of the first and second operational amplifiers (31, 32), the second high control signal (VCS2) and the second low control signal (GCS2) from the second controller 34 The first and second charging units 21 and 22 output the precharge voltage or the data voltage Output to the output line.

Here, the first and second operational amplifiers 31 and 32 compare the input voltage Input input to the first input terminal (+) and the data voltage Output fed back to the second input terminal (−). Outputs a data voltage (Output) that converges with the voltage (Input).

The first operational amplifier 31 is a P-type operational amplifier and the second operational amplifier 32 is an N-type operational amplifier. Accordingly, the first operational amplifier 31 compensates the data voltage Output fed back in response to the negative input voltage Input and the second operational amplifier 32 compensates with the offset voltage, respectively. Output

The first charging unit 21 applies the first constant voltage VDD according to the first switch SW1 for controlling the input / output of the first constant voltage VDD and the voltage difference between the first constant voltage VDD and the data voltage Output. First and second voltage dividing resistors nR and R for voltage dividing, a second switch SW2 for forming an equipotential at output lines of the first switch SW1 and the first operational amplifier 31, and a first And a third switch SW3 for supplying the voltage divided by the second voltage dividing resistors nR and R to the output line as a precharge voltage, and a data voltage output of the first operational amplifier 31. It includes a fourth switch (SW4) for controlling.

Here, the voltage applied to the divided nodes of the first and second voltage divider resistors nR and R connected in series with the first constant voltage VDD, that is, the divided voltage, is equal to the difference voltage between the first constant voltage VDD and the data voltage Output. The resistance ratios of the first and second voltage divider resistors nR and R are multiplied. The resistance ratio of the first and second voltage dividing resistors nR and R is a value obtained by dividing the first voltage dividing resistor nR by the second voltage dividing resistor R.

The first switch SW1 of the first charging unit 21 is provided at the first constant voltage VDD supply terminal, and the first and second voltage divider resistors nR and R are connected to the first switch SW1 and the first operational amplifier. It is connected in series with the output line of 31 to form a divided node. The second switch SW2 is connected in parallel with the first and second voltage dividing resistors nR and R to the output lines of the first switch SW1 and the first operational amplifier 31. The third switch SW3 is configured in parallel between the divided node formed of the first and second divided resistors nR and R and the output line of the first operational amplifier 31. In addition, the fourth switch SW4 is connected in parallel with the third switch SW3 between the output lines of the first operational amplifier 31.

The second charging unit 22 applies the second constant voltage GND according to the fifth switch SW5 for controlling the input / output of the second constant voltage GND and the voltage difference between the second constant voltage GND and the data voltage Output. Third and fourth voltage dividing resistors nR 'and R' for voltage dividing, a sixth switch SW6 for forming an equipotential at output lines of the fifth switch SW5 and the second operational amplifier 32, A seventh switch SW7 for supplying the voltages divided by the third and fourth voltage dividers nR 'and R' to the output line as a precharge voltage, and the data voltage of the second operational amplifier 32 ( Output) The eighth switch (SW8) for controlling the output.

Here, the voltage applied to the divided nodes of the third and fourth voltage dividing resistors nR 'and R' connected in series with the second constant voltage GND, that is, the divided voltage is the voltage of the second constant voltage GND and the data voltage Output. The difference voltage is a value obtained by multiplying the resistance ratios of the third and fourth divided resistors nR 'and R'. The resistance ratios of the third and fourth divided resistors nR 'and R' are obtained by dividing the third divided resistor nR 'by the fourth divided resistor R'.

The fifth switch SW5 of the second charging unit 22 is provided at the second constant voltage GND supply terminal, and the third and fourth voltage dividers nR 'and R' are connected to the fifth switch SW5 and the second. It is connected in series with the output line of the operational amplifier 32 to form a divided node. The sixth switch SW6 is connected to the output lines of the fifth switch SW5 and the second operational amplifier 32 in parallel with the third and fourth voltage dividers nR 'and R'. The seventh switch SW7 is configured in parallel between the divided nodes formed of the third and fourth divided resistors nR 'and R' and an output line of the second operational amplifier 32. In addition, the eighth switch SW8 is connected in parallel with the seventh switch SW7 to the output line of the first operational amplifier 32.

FIG. 4 is a waveform diagram illustrating input and output signals of the analog buffer shown in FIG. 3.

The output signal of the analog buffer shown in FIG. 4 includes a section in which a data voltage Output converged with an input voltage is output in a first driving section after a precharge voltage is output in a first charging section, and a second signal. After the pre-charging voltage is output in the charging section, the waveform of the section in which the data voltage Output converging with the input voltage Input is output in the second driving section.

Here, the first charging section and the first driving section represent the precharging voltage and the data voltage Output from the first operational amplifier 31 and the first charging unit 21. The second charging section and the second driving section represent the precharging voltage and the data voltage Output from the second operational amplifier 32 and the second charging section 22.

Referring to Figures 3 and 4 will be described in detail the driving method of the analog buffer according to an embodiment of the present invention.

First, in the first charging section shown in FIG. 4, as shown in FIG. 3, the first high control signal CSH1 from the first controller 33 is supplied to the first operational amplifier 31, and the first The operational amplifier 31 outputs an input voltage Input as a data voltage output. The second high control signal VCS2 from the second controller 34 is supplied to the first charging unit 21. Accordingly, the first switch SW1 and the third switch SW3 are turned on, and the second switch SW2 and the fourth switch SW4 are turned off.

In this case, the first constant voltage VDD is supplied to the first to second voltage dividing resistors nR and R through the first switch SW1. Data voltages of the first constant voltage VDD and the first operational amplifier 31 between the first to second voltage dividing resistors nR and R, that is, the voltage dividing node, by the first to second voltage dividing resistors nR and R. The distribution voltage is formed according to the difference voltage of (Output). Accordingly, the divided voltage generated at the divided node is output to the output line through the third switch SW3. The data line connected to the output line is precharged.

As shown in FIG. 5, the first high control signal CSH1 from the first controller 33 is supplied to the first operational amplifier 31 during the first driving period, and the first operational amplifier 31 is input. Output the data voltage (Output) to the output line. At this time, the first operational amplifier 31 outputs a data voltage (Output) and outputs a data voltage (Output) and at the same time feeds it back to compensate for the offset voltage, so that the output voltage converges to the input voltage (Input) output line Will output

Meanwhile, in the first charging unit 21, the first switch SW1 and the third switch SW3 are turned off according to the second high control signal VCS2 from the second controller 34, and the second switch SW2 is turned off. And fourth switch SW4 are turned on.

At this time, since equipotentials are formed in the first to second voltage dividing resistors nR and R connected in parallel with the second switch SW2, the data voltage Input from the first operational amplifier 31 is applied to the fourth switch SW4. ) Is output to the output line.

Here, the precharge voltage precharged to the output line is the first constant voltage VDD and the data voltage Output of the first operational amplifier 31 by the first to second divided resistors nR and R in the first charging section. Since it is a distribution voltage according to the difference voltage of the Δ), there is no significant difference from the data voltage Output from the first operational amplifier 31. That is, the voltage level of the output line charged with the divided voltage is not significantly different from the data voltage Output according to the gray level of the image. Therefore, since the voltage level of the output line changes rapidly to the data voltage (Output) level, the gray scale characteristic of the image data is not distorted, thereby displaying more accurate image data.

Thereafter, although not shown in the second charging section, the first row control signal CSL1 from the first controller 33 is supplied to the second operational amplifier 32, and the second operational amplifier 32 is input. The negative data voltage Output is output to the output line. The second row control signal GCS2 from the second controller 34 is supplied to the second charging unit 22. As a result, the fifth switch SW5 and the seventh switch SW7 are turned on, and the sixth switch SW6 and the eighth switch SW8 are turned off.

At this time, the second constant voltage GND is supplied to the third to fourth voltage divider nR 'and R' through the fifth switch SW5. The difference voltage between the second constant voltage GND and the data voltage Output between the third to fourth divided resistors nR and R, that is, the divided node by the third to fourth divided resistors nR 'and R'. As a result, a distribution voltage is formed. The divided voltage between the third to fourth divided resistors nR 'and R' is output to the output line as a precharge voltage through the seventh switch SW7. The data line connected to the output line is precharged according to the distribution voltage, that is, the precharge voltage.

In the second driving section, the first row control signal CSL1 from the first controller 33 is supplied to the second operational amplifier 32, and the second operational amplifier 32 is input to the negative input voltage Input. Output to the output line. At this time, the second operational amplifier 32 outputs the data voltage Output and simultaneously feeds it back to compensate for the offset voltage, thereby outputting a data voltage Output that converges with the input voltage Input.

Meanwhile, in the second charging unit 22, the fifth switch SW5 and the seventh switch SW7 are turned off according to the second row control signal GCS2 from the second controller 34, and the sixth switch SW6 is turned off. And the eighth switch SW8 are turned on.

At this time, since equipotentials are formed in the third to fourth divided resistors nR 'and R' connected in parallel with the sixth switch SW6, the data voltage Output from the second operational amplifier 32 is controlled by the eighth switch. Output to the output line through (SW8).

Here, the precharging voltage precharged to the output line is caused by the difference between the second constant voltage GND and the data voltage Output by the third to fourth voltage dividing resistors nR 'and R' in the second charging section. Since it was the divided voltage, there is no significant difference from the second operational amplifier 32 data voltage Output. That is, the level of the precharge voltage charged with the divided voltage is not significantly different from the data voltage output according to the gray level of the image. Therefore, since the pre-charge voltage level quickly converges to the data voltage output level, the gray scale characteristic of the image data is not distorted, so that more accurate image data can be displayed.

6 is a block diagram of a liquid crystal display device having an analog buffer according to an embodiment of the present invention.

6 illustrates a liquid crystal panel 60 including a plurality of gate lines GL1 through GLn and a plurality of data lines DL1 through DLm, and a plurality of gate lines GL1 through GLn. A gate driver 62, a data driver 64 for driving the plurality of data lines DL1 to DLm, a timing controller 66 for controlling the gate driver 62 and the data driver 64, and a liquid crystal panel ( And a common voltage generator 68 for generating the common voltage Vcom supplied to the second terminal 60.

The liquid crystal panel 60 includes a TFT formed in each pixel region defined by a plurality of gate lines GL1 to GLn and a plurality of data lines DL1 to DLm, and a liquid crystal capacitor Clc connected to the TFT. The liquid crystal capacitor Clc is composed of a pixel electrode connected to a TFT and a common electrode facing each other with the pixel electrode and the liquid crystal interposed therebetween. The TFT supplies the data signals from the respective data lines DL1 to DLm to the pixel electrodes in response to the scan pulses from the respective gate lines GL1 to GLn. The liquid crystal capacitor Clc charges the difference voltage between the data signal supplied to the pixel electrode and the common voltage supplied to the common electrode, and adjusts the light transmittance by varying the arrangement of liquid crystal molecules according to the difference voltage. The storage capacitor Cst is connected to the liquid crystal capacitor Clc in parallel so that the voltage charged in the liquid crystal capacitor Clc is maintained until the next data signal is supplied. The storage capacitor Cst is formed by overlapping the pixel electrode with the previous gate line and the insulating layer interposed therebetween. In contrast, the storage capacitor Cst may be formed by overlapping the pixel electrode with the storage line and the insulating layer interposed therebetween.

The gate driver 62 includes a shift register that sequentially generates scan pulses, that is, gate high pulses, in response to the gate control signal GCS from the timing controller 66.

The data driver 64 converts the digital image data into analog image data according to the data control signal DCS from the timing controller 66 and one horizontal period every horizontal period in which scan pulses are supplied to the gate lines GL1 to GLn. Analog image data for a line is supplied to the data lines DL1 to DLm. That is, the data driver 64 selects a gamma voltage having a predetermined level according to the gray value of the analog image data and supplies the selected gamma voltage to the data lines DL1 to DLm.

The common voltage generator 68 generates a common voltage Vcom and supplies it to the common electrode of the liquid crystal panel 60.

 Here, the gate driver 62, the data driver 64, and the common voltage generator 68 are analog for preventing the driving signals supplied to the gate lines GL1 to GLn and the data lines DL1 to DLm from being distorted. A buffer is provided.

As shown in FIG. 3, the analog buffer outputs a first operational amplifier configured to output a data voltage Output that converges with the positive input voltage Input according to the first high control signal CSH1 from the first controller 33. A second operational amplifier 32 that outputs a data voltage Output that converges with the negative input voltage Input in response to the first row control signal CSL1 from the first controller 33; In addition, a pre-charge voltage is generated according to the data voltages (Output) of the first and second operational amplifiers 31 and 32, and the second high control signal VCS2 and the second low control signal from the second controller 34 are generated. First and second charging units 21 and 22 outputting a pre-charging voltage or a data voltage Output to an output line according to GCS2).

Here, the first and second operational amplifiers 31 and 32 compare the input voltage Input input to the first input terminal (+) and the data voltage Output fed back to the second input terminal (−). Outputs a data voltage (Output) that converges with the voltage (Input).

The first operational amplifier 31 is a P-type operational amplifier and the second operational amplifier 32 is an N-type operational amplifier. Accordingly, the first operational amplifier 31 compensates the data voltage Output fed back in response to the negative input voltage Input and the second operational amplifier 32 compensates with the offset voltage, respectively. Output

The first charging unit 21 applies the first constant voltage VDD according to the first switch SW1 for controlling the input / output of the first constant voltage VDD and the voltage difference between the first constant voltage VDD and the data voltage Output. First and second voltage dividing resistors nR and R for voltage dividing, a second switch SW2 for forming an equipotential at output lines of the first switch SW1 and the first operational amplifier 31, and a first And a third switch SW3 for supplying the voltage divided by the second voltage dividing resistors nR and R to the output line as a precharge voltage, and a data voltage output of the first operational amplifier 31. It includes a fourth switch (SW4) for controlling.

Here, the voltage applied to the divided nodes of the first and second voltage divider resistors nR and R connected in series with the first constant voltage VDD, that is, the divided voltage, is equal to the difference voltage between the first constant voltage VDD and the data voltage Output. The resistance ratios of the first and second voltage divider resistors nR and R are multiplied. The resistance ratio of the first and second voltage dividing resistors nR and R is a value obtained by dividing the first voltage dividing resistor nR by the second voltage dividing resistor R.

The first switch SW1 of the first charging unit 21 is provided at the first constant voltage VDD supply terminal, and the first and second voltage divider resistors nR and R are connected to the first switch SW1 and the first operational amplifier. It is connected in series with the output line of 31 to form a divided node. The second switch SW2 is connected in parallel with the first and second voltage dividing resistors nR and R to the output lines of the first switch SW1 and the first operational amplifier 31. The third switch SW3 is configured in parallel between the divided node formed of the first and second divided resistors nR and R and the output line of the first operational amplifier 31. In addition, the fourth switch SW4 is connected in parallel with the third switch SW3 between the output lines of the first operational amplifier 31.

The second charging unit 22 applies the second constant voltage GND according to the fifth switch SW5 for controlling the input / output of the second constant voltage GND and the voltage difference between the second constant voltage GND and the data voltage Output. Third and fourth voltage dividing resistors nR 'and R' for voltage dividing, a sixth switch SW6 for forming an equipotential at output lines of the fifth switch SW5 and the second operational amplifier 32, A seventh switch SW7 for supplying the voltages divided by the third and fourth voltage dividers nR 'and R' to the output line as a precharge voltage, and the data voltage of the second operational amplifier 32 ( Output) The eighth switch (SW8) for controlling the output.

Here, the voltage applied to the divided nodes of the third and fourth voltage dividing resistors nR 'and R' connected in series with the second constant voltage GND, that is, the divided voltage is the voltage of the second constant voltage GND and the data voltage Output. The difference voltage is a value obtained by multiplying the resistance ratios of the third and fourth divided resistors nR 'and R'. The resistance ratios of the third and fourth divided resistors nR 'and R' are obtained by dividing the third divided resistor nR 'by the fourth divided resistor R'.

The fifth switch SW5 of the second charging unit 22 is provided at the second constant voltage GND supply terminal, and the third and fourth voltage dividers nR 'and R' are connected to the fifth switch SW5 and the second. It is connected in series with the output line of the operational amplifier 32 to form a divided node. The sixth switch SW6 is connected to the output lines of the fifth switch SW5 and the second operational amplifier 32 in parallel with the third and fourth voltage dividers nR 'and R'. The seventh switch SW7 is configured in parallel between the divided nodes formed of the third and fourth divided resistors nR 'and R' and an output line of the second operational amplifier 32. In addition, the eighth switch SW8 is connected in parallel with the seventh switch SW7 to the output line of the first operational amplifier 32.

Since the method of driving the analog buffer has been described above in detail with reference to FIGS. 3 to 5, it will be omitted.

In the liquid crystal display having the analog buffer according to the present invention as described above, the first and second constant voltages VDD are driven by the first to fourth voltage dividers nR and R 'while driving the liquid crystal panel 60. The plurality of data lines DL1 to DLm are precharged with a division voltage corresponding to a difference voltage between the GND and the data voltages of the first and second operational amplifiers 31 and 32. That is, the precharge voltage is generated according to the data voltage output to precharge the plurality of data lines DL1 to DLm.

Accordingly, the difference between the data voltage output of the first and second operational amplifiers 31 and 32 and the pre-charge voltage between the data lines DL1 to DLm is minimized, so that accurate image data can be obtained without distortion of the gray scale characteristic of the image data. I can display it.

The present invention described above is not limited to the above-described embodiment and the accompanying drawings, it is conventional in the art that various substitutions, modifications and changes are possible without departing from the technical spirit of the present invention. It will be evident to those who have knowledge of.

As described above, the analog buffer, the driving method thereof, and the display device using the same according to the embodiment of the present invention have the following effects.

The present invention generates a pre-charge voltage according to the data voltage supplied to the display panel or supplies it to the output line. Accordingly, by minimizing the level difference between the data voltage and the pre-charge voltage, it is possible to display accurate image data without distorting the gray scale characteristic of the image data.

Claims (17)

At least one operational amplifier comparing the input voltage input to the first input terminal with the output voltage fed back to the second input terminal and outputting an output voltage converged to the input voltage to an output line; And And at least one charger configured to generate a precharge voltage using the output voltage from the at least one operational amplifier and supply the precharge voltage to the output line. The method of claim 1, The at least one charging unit A first switching element for controlling input and output of the first and second constant voltages, First and second voltage divider resistors for generating a precharge voltage according to the difference voltage between the first and second constant voltages and the output voltage; A second switching element for forming an equipotential in the first and second voltage divider resistors and the output line; A third switching element for supplying the precharge voltage to the output line, and And a fourth switching element for supplying the output voltage to the output line. The method of claim 2, The first switching device And an analog buffer connected to the first and second constant voltage supply terminals and the first and second voltage divider resistors. The method of claim 3, wherein The first and second voltage divider resistance And a divided node connected in series with the first switching element and an output line of the at least one operational amplifier. 5. The method of claim 4, The second switching device And an analog buffer connected to the first switching element and the output line in parallel with the first and second voltage divider resistors. 6. The method of claim 5, The third switching device is And the divided node formed by the first and second divided resistors and the output line in parallel with the at least one operational amplifier. The method of claim 6,  The fourth switching element is And at least one operational amplifier in series with the output line. A display panel for displaying an image; A data driver for supplying an image signal to the display panel; A gate driver supplying a scan pulse to the display panel; A timing controller controlling the data driver and the gate driver; A common voltage generator supplying a common voltage to the display panel; And And an analog buffer provided in at least one of the data driver, the gate driver, and the common voltage generator to generate a precharge voltage using an output voltage converging to an input voltage and supply the precharge voltage to an output line. . 9. The method of claim 8, The analog buffer At least one operational amplifier for comparing the input voltage input to the first input terminal with the output voltage fed back to the second input terminal and outputting the output voltage converged to the input voltage to the output line; And at least one charger configured to generate a precharge voltage using the output voltage from the at least one operational amplifier and supply the precharge voltage to the output line. The method of claim 9, The at least one charging unit A first switching element for controlling input and output of the first and second constant voltages, First and second voltage divider resistors for generating a precharge voltage according to the difference voltage between the first and second constant voltages and the output voltage; A second switching element for forming an equipotential in the first and second voltage divider resistors and the output line; A third switching element for supplying the precharge voltage to the output line, and And a fourth switching element for supplying the output voltage to the output line. 11. The method of claim 10, The first switching device And a first and a second constant voltage supply terminals and the first and second voltage divider resistors. The method of claim 11, The first and second voltage divider resistance And a divided node connected in series with the first switching element and an output line of the at least one operational amplifier. 13. The method of claim 12, The second switching device And a display device connected to the first switching element and the output line in parallel with the first and second voltage divider resistors. The method of claim 13, The third switching device is And a divided node formed by the first and second divided resistors and the output line in parallel with the at least one operational amplifier. 15. The method of claim 14,  The fourth switching element is And a display device connected in series with the at least one operational amplifier and the output line. delete delete

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