KR0140703B1 - A method manufacture of polysilicon soure/drain - Google Patents

Abstract

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Description

Method for manufacturing self-aligned sloped polysilicon source / drain cells

1 is a source / drain formation process diagram according to a conventional ion implantation process

2 is a process diagram of self-aligned sloped polysilicon source / drain formation of the present invention.

3 is a comparison of the source / drain formation by the present invention and the conventional process,

(a) is a complete cross-sectional view of source / drain using conventional polysilicon

(b) is an enlarged view of portion A of (a)

(c) is a completed cross-sectional view of a slinging source / drain of the present invention.

* Explanation of symbols for main parts of the drawings

1: silicon substrate 2: feed oxide

3,5: gate oxide 4: source / drain

6: gate

FIELD OF THE INVENTION The present invention relates to a method for fabricating a self-aligned (sloping) polysilicon source / drain cell during a semiconductor manufacturing process, in particular using a shallow junction and shallow junction using a polysilicon source / drain process. It improves the step coverage characteristics, making it suitable for use in high grade devices.

Source / drain fabrication methods of conventional DRAMs include a method of performing an ion implantation process on a silicon substrate and a method using polysilicon doped at an appropriate concentration.

First, in the ion implantation method, as shown in (a) of FIG. 1, the first gate oxide 3 was formed after the formation of the oxide oxide 2 on the silicon substrate 1 and ion implantation was performed to control the threshold voltage.

Next, as shown in (b), the first gate oxide 3 was removed, and an oxidation process, a polysilicon deposition process, and a doping operation for the second gate oxide 5 were performed.

In addition, as shown in (c), polysilicon was limited and etched through the photo work to form the gate 6, and ion implantation for LDD (Lightly Doped Drain) or DILDD (Double Implant Lightly Doped Drain) was performed. .

Next, as shown in (d), the low-temperature deposition oxide (LTO) deposition and sidewall etching for forming the sidewalls of the gate 6 are performed, followed by patterning the source / drain 4 through photo work, and source / drain ions. Injection and annealing were performed.

On the other hand, the method using polysilicon is as follows.

That is, the first gate oxide was formed, ion implantation was performed to control the threshold voltage, the first gate oxide was removed, and polysilicon doping was performed through polysilicon deposition and ion implantation for source / drain.

Next, patterning was performed to form source / drain regions, and silicon nitride deposition was performed after patterning to prevent breakdown of the gate and source / drain.

In addition, after the oxidation operation for the gate oxide formation, the polysilicon deposition operation for the gate formation and patterning operation to form a gate.

However, in the case of the former, in the case of the former, due to the channeling problem of the ion implantation process, it is difficult to form a shallow junction due to high integration, and the gate 6 is formed on the silicon surface. Coverage worsened and there was a difficulty in forming the metal line.

In the latter case, the silicon nitride layer forming process for preventing breakdown between the source / drain and the gate is complicated and reliability is easily deteriorated due to the compressive stress of the film.

The present invention has been devised in view of the above-mentioned general drawbacks, which will be described in detail with reference to an example of NMOS according to FIG. 2.

First, as shown in (a), after the formation of the oxide oxide 2 on the silicon substrate 1, the first gate oxide 3 is formed and ion implantation is performed to control the threshold voltage.

Next, as shown in (b), polysilicon deposition (or PoCl ₃ doping for polysilicon deposition and doping, polysilicon deposition and phosphorus for doping to remove the first gate oxide (3) and form a source / drain) Phosphorus ion implantation.

Then, as shown in (c), ions (arsenic or phosphorus) for the slitting etch are ion implanted in the energy range of 5-80Kev and the dose range of 1E15-2E16 Ions / cm ² and then the source / drain (4) Photo work for the formation and the slitting etch work and oxidation work for the second gate oxide (5) formation.

Next, as shown in (d), polysilicon (or polyside) deposition for forming the gate 6 is performed and patterned.

The polysilicon source / drain cell manufacturing method of the present invention by such a manufacturing process can easily obtain the required cell junction as the device is highly integrated, and thus can solve the step coverage problem caused by the high step height. have.

In addition, the formation of the sloped polysilicon source / drain 4 results in a weak point (C, D in FIG. 3) which causes breakdown between the gate 6 and other layers (e.g., Si ₃ N ₄ , this solution can be solved without the need of 7) and the thickness of the source / drain polysilicon 4a near the gate 6 region is thin (B in Fig. 3 (c)) to achieve the LDD effect naturally. .

In addition, the present invention can obtain an area increase of the thickness of the source / drain polysilicon 4a when forming a stack capacitor, and have the same effect as that of the pad poly upon subsequent metal contact.

Claims (3)

In the formation of the first gate oxide (3) after the formation of the feed oxide (2) on the silicon substrate (1) and ion implantation for controlling the threshold voltage, the first gate oxide (3) is removed and the source / drain is removed. After the polysilicon deposition to form, ion implantation for the slitting etch, photo operation for the formation of the source / drain (4) and the etching operation for the formation of the slope, and oxidation for the formation of the gate oxide (5) are performed. A method for producing a self-aligned sloped polysilicon source / drain cell, characterized in that the polysilicon deposition operation and the patterning operation for forming are performed. 2. The method of claim 1, wherein the implantation of the sloping ions is carried out using arsenic or phosphorus ions with an energy of 5-80 Kev and a dose of 1E15-2E16 Ions / cm ² . . 2. A method according to claim 1, characterized in that the thickness of the source / drain polysilicon (4a) in the gate (6) forming area is made thin through the slitting etch.