JPS6356959A - Manufacture of field-effect transistor - Google Patents

Abstract

PURPOSE:To provide a field-effect transistor having improved property of saturat ing drain current and improved transconductance even if a gate length is de creased, by providing a highconcentration conducting layer such that it is located at a shallow level and has a decreased concentration while providing an ohmic electrode close to a gate electrode. CONSTITUTION:A channel layer 5 and a provisional gate pattern 6 are provided on a semiconductor substrate 4 formed of semi-insulating GaAs. Si<+> ions are implanted with the pattern 6 used as a mask to provide high-concentration conducting layers 7a and 7b. Side walls 8 of a silicon nitride film are formed on the side faces of the provisional gate pattern 6. An ohmic metal Au.Ge.Ni 9 is vapor deposited and a photoresist film 10 is applied thereon. The ohmic metal 9 on the provisional gate pattern 6 is removed so as to provide separate ohmic metal portions 9a and 9b. After the residual photoresist film 10 is re moved, the substrate is heat treated within hydrogen so that the ohmic metal Au.Ge.Ni in 9a and 9b is diffused into the high concentration conducting layer 7 of the GaAs substrate to produce an ohmic electrode. Subsequently, a nitride film is formed as an inversion film 11 on the whole surface by means of the sputtering process and a gate aperture 14 is provided.

Description

DETAILED DESCRIPTION OF THE INVENTION ['Industrial Field of Application] The present invention relates to a method for manufacturing a field effect transistor, and particularly to a method for manufacturing a field effect transistor having a shallow highly doped conductive layer and an ohmic electrode close to a gate portion. Regarding.

[Conventional technology]

Compound semiconductors, represented by GaAs, are characterized by higher electron mobility than Si, and research and development are actively being conducted to apply them to ultra-high-speed integrated circuits. Here, a GaAs Schottky barrier gate field effect transistor (hereinafter referred to as MESFET) will be explained as an example.

As a manufacturing method of this MESFET,
There is one proposed in the No. 978 publication. Figure 3 (a
) to (h) are cross-sectional views of main steps for explaining this manufacturing method.

First, as shown in FIG. 3(a), Si+ is applied to a semiconductor substrate 4 made of semi-insulating GaAs at an accelerating voltage of 30 KeV.

A channel layer 5 is formed by ion implantation at a dose of 2×10 12 cm −2 . Next, as shown in FIG. 3<b>, a silicon oxide film of 0.8 μm is vapor-phase grown on the semiconductor substrate 4, and the oxide film is etched by parallel plate dry etching using the photoresist film as a mask to form a gate with a gate length of 1.0 μm.
A temporary gate pattern 6 of μm is formed.

Next, as shown in FIG. 3(c), using the temporary gate pattern 6 as a mask, Si" was accelerated at a voltage of 100 KeV and at a dose of Bk.
High concentration conductive layers 7a and 7b are formed by ion implantation at 3 x 10" cm-2. Next, as shown in FIG. The crystallinity of the channel layer 5 and the highly doped conductive layers 7a and 7b is restored by heat treatment at 800'C for 20 minutes in hydrogen.

Next, as shown in FIG. 3(C), when the photoresist film 12 is applied to a thickness of 1.0 to 1 m, the surface of the photoresist film 12 becomes smooth, and the photoresist film 12 on the temporary gate pattern 6
becomes thinner. Next, as shown in FIG. 3(f), the entire surface is etched by parallel plate dry etching using CF4 gas to expose the temporary gate pattern 6 of the acid-etched film.

Next, as shown in FIG. 3(g), the remaining photoresist film 12 is removed using a stripping solution, and the oxide film 6 of the temporary gate pattern is removed using a hydrofluoric acid solution to form a gate opening 14. Next, as shown in FIG. 3(h), a gate electrode 1 made of aluminum is placed in the opening 14, and a source electrode 2 made of ohmic metal Au-Ge-Ni is placed on the high concentration conductive layers 7a and 7b. A drain electrode 3 is formed to complete the MESFET.

The feature of this manufacturing method is that after high-temperature heat treatment, the gate electrode 1
Since it is possible to form a gate electrode, there is a large degree of freedom in selecting the gate electrode.

[Problem that the invention seeks to solve]

In order to increase the mutual conductance (gm) of the FET, it is necessary to shorten the gate length and reduce the resistance (source resistance) between the source and the electrode. Shigashi,
The highly concentrated conductive layer formed by ion implantation has a size of 8 x 10 under normal annealing conditions such as in the conventional double series.
It is difficult to activate the layer to a level higher than ``ClTl-''.If the highly doped conductive layer is made deeper and thicker in an attempt to lower the source resistance, the lateral diffusion of the implanted impurities under the gate and the substrate leakage current will increase, resulting in Current saturation deteriorates and mutual conductance also decreases.

An object of the present invention is to provide a field effect transistor that has good drain current saturation and mutual conductance even when the gate length is shortened.

[Means for solving problems]

The method for manufacturing a field effect transistor of the present invention includes a step of forming a channel layer on a semiconductor substrate, a step of forming a temporary gate pattern to determine a gate shape on the channel layer, and a step of forming a temporary gate pattern on the channel layer. A step of injecting impurities using an ion implantation method as a mask to form a highly concentrated conductive layer on the surface of the semiconductor substrate, a step of forming sidewalls made of a dielectric film on the sides of the temporary gate pattern, and a step of forming an ohmic metal on the entire surface. a step of removing the ohmic metal on the part of the temporary game I/pattern, covering the surface of the semiconductor substrate with a coating film and removing the coating film on the temporary game/pattern; The method includes a step of selectively removing only the temporary gate pattern to form a gate pattern, and a step of forming a gate electrode in the gate opening.

[Function] The manufacturing method of the present invention reduces lateral diffusion of the ion-implanted layer by providing the highly concentrated conductive layer at a shallow angle of 12 degrees, and by providing the ohmic electrode close to the gate electrode. This reduces source resistance.

〔Example〕

Next, a method for manufacturing a field effect transistor according to the present invention will be explained with reference to the drawings.

FIGS. 1A to 1H are cross-sectional views of a semiconductor chip in main manufacturing steps for explaining a first embodiment of the present invention.

First, as shown in FIG. 1(a), semi-insulating Ga is used. A channel layer 5 is formed by ion-implanting Si+ into a semiconductor substrate 4 made of S at an acceleration voltage of 30 Ke and a dose of 2.times.10' 2 cm.sup.-2. Subsequently, after forming a silicon oxide film on the entire surface, the silicon oxide film is processed by parallel plate dry etching using the photoresist film pattern as a mask to form a temporary gate pattern 6 with a height of 0.8 μm and a gate length of 0.5 μm. . Next, using the temporary gate pattern 6 as a mask, Si + was accelerated at a voltage of 30 KeV and at a dose of 7×10.
High concentration conductive layers 7a and 7b are provided by ion implantation at a depth of 12 cm.sup.-2.

Next, as shown in FIG. 1(b), the entire surface is covered with a sputtered silicon nitride film with a thickness of 0.1 μm, and heat treatment is performed at 800° C. for 20 minutes in hydrogen to form the channel layer 5 and the highly concentrated conductive layer 7.
The crystallinity of a and 7b was restored, and a silicon nitride film with a thickness of 0.2 μm was added by sputtering to cover the CF4
Perform parallel plate dry etching using gas,
A side wall 8 made of a silicon nitride film with a thickness of 0.3 μm is left on the side surface of the temporary gate pattern 6.

Next, as shown in FIG. 1(c), after cleaning the GaAs surface by organic cleaning, ohmic metal U-Ge-Ni9 is deposited to a thickness of 0.2 μm, and a photoresist film 10 is deposited on it to a thickness of 1.5 μm. Apply 0μm. At this time, the photoresist film 10 on the temporary gate pattern 6 becomes thinner.

Next, as shown in FIG. 1(d), the entire surface is etched by ion milling using Ar gas to remove the ohmic metal 9 on the temporary gate pattern 6, and the ohmic metal 9a and 9
Separate b. Here, ion milling is performed on the semiconductor substrate 4.
While rotating ^ ``Do this at an angle of incidence of 30°.

Next, as shown in FIG. 1(e), the remaining photoresist film 10
After removing the ohmic metals Au-Ge and Ni9a, heat treatment was performed at 430°C for 1 minute in hydrogen.

9b is diffused several tens of nanometers into the highly doped conductive layer 7 of the GaAs substrate to form an ohmic electrode. Ohmic metal 9a attached to the side surface of sidewall 8 made of silicon nitride film.

When 9b is heat treated, it softens and is attracted by surface tension and disappears.

Next, as shown in FIG. 1 (f>), a nitride film of 0.3 μm thick is formed by sputtering as the inversion film 11 over the entire surface.Next, as shown in FIG. An opening 14 is provided.

Subsequently, as shown in FIG. 1<h), an aluminum gate electrode 1 is provided in the gate opening. and ohmic metal 9a,
The nitride film 11 on 9b is removed, and a source electrode 2 and a drain electrode 3 are formed to complete the MESFET.

The characteristics of the FET obtained by this first example are as follows: gate threshold voltage VT=-0.3V (standard deviation 30m
In V), the mutual conductance gm = 480mS/mm, the source resistance Rs = 0.4Ω-mm, and the gate reverse breakdown voltage BVG-7V at a voltage of 0.6. Further, the drain feedback rate γ, which indicates the saturation property of the train current, was “Vt1” and Vo=0.02.

If a conventional manufacturing method is used to form a deep ion-implanted high-concentration conductive layer and the gate length is 0.5 μm, VT = -
At 0.4V (standard deviation 120mV>, gm=
240ms/mm, Rs -0, 7Ω -mrr3
BVG = -4V, 7 = 0.12.

Thus, it can be seen that in the FET manufactured in the first example, the standard deviation of the gate threshold voltage, the source resistance, and the drain feedback factor are reduced, and the mutual conductance and gate reverse breakdown voltage are improved.

The above description mainly refers to MESFETs, but is not limited thereto. Next, a second embodiment applied to a two-dimensional electron gas field effect transistor will be described. FIGS. 2(a) to 2(c) are cross-sectional views of main manufacturing steps for explaining the second embodiment. .

First, as shown in FIG. 2(a), undoped G is formed on a semiconductor substrate 4 made of semi-insulating GaAs by molecular beam crystal growth.
An aAs layer (channel layer) 21 is grown to a thickness of 1.0 μm,
Subsequently, an electron supply layer 22 made of GaAffAs doped with 1.5×1018 cm of Si is formed to a thickness of 40 cm.
grow by nm.

Next, as shown in FIG. 2(b), a temporary gate pattern 6 having a height of 0.8 μm and a gate length of 0.5 μm is formed in the same manner as in the first embodiment, and then using the temporary gate pattern 6 as a mask, St+ Accelerating voltage 50KeV, dose amount 3X10"c
High concentration conductive layers 7a and 7b are provided by m-2 ion implantation,
The crystallinity of the highly concentrated conductive layers 7a and 7b is restored without heat treatment at 850° C. for 10 seconds using As1I3 gas. and,
The entire surface is covered with a silicon nitride film with a thickness of 0.3 μm formed by sputtering, and a side wall 8 of a silicon nitride film with a thickness of 0.3 μm is provided by performing parallel plate dry etching using CF4 gas. Thereafter, high concentration conductive layers 7a and 7b are etched by parallel plate dry etching using CCl4 gas.
Dig into nm.

Next, as shown in FIG. 2(c), after cleaning the semiconductor surface by organic cleaning, the ohmic metal 9
A and 9b are provided, and heat treatment is performed at 450° C. for 1 minute to diffuse the ohmic metals 9a and 9b into the high concentration conductive layers 7a and 7b, which can be used as source electrodes and drain electrodes. Thereafter, an aluminum gate electrode 1 is provided in the same manner as in the first embodiment, thereby completing the field effect transistor.

Since carriers are generated inside the undoped GaAs layer 21 by the electron supply layer 22 made of GaAlAs and a channel is formed, the undoped GaAs layer 21 becomes a channel layer in the two-dimensional electron gas field effect transistor.

The characteristics of the FET obtained in this second embodiment are as follows: gate threshold voltage ■□=-0.3V, maximum mutual conductance gm=380ms/mm, source resistance Rs=
A good value of O15Ω-mm was obtained.

〔Effect of the invention〕

As explained above, according to the manufacturing method of the present invention, by making the highly doped conductive layer shallow and lowering the impurity concentration, lateral diffusion and substrate leakage are reduced, and drain current saturation and gate threshold voltage are reduced. The dispersion is improved. By providing the ohmic electrode close to the gate electrode, the source resistance can be lowered and the mutual conductance can be increased.

Furthermore, in the present invention, since the gate electrode is formed later, a material with low resistivity is also used thickly for the gate electrode, which has the effect of lowering the gate resistance.

[Brief explanation of drawings]

1(a) to 1(h) are cross-sectional views of a semiconductor chip in main steps for explaining the first embodiment of the present invention, and FIG.
Figures (a) to (C) are cross-sectional views of a semiconductor chip in main steps for explaining the second embodiment of the present invention, and Figure 3 (
1A to 1H are cross-sectional views for explaining a conventional method of manufacturing a field effect transistor. DESCRIPTION OF SYMBOLS 1... Gate electrode, 2... Source electrode, 3... Train electrode, 4... Semiconductor substrate, 5... Channel layer, 6... Temporary gate pattern, 7a, 7b... Height Concentrated conductive layer, 8... Side wall, 9.9a, 9b... Ohmic metal, 11... Inversion film, 10.12... Resist film, 13... Inversion pattern, 14... Gate Opening. Mature 1 Floy anti-gate "Evening 9 (C) (d) Ushi! ■ (C) ke) (h) Ushi 2 Figure 9α O4 Small master kqb Early 3 Figure (b) 7α Manko Venerable 17b (,,C), 1/L conversion vL (d)

Claims (1)

[Claims] A step of forming a channel layer on a semiconductor substrate, a step of forming a temporary gate pattern for determining a gate shape on the channel layer, and a step of implanting impurities by ion implantation using the temporary gate pattern as a mask, and then implanting an impurity into the semiconductor substrate. a step of forming a highly concentrated conductive layer on the surface; a step of forming a sidewall made of a dielectric film on the side surface of the temporary gate pattern;
A step of depositing an ohmic metal on the entire surface and removing the ohmic metal above the temporary gate pattern, and a step of covering the surface of the semiconductor substrate with a coating film and removing the coating film above the temporary gate pattern. A method for manufacturing a field effect transistor, comprising the steps of: selectively removing only a gate pattern to form a gate opening; and forming a gate electrode in the gate opening.