JPS63155646A - Formation of multilayer interconnection - Google Patents
Formation of multilayer interconnectionInfo
- Publication number
- JPS63155646A JPS63155646A JP30231186A JP30231186A JPS63155646A JP S63155646 A JPS63155646 A JP S63155646A JP 30231186 A JP30231186 A JP 30231186A JP 30231186 A JP30231186 A JP 30231186A JP S63155646 A JPS63155646 A JP S63155646A
- Authority
- JP
- Japan
- Prior art keywords
- insulating film
- electrode layer
- layer
- interlayer insulating
- electrode
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 230000015572 biosynthetic process Effects 0.000 title 1
- 239000010410 layer Substances 0.000 claims abstract description 93
- 239000011229 interlayer Substances 0.000 claims abstract description 33
- 239000007772 electrode material Substances 0.000 claims abstract description 22
- 238000005530 etching Methods 0.000 claims abstract description 11
- 239000000758 substrate Substances 0.000 claims abstract description 10
- 239000004065 semiconductor Substances 0.000 claims abstract description 7
- 238000000034 method Methods 0.000 abstract description 13
- 229910021420 polycrystalline silicon Inorganic materials 0.000 abstract description 5
- 229920005591 polysilicon Polymers 0.000 abstract description 5
- 238000001312 dry etching Methods 0.000 description 7
- 238000001020 plasma etching Methods 0.000 description 6
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 5
- 229910052782 aluminium Inorganic materials 0.000 description 5
- 238000007796 conventional method Methods 0.000 description 3
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- 230000003647 oxidation Effects 0.000 description 2
- 238000007254 oxidation reaction Methods 0.000 description 2
- 238000000206 photolithography Methods 0.000 description 2
- 229910052814 silicon oxide Inorganic materials 0.000 description 2
- 238000004544 sputter deposition Methods 0.000 description 2
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 210000004709 eyebrow Anatomy 0.000 description 1
- 238000004518 low pressure chemical vapour deposition Methods 0.000 description 1
- 229910052698 phosphorus Inorganic materials 0.000 description 1
- 239000011574 phosphorus Substances 0.000 description 1
Landscapes
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
Description
【発明の詳細な説明】
（イ）産業上の利用分野
本発明は多層配線の形成方法、特に平坦化された多層配
線の形成方法に関する。DETAILED DESCRIPTION OF THE INVENTION (A) Field of Industrial Application The present invention relates to a method for forming multilayer wiring, and particularly to a method for forming flattened multilayer wiring.
（ロ）従来の技術
従来の多層配線の形成方法を第２図Ａ乃至第２図Ｃを参
照して詳述する。なお斯る従来技術は特開昭６０−１４
０７３５号公報（ＨＯＩ Ｌ２１／８８）等で知られて
いる。(B) Prior Art A conventional method for forming multilayer wiring will be described in detail with reference to FIGS. 2A to 2C. Furthermore, such conventional technology is disclosed in Japanese Unexamined Patent Application Publication No. 1986-14.
It is known from Publication No. 0735 (HOI L21/88).
先ず第２図Ａに示すように、半導体基板（１１）上の酸
化膜（１２）上に所望のパターンを有するリンドープし
たポリシリコン層より成る第１の電極層（１３）を形成
し、この第１の電極層（１３）を被覆する層間絶縁膜（
１４）を付着している。First, as shown in FIG. 2A, a first electrode layer (13) made of a phosphorus-doped polysilicon layer having a desired pattern is formed on an oxide film (12) on a semiconductor substrate (11). An interlayer insulating film (
14) is attached.
半導体基板（１１）内にはＭＯ８Ｉ−ランジスク等の所
望の回路素子が組み込まれ、基板（１１）表面には熱酸
化等でゲート酸化膜あるいはフィールド酸化膜等のシリ
コン酸化膜（１２）が形成される。この酸化膜（１２）
上には全面にリンドープしたポリシリコン層が減圧ＣＶ
Ｄ法等で付着された後、所望のパターンの第１の電極層
（１３）がホトリソ工程を用いて形成される。層間絶縁
膜（１４）としてはリンドープしたＰＳＧ膜を用い、酸
化膜（１２）上に約１００００へ以上の厚みにＣＶＤ法
で付着され且つ層間絶縁膜（１４）上面の平坦化も行な
う。Desired circuit elements such as MO8I-randisk are incorporated into the semiconductor substrate (11), and a silicon oxide film (12) such as a gate oxide film or a field oxide film is formed on the surface of the substrate (11) by thermal oxidation or the like. Ru. This oxide film (12)
On top is a polysilicon layer doped with phosphorus over the entire surface under reduced pressure CVD.
After being deposited using the D method or the like, a first electrode layer (13) having a desired pattern is formed using a photolithography process. A phosphorus-doped PSG film is used as the interlayer insulating film (14), and is deposited on the oxide film (12) to a thickness of approximately 10,000 µm or more using the CVD method, and the upper surface of the interlayer insulating film (14) is also planarized.
次に第２図Ｂに示すように、第１の電極層（１３）上の
層間絶縁膜（１４）にコンタクト孔（１５）を形成し、
層間絶縁膜（１４）上全面に電極材料層（１６）を付着
する。Next, as shown in FIG. 2B, a contact hole (15) is formed in the interlayer insulating film (14) on the first electrode layer (13),
An electrode material layer (16) is deposited on the entire surface of the interlayer insulating film (14).
コンタクト孔（１５）は第１の電極層（１３）上の層間
絶縁膜り１４）を露出してレジスト工程で被覆した後、
ＲＩＥ等のドライエツチングを用いて形成され、所望の
第１の電極層（１３）を露出する。然る後層間絶縁膜（
１４）全面に第２の電極層（１７）を形成するためのア
ルミニウム等の電極材料層（１６〉をスパッタにより付
着する。この電極材料層＜１６）はコンタクト孔（１５
）を介して第１の電極層（１３）とオーミックコンタク
トされる。The contact hole (15) is formed by exposing the interlayer insulating film 14) on the first electrode layer (13) and covering it with a resist process.
It is formed using dry etching such as RIE to expose the desired first electrode layer (13). After that, an interlayer insulating film (
14) Deposit an electrode material layer (16> such as aluminum by sputtering to form a second electrode layer (17) on the entire surface. This electrode material layer <16) is attached to the contact hole (15).
) is in ohmic contact with the first electrode layer (13).
更に第２図Ｃに示すように、電極材料層（１６）をを所
望のパターンにエツチングして第２の電極層（１７〉を
形成している。Furthermore, as shown in FIG. 2C, the electrode material layer (16) is etched into a desired pattern to form a second electrode layer (17).
電極材料層（１６）は所望のパターンのレジスト層（１
８）で選択的に被覆し、ＲＩＥ等のドライエツチングに
より所望のパターンの第２の電極層（１７〉を形成する
。The electrode material layer (16) is a resist layer (1) with a desired pattern.
8), and dry etching such as RIE is performed to form a second electrode layer (17) in a desired pattern.
（ハ）発明が解決しようとする問題点
しかしながら第２の電極層（１７）の微細化加工が進む
につれて種々の問題点が発生する。(c) Problems to be Solved by the Invention However, as the second electrode layer (17) becomes finer, various problems arise.
第１にＲＩＥ等のドライエツチングを用いるとレジスト
層（１８）とアルミニウム等の電極材料層（１６）との
エツチング選択比が悪いために、レジスト層（１８）を
２．０〜２．５μｍと厚く付着されなくてはならず微細
化しにくい問題点がある。Firstly, when dry etching such as RIE is used, the etching selectivity between the resist layer (18) and the electrode material layer (16) such as aluminum is poor, so the resist layer (18) has a thickness of 2.0 to 2.5 μm. There is a problem that it must be deposited thickly and is difficult to miniaturize.
第２に微細化に伴い、第２図Ｃに示すようにレジスト層
（１８）がコンタクト孔（１５）よりずれて形成きれる
場合があり、ドライエツチング時に電極材料層（１６）
とともに第１の電極層（１３）もエツチングされ、第１
の電極層（１３）が薄くなり抵抗値が増大したりあるい
は基板（１１）までエツチングされる等の問題点がある
。Second, with miniaturization, the resist layer (18) may be formed completely shifted from the contact hole (15) as shown in Figure 2C, and the electrode material layer (16) may be completely formed during dry etching.
At the same time, the first electrode layer (13) is also etched, and the first electrode layer (13) is also etched.
There are problems such as the electrode layer (13) becoming thinner and the resistance value increasing, or even the substrate (11) being etched.
第３に層間絶縁膜（１４）にオーバーハングした部分が
あると、電極材料層（１６）が残りショー１〜する問題
点がある。Thirdly, if there is an overhanging portion of the interlayer insulating film (14), there is a problem that the electrode material layer (16) remains.
（ニ）問題点を解決するための手段
本発明は斯上した種々の問題点に鑑みてなされ、層間絶
縁膜に予じめ段差を形成した後に第２の電極層を全面エ
ツチングにより形成することにより、従来の種々の問題
点を大幅に改善した多層配線の形成方法を提供するもの
である。(d) Means for Solving the Problems The present invention has been made in view of the various problems mentioned above, and includes forming steps on the interlayer insulating film in advance and then forming the second electrode layer by etching the entire surface. This provides a method for forming multilayer interconnections that greatly improves the various problems of the conventional method.
（ホ）作用
本発明に依れば、層間絶縁膜に予じめ段差を形成してお
き、この段差に電極材料層を充填して第２の電極層を形
成しているので、第２の電極層を形成する際にレジスト
工程を必要とせずセルファラインにより第２の電極層を
形成できる点に特徴がある。(E) Function According to the present invention, a step is formed in advance in the interlayer insulating film, and the step is filled with the electrode material layer to form the second electrode layer. A feature of this method is that the second electrode layer can be formed by self-aligning without requiring a resist process when forming the electrode layer.
（へ）実施例
本発明の一実施例を第１図Ａ乃至第１図Ｅを参照して詳
述する。(F) Embodiment An embodiment of the present invention will be described in detail with reference to FIGS. 1A to 1E.
先ず第１図Ａに示すように、半導体基板（１）上の酸化
膜（２）上に所望のパターンを有するリンドープしたポ
リシリコン層より成る第１の電極層（３）を形成し、こ
の第１の電極層（３）を被覆する層間絶縁膜（４）を付
着している。First, as shown in FIG. 1A, a first electrode layer (3) made of a phosphorus-doped polysilicon layer having a desired pattern is formed on an oxide film (2) on a semiconductor substrate (1). An interlayer insulating film (4) covering the first electrode layer (3) is attached.
半導体基板（１）内にはＭＯＳトランジスタ等の所望の
回路素子が組み込まれ、基板（１）表面には熱酸化等で
ゲート酸化膜あるいはフィールド酸化膜等のシリコン酸
化膜（２）が形成きれる。この酸化膜（２）には全面に
リンドープしたポリシリコン層が減圧ＣＶＤ法等で付着
された後、所望のパターンの第１の電極層（３）がホト
リソ工程を用いて形成される。居間絶縁膜（４）として
はリンドープしたＰＳＧ膜を用い、酸化膜（２）上に約
１５０００〜１８０００人の厚みにＣＶＤ法で付着され
且つ層間絶縁膜（４）上面の平坦化も行なわれる。Desired circuit elements such as MOS transistors are incorporated into the semiconductor substrate (1), and a silicon oxide film (2) such as a gate oxide film or a field oxide film is formed on the surface of the substrate (1) by thermal oxidation or the like. After a phosphorus-doped polysilicon layer is deposited on the entire surface of this oxide film (2) by low pressure CVD or the like, a first electrode layer (3) having a desired pattern is formed using a photolithography process. A phosphorus-doped PSG film is used as the living room insulating film (4), and is deposited on the oxide film (2) to a thickness of about 15,000 to 18,000 yen by CVD, and the upper surface of the interlayer insulating film (4) is also planarized.
次に第１図Ｂに示すように、層間絶縁膜（４）上を選択
的にレジスト層（５）で被覆し、層間絶縁膜（４）を部
分的にエツチングして段差（６）を形成している。Next, as shown in FIG. 1B, the interlayer insulating film (4) is selectively covered with a resist layer (5), and the interlayer insulating film (4) is partially etched to form a step (6). are doing.
レジスト層（５〉は第２の電極層（１０）が延在される
部分を除いて層間絶縁膜（４）上を被覆し、レジスト層
（５）をマスクとして層間絶縁膜（４）をＲＩＥ等のド
ライエツチングにより第２の電極層（１０）の厚みを確
保するのに十分なだけ、例えば約７０００〜１００００
人の段差（６）を形成する。ＰＳＧ膜より成る層間絶縁
膜＜４）のドライエツチングガスとしてＣＦ４を用い、
レジストＮ（５）はＣＦ４ではほとんどエツチングされ
ないのでエツチング選択比を大きく取れ、薄いレジスト
層（５）で段差（６）のエツチングが可能となり微細化
ができる。なお段差（６）は第１の電極層（３）の端部
付近より始まり、第１の電極層（３）上を通り第２の電
極層（１０）の延在方向に形成される。The resist layer (5>) covers the interlayer insulating film (4) except for the portion where the second electrode layer (10) is extended, and RIEs the interlayer insulating film (4) using the resist layer (5) as a mask. The thickness is sufficient to ensure the thickness of the second electrode layer (10) by dry etching, for example, about 7,000 to 10,000.
Form a person's step (6). Using CF4 as a dry etching gas for an interlayer insulating film <4) consisting of a PSG film,
Since the resist N (5) is hardly etched with CF4, a large etching selection ratio can be obtained, and the step (6) can be etched with a thin resist layer (5), allowing for miniaturization. Note that the step (6) starts near the end of the first electrode layer (3), passes over the first electrode layer (3), and is formed in the extending direction of the second electrode layer (10).
更に第１図Ｃに示すように、第１の電極層（３）上の層
間絶縁膜（４）の段差（６）の部分にコンタクト孔（７
）を形成する。Further, as shown in FIG. 1C, a contact hole (7) is formed in the step (6) of the interlayer insulating film (4) on the first electrode layer (3).
) to form.
即ち、層間絶縁膜（４）上に段差（６）の形成時に用い
たレジスト層（５）を残存させたまま新たにレジスト層
（８）を全面に付着し、露光現像して第１の電極層（３
）上のコンタクト孔（７）を形成する部分のレジスト層
（８）を除去する。続いて両レジスト層（５）（８）を
マスクとしてＲＩＥ等のドライエツチングを行ない、コ
ンタクト孔（７）を形成して第１の電極層（３）表面を
露出する。なお本工程では段差＜６）形成時のレジスト
層（５）が残存しているので、コンタクト孔（７）は必
ず第２の電極層（１０）の延在方向にしかずれるおそれ
がなく、コンタクト孔（７〉）一端をセルファラインに
より固定できる利点がある。That is, a new resist layer (8) is deposited on the entire surface of the interlayer insulating film (4) while leaving the resist layer (5) used for forming the step (6), and exposed and developed to form the first electrode. Layer (3
) on which the contact hole (7) will be formed is removed. Subsequently, using both resist layers (5) and (8) as masks, dry etching such as RIE is performed to form a contact hole (7) and expose the surface of the first electrode layer (3). In addition, in this process, since the resist layer (5) from the time of forming the step <6 remains, the contact hole (7) is always at risk of shifting only in the extending direction of the second electrode layer (10), and the contact hole (7) There is an advantage that one end of the hole (7>) can be fixed with a self-alignment line.
更に第１図りに示すように、層間絶縁膜（４）上にアル
ミニウム等の電極材料層（９）をスパッタにより全面に
付着している。Furthermore, as shown in the first diagram, an electrode material layer (9) such as aluminum is deposited over the entire surface of the interlayer insulating film (4) by sputtering.
本工程ではアルミニウム等の電極材料層（９）を層間絶
縁膜（４）上に１゜０μｍ以上に上面が平坦化されるま
で付着している。従って電極材料層（９）はコンタクト
孔（７）および層間絶縁膜（４）の段差（６）を十分に
埋め尽している。In this step, an electrode material layer (9) made of aluminum or the like is deposited on the interlayer insulating film (4) until the upper surface is flattened to 1.0 μm or more. Therefore, the electrode material layer (9) sufficiently fills the contact hole (7) and the step (6) of the interlayer insulating film (4).
更に第１図Ｅに示すように、電極材料層（９）を全面エ
ツチングして第２の電極層（１０）を形成している。Furthermore, as shown in FIG. 1E, the electrode material layer (9) is etched over the entire surface to form a second electrode layer (10).
本工程は本発明の特徴とするものであり、電極材料層（
９）をノーマスクでＲＩＥ等で全面ドライエツチングす
る。このエツチングは段差（６）を設けていない厚い居
間絶縁膜（４）が露出するまで続けられ、層間絶縁膜（
４）の段差（６）に完全に埋め込まれた第２の電極層（
１０）を形成する。この結果コンタクト孔（７）の位置
ずれに関係なくコンタクト孔（７）は完全に第２の電極
層（１０）で充填され、電極材料層（９）のドライエツ
チング時に第１の電極層（３）がドライエツチングされ
ることは皆無となる。This step is a feature of the present invention, and includes the electrode material layer (
9) is completely dry etched using RIE or the like without a mask. This etching is continued until the thick living room insulating film (4) without the step (6) is exposed, and the interlayer insulating film (4) is exposed.
The second electrode layer (4) is completely embedded in the step (6).
10). As a result, the contact hole (7) is completely filled with the second electrode layer (10) regardless of the positional shift of the contact hole (7), and when the electrode material layer (9) is dry-etched, the first electrode layer (3) is completely filled with the second electrode layer (10). ) will never be dry etched.
（ト）発明の効果
以上に詳述した如く、本発明に依れば、第１に眉間絶縁
膜（４）をエツチングして形成した段差（６）を用いて
第２の電極層（１０）を形成しているので、アルミニウ
ム等の電極材料層（９）に比べて層間絶縁膜（４）の方
がエツチング選択度が向上して微細加工を行なえる利点
を有する。(G) Effects of the Invention As detailed above, according to the present invention, the step (6) formed by first etching the glabella insulating film (4) is used to form the second electrode layer (10). Therefore, compared to the electrode material layer (9) made of aluminum or the like, the interlayer insulating film (4) has an advantage in that etching selectivity is improved and microfabrication can be performed.
第２に電極材料層（９）のエツチングはノーマスクで行
なえるので第２の電極層（１０）はセルファラインによ
り形成できる利点を有する。Secondly, since the electrode material layer (9) can be etched without a mask, the second electrode layer (10) has the advantage that it can be formed by self-alignment.
第３に電極材料層（９）のエツチングは」二面部分の全
面エツチングであるので、第１の電極層（３）の不所望
のエツチングは全く無くなる利点を有する。Thirdly, since the electrode material layer (9) is etched entirely on two surfaces, there is an advantage that undesired etching of the first electrode layer (3) is completely eliminated.
第４にコンタクト孔（７）の形成時に層間絶縁膜（４）
の段差（６）を利用しているので、コンタクト孔（７）
は必ず第２の電極層（１０）の延在方向のみにしかづれ
す、確実にコンタクト孔（７）は第２の電極Ｍ（１０）
で充填され、凹凸を発生しない利点を有する。Fourth, when forming the contact hole (7), the interlayer insulating film (4)
Since the step (6) is used, the contact hole (7)
be sure to move only in the extending direction of the second electrode layer (10), and ensure that the contact hole (7) is aligned with the second electrode M (10).
It has the advantage of not creating unevenness.
第５に第２の電極層（１０）は層間絶縁膜（４）の段差
（６）に埋め込まれるので上面の平坦化ができ、多層構
造デバイスの形成に有利となる。Fifth, since the second electrode layer (10) is embedded in the step (6) of the interlayer insulating film (4), the upper surface can be flattened, which is advantageous for forming a multilayer structure device.
第１図Ａ乃至第１図Ｅは本発明に依る多層配線の形成方
法を説明する断面図、第２図Ａ乃至第２図Ｃは従来の多
層配線の形成方法を説明する断面図である。
（１）は半導体基板、 （２）は酸化膜、 （３）は第
１の電極層、 （４）は眉間絶縁膜、 （５）（８）は
レジスト層、（６）は段差、り７）はコンタクト孔、り
９）は電極材料層、 （１０）は第２の電極層である。1A to 1E are cross-sectional views illustrating a method for forming a multilayer wiring according to the present invention, and FIGS. 2A to 2C are cross-sectional views illustrating a conventional method for forming a multilayer wiring. (1) is a semiconductor substrate, (2) is an oxide film, (3) is a first electrode layer, (4) is an insulating film between the eyebrows, (5) and (8) is a resist layer, (6) is a step, and 7 ) is a contact hole, 9) is an electrode material layer, and (10) is a second electrode layer.
Claims (1)
電極層を層間絶縁膜で被覆する工程、前記層間絶縁膜の
前記第１の電極層の端部付近から第２の電極層の延在方
向に段差を形成する工程、 前記層間絶縁膜の段差部分に前記第１の電極層を露出す
るようにコンタクト孔を形成する工程、前記層間絶縁膜
全面に前記第２の電極層を形成する電極材料層を付着す
る工程、 前記電極材料層を全面エッチングして前記層間絶縁膜上
面と平坦化された前記第２の電極層を形成する工程とを
有することを特徴とする多層配線の形成方法。(1) A step of forming a first electrode layer on a semiconductor substrate and covering the first electrode layer with an interlayer insulating film, a step of forming a second electrode from near an end of the first electrode layer of the interlayer insulating film. forming a step in the extending direction of the layer; forming a contact hole in the stepped portion of the interlayer insulating film to expose the first electrode layer; forming the second electrode layer on the entire surface of the interlayer insulating film; a step of etching the entire surface of the electrode material layer to form the second electrode layer that is planarized with the upper surface of the interlayer insulating film. How to form.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61302311A JPH0748492B2 (en) | 1986-12-18 | 1986-12-18 | Multilayer wiring formation method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61302311A JPH0748492B2 (en) | 1986-12-18 | 1986-12-18 | Multilayer wiring formation method |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS63155646A true JPS63155646A (en) | 1988-06-28 |
| JPH0748492B2 JPH0748492B2 (en) | 1995-05-24 |
Family
ID=17907427
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP61302311A Expired - Lifetime JPH0748492B2 (en) | 1986-12-18 | 1986-12-18 | Multilayer wiring formation method |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0748492B2 (en) |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5944844A (en) * | 1982-09-07 | 1984-03-13 | Toshiba Corp | Semiconductor device and manufacture thereof |
-
1986
- 1986-12-18 JP JP61302311A patent/JPH0748492B2/en not_active Expired - Lifetime
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5944844A (en) * | 1982-09-07 | 1984-03-13 | Toshiba Corp | Semiconductor device and manufacture thereof |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0748492B2 (en) | 1995-05-24 |
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