JPS62242342A - Manufacture of semiconductor chip carrier - Google Patents
Manufacture of semiconductor chip carrierInfo
- Publication number
- JPS62242342A JPS62242342A JP61085417A JP8541786A JPS62242342A JP S62242342 A JPS62242342 A JP S62242342A JP 61085417 A JP61085417 A JP 61085417A JP 8541786 A JP8541786 A JP 8541786A JP S62242342 A JPS62242342 A JP S62242342A
- Authority
- JP
- Japan
- Prior art keywords
- mounting
- semiconductor chip
- recessed part
- inner layer
- layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 23
- 238000004519 manufacturing process Methods 0.000 title claims description 5
- 239000000463 material Substances 0.000 claims abstract description 28
- 239000000758 substrate Substances 0.000 claims abstract description 23
- 238000000034 method Methods 0.000 claims abstract description 15
- 238000007747 plating Methods 0.000 claims abstract description 11
- 239000002390 adhesive tape Substances 0.000 claims abstract description 8
- 230000015572 biosynthetic process Effects 0.000 claims abstract description 3
- 238000005553 drilling Methods 0.000 claims description 2
- 239000007779 soft material Substances 0.000 abstract description 10
- 238000012545 processing Methods 0.000 abstract description 5
- 239000002648 laminated material Substances 0.000 abstract 1
- 238000005520 cutting process Methods 0.000 description 6
- 239000000853 adhesive Substances 0.000 description 4
- 230000001070 adhesive effect Effects 0.000 description 4
- 238000005530 etching Methods 0.000 description 4
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 2
- 239000011889 copper foil Substances 0.000 description 2
- 239000003822 epoxy resin Substances 0.000 description 2
- 238000010030 laminating Methods 0.000 description 2
- 238000003475 lamination Methods 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- 229910052751 metal Inorganic materials 0.000 description 2
- 238000000465 moulding Methods 0.000 description 2
- 229920000647 polyepoxide Polymers 0.000 description 2
- 239000000969 carrier Substances 0.000 description 1
- 239000000919 ceramic Substances 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000007772 electroless plating Methods 0.000 description 1
- 239000011888 foil Substances 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 239000005011 phenolic resin Substances 0.000 description 1
- 230000007261 regionalization Effects 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/02—Containers; Seals
- H01L23/04—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls
- H01L23/053—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls the container being a hollow construction and having an insulating or insulated base as a mounting for the semiconductor body
- H01L23/057—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls the container being a hollow construction and having an insulating or insulated base as a mounting for the semiconductor body the leads being parallel to the base
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/49105—Connecting at different heights
- H01L2224/49109—Connecting at different heights outside the semiconductor or solid-state body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15312—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a pin array, e.g. PGA
Landscapes
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Production Of Multi-Layered Print Wiring Board (AREA)
Abstract
Description
【発明の詳細な説明】
［技術分野１
本発明はピングリッドアレイ（ＰＧ＾）とかリードレス
チップキャリア（ＬＣＣ）等の半導体チップキャリアの
製造方法に関する。DETAILED DESCRIPTION OF THE INVENTION [Technical Field 1] The present invention relates to a method of manufacturing a semiconductor chip carrier such as a pin grid array (PG^) or a leadless chip carrier (LCC).
［背景技術１
従来より、プリント配線板をチップキャリアとして半導
体チップが実装されている。この場合多層プリント配線
板にあっては、第３図に示すように表面に内層回路が形
成され、実装用凹部３形成用の凹部３ａ乃至貫通孔３ｂ
が形成された複数枚の内層用絶縁基板１からなる内層材
４と実装用凹部形成用の貫通孔３Ｃを有する外層用絶縁
基板５を接着剤、接着シート又はローフロープリプレグ
などのボンディングシート層８を介在させて多層成形し
、次いで孔１３明は加工、スルーホールめつ外及び外層
エツチングなどを施して表面側に実装用凹部３が形成さ
れた多層プリント配線板７′が製造されるが、実装用凹
部３にもめっ外層が形成されてしまい、このめっ外層に
より汚染されて、半導体チップを実装するには、めっき
層を除去しなければならないという問題があった。[Background Art 1] Conventionally, semiconductor chips have been mounted using printed wiring boards as chip carriers. In this case, in the case of a multilayer printed wiring board, an inner layer circuit is formed on the surface as shown in FIG.
An inner layer material 4 consisting of a plurality of inner layer insulating substrates 1 on which are formed and an outer layer insulating substrate 5 having through holes 3C for forming recesses for mounting are bonded to a bonding sheet layer 8 such as an adhesive, an adhesive sheet, or a low flow prepreg. A multilayer printed wiring board 7' is manufactured in which a mounting recess 3 is formed on the surface side by performing multilayer molding with the holes 13 interposed therebetween, and then processing the holes 13, etching the outer layer of the through hole, and etching the outer layer. There was a problem in that the outer plating layer was also formed in the mounting recess 3 and was contaminated by the outer plating layer, so that the plating layer had to be removed in order to mount the semiconductor chip.
このため、本発明者らは、第４図に示すように表面に内
層回路が形成され、複数枚の内層用絶縁基板１をボンデ
ィングシート層８を介在させて積層して表面側に実装用
凹部３を有する内層材４を形成し、次いで外層用絶縁基
板５を内層材４の表面に積層し、この後孔明は加工、ス
ルーホールめっき、外層形成し、次いで最外層の外層用
絶縁基板５の実装用凹部３に対応する箇所５ａを切削し
て実装用凹部３を露出させて形成した多層プリント配線
板７″に半導体チップを実装する方法を開発したが、こ
の方法では実装用凹部３がめっきにより汚染されること
はないものの、外層用絶縁基板５の切削加工に際して内
層材４のワイヤーボンディング部９を傷付けてしまうこ
とがあった。Therefore, as shown in FIG. 4, the present inventors discovered that an inner layer circuit is formed on the surface, and a plurality of inner layer insulating substrates 1 are laminated with a bonding sheet layer 8 interposed therebetween, and a recess for mounting is formed on the surface side. 3, and then an insulating substrate 5 for the outer layer is laminated on the surface of the inner layer material 4. After this, the insulating substrate 5 for the outer layer is formed by processing, through-hole plating, and forming the outer layer. A method was developed for mounting a semiconductor chip on a multilayer printed wiring board 7'' formed by cutting a portion 5a corresponding to the mounting recess 3 to expose the mounting recess 3. However, in this method, the mounting recess 3 is not plated. Although the wire bonding portion 9 of the inner layer material 4 may be damaged during cutting of the outer layer insulating substrate 5, the wire bonding portion 9 of the inner layer material 4 may be damaged.
［発明の目的１
本発明は上記事情に鑑みて為されたものであり、その目
的とするところは、最外層の回路パターンの形成に際し
て実装用凹部がめっ外で汚染されることがなく、又、内
層材のワイヤーボンディング部が傷付くこともない半導
体チップキャリアの製造方法を提供することにある。[Objective of the Invention 1 The present invention has been made in view of the above-mentioned circumstances, and its object is to prevent the mounting recess from being contaminated by the outside layer during the formation of the outermost layer circuit pattern, and to Another object of the present invention is to provide a method for manufacturing a semiconductor chip carrier in which the wire bonding part of the inner layer material is not damaged.
［発明の開示１
本発明の半導体チップキャリアの製造方法は、内層回路
が形成された複数枚の内層用絶縁基板１を積層して表面
側に半導体チップ２の実装用凹部３を有する内層材４を
形成し、この実装用凹部３内のワイヤボンディング部９
を粘着テープのような軟質材６で被覆し、次いで最外層
となる外層用絶縁基板５を内層材４の表面に積層して多
層成形し、この後順次孔１３明は加工、スルーホールめ
っ外、外層形成を行なって多層プリント配線板７を形成
し、次いで最外層から外層用絶縁基材５の内層材４の実
装用凹部３に対応する部分５ａを切削して実装用凹部３
を露出させ、粘着テープ６を剥離除去し、この後実装用
凹部３に半導体チップ２を実装することを特徴とするも
のであり、この構成により上記目的を達成できたもので
ある。DISCLOSURE OF THE INVENTION 1 The method for manufacturing a semiconductor chip carrier of the present invention comprises laminating a plurality of inner layer insulating substrates 1 on which inner layer circuits are formed, and forming an inner layer material 4 having a recess 3 for mounting a semiconductor chip 2 on the surface side. A wire bonding portion 9 in this mounting recess 3 is formed.
is covered with a soft material 6 such as adhesive tape, and then an outer layer insulating substrate 5, which is the outermost layer, is laminated on the surface of the inner layer material 4 to perform multilayer molding. The outer layer is formed to form the multilayer printed wiring board 7, and then the portion 5a corresponding to the mounting recess 3 of the inner layer material 4 of the outer layer insulating base material 5 is cut from the outermost layer to form the mounting recess 3.
is exposed, the adhesive tape 6 is peeled off, and then the semiconductor chip 2 is mounted in the mounting recess 3. With this configuration, the above object can be achieved.
以下、本発明を添付の図面を参照しで説明する。The present invention will now be described with reference to the accompanying drawings.
多層プリント配線板７は周知のマスラミネート方式又は
ビンラミネート方式により製造される。この実施例は三
層プリント配線板である。内層用絶縁基板１は、銅箔な
どの金属箔を張った紙フエノール樹脂積層板、紙エポキ
シ樹脂積層板などの金属箔張り積層板に順次、孔明け、
無電解めっき、パターン形成、パターンめっき、レジス
トめっト、レジスト除去、エツチング、外形仕上げ、シ
ンボルマーク印刷といった常法の工程でその表面に内層
回路が形成される。内層回路を形成する前に、まず、二
枚の内層用絶縁基板１ａ、ｌｂにそれぞれ実装用凹部形
成用の凹部３ａ及び貫通孔３ｂを機械的切削加工により
形成する。次いで、この二枚の内層用絶縁基板４ａ、４
ｂを接着剤、接着シー（あるいはローフ０−ブリブレグ
のようなボンディングシート層８を介して加熱加圧して
積層成形して表面側に半導体チップ２の実装用凹部３を
有する内層材４を形成する。この実装用凹部３の表面側
のワイヤボンディング部９を粘着テープである軟質材６
で被着する。−力量外層となる外層用絶縁基板５は銅箔
プリプレグのようなものであり、この外層用絶縁基板５
を内層材４の表面にポンディングシート層８を介して加
熱加圧して多層成形する。この後孔１３明は加工、スル
ーホールめっきのスルーホール工程、次いで外層エツチ
ング等の外層形成工程により多層プリント配線板７を形
成する。この後最外層の表面側から機械的切削加工によ
り外層用絶縁基材５の内層材４の実装用凹部３に対応す
る部分５ａを切削して実装用凹部３を露出させる。この
場合、例えばドリルなどによる座ぐり中において外層用
絶縁基板５と軟質材６のドリルへの抵抗がかなり違うこ
とがら、抵抗差を感知することにより、ワイヤボンディ
ング部９を傷付けることなく座ぐりを行うことができる
。この後軟質材６を剥離除去する。残存した場合は薬品
で溶解除去する。この実装用凹部３には半導体チップ２
を搭載し、ワイヤボンディング部９にワイヤ１０により
ボンディングして内層回路と電気的に接続し、エポキシ
樹脂などにより樹脂封止したり、セラミック製のカバー
を被着して絶縁処理を施し、パッケージとしての実装を
完了して実用に供する。尚、この半導体チップキャリア
Ａは、第２図に示すようにスルーホール１１に端子ピン
１２を保持させることによりビングリッドアレイとして
、又スルーホール１１を接続孔として機能させることに
よりリードレスチップキャリアとして使用できるもので
ある。The multilayer printed wiring board 7 is manufactured by a well-known mass lamination method or bottle lamination method. This example is a three-layer printed wiring board. The inner layer insulating substrate 1 is made by sequentially drilling holes in a metal foil-covered laminate such as a paper phenol resin laminate or a paper epoxy resin laminate covered with a metal foil such as copper foil.
Inner layer circuits are formed on the surface through conventional processes such as electroless plating, pattern formation, pattern plating, resist plating, resist removal, etching, external finishing, and symbol mark printing. Before forming the inner layer circuit, first, a recess 3a for forming a recess for mounting and a through hole 3b are respectively formed in the two inner layer insulating substrates 1a and lb by mechanical cutting. Next, these two inner layer insulating substrates 4a, 4
The inner layer material 4 having a recess 3 for mounting the semiconductor chip 2 on the surface side is formed by heating and pressurizing and laminating b through an adhesive, an adhesive sheet (or a bonding sheet layer 8 such as a loaf 0-brib leg). .The wire bonding portion 9 on the surface side of the mounting recess 3 is covered with a soft material 6 made of adhesive tape.
It is covered with. - Competence The outer layer insulating substrate 5 serving as the outer layer is something like a copper foil prepreg, and this outer layer insulating substrate 5
is heated and pressed onto the surface of the inner layer material 4 via the bonding sheet layer 8 to form a multilayer. This rear hole 13 is formed into a multilayer printed wiring board 7 by processing, a through-hole process such as through-hole plating, and then an outer layer forming process such as outer layer etching. Thereafter, a portion 5a corresponding to the mounting recess 3 of the inner layer material 4 of the outer layer insulating base material 5 is cut off from the surface side of the outermost layer by mechanical cutting to expose the mounting recess 3. In this case, for example, during spot boring with a drill, the resistance to the drill of the outer layer insulating substrate 5 and the soft material 6 is quite different, so by sensing the resistance difference, the spot boring can be performed without damaging the wire bonding part 9. It can be carried out. After this, the soft material 6 is peeled off and removed. If any remains, dissolve and remove with chemicals. The semiconductor chip 2 is placed in this mounting recess 3.
It is equipped with a wire 10 and is electrically connected to the inner layer circuit by bonding it to the wire bonding part 9 with a wire 10, and then it is sealed with epoxy resin or the like or covered with a ceramic cover for insulation treatment, and then used as a package. Complete the implementation and put it into practical use. As shown in FIG. 2, this semiconductor chip carrier A can be used as a bin grid array by having the terminal pins 12 held in the through holes 11, and as a leadless chip carrier by having the through holes 11 function as connection holes. It can be used.
［発明の効果１
本発明にあっては、半導体チップの実装用凹部を有する
内層材を形成し、この実装用凹部内のワイヤボンディン
グ部を粘着テープのような軟質材で被覆し、次いで最外
層となる外層用絶縁基板を内層材の表面に積層して多層
成形し、この後順次孔明は加工、スルーホールめっき、
外層形成を行なって多層プリント配線板を形成するので
、最外層の回路パターンの形成に際し、実装用凹部が最
外層の外層用絶縁基板により保ｉｌ！されてめっ外に汚
染されることがなく、しかも多層プリント配線板の最外
層の表面側から外層用絶縁基材の内層材の実装用凹部に
対応する部分を切削して実装用凹部を露出させ、軟質材
を剥離除去し、この後実装用凹部に半導体チップを実装
するので、切削加エアー
に際してワイヤボンディング部を軟質材により保護して
傷付けることがなく、半導体チップと内層材の内層回路
との電気的接続を確実なものにできる。[Effect of the invention 1] In the present invention, an inner layer material having a recess for mounting a semiconductor chip is formed, a wire bonding part in the recess for mounting is covered with a soft material such as an adhesive tape, and then an outermost layer is formed. The insulating substrate for the outer layer is laminated on the surface of the inner layer material and multi-layer molded. After this, hole processing, through-hole plating, and
Since a multilayer printed wiring board is formed by forming an outer layer, when forming a circuit pattern on the outermost layer, the mounting recess is protected by the outermost outer layer insulating substrate! In addition, the mounting recess is exposed by cutting the portion of the outer layer insulating base material corresponding to the mounting recess of the inner layer material from the surface side of the outermost layer of the multilayer printed wiring board. Since the semiconductor chip is mounted in the mounting recess after the soft material is peeled off and removed, the wire bonding part is protected by the soft material during cutting air and is not damaged, and the inner layer circuit between the semiconductor chip and the inner layer material is The electrical connection can be ensured.
１１図は本発明の一実施例の工程を示す断面図、第２図
は同一ヒへの半導体チップの実装を示す断面図、第３図
は従来例を示す断面図、第４図は本発明の完成過程で開
発された方法を示す断面図であって、Ａは半導体チップ
キャリア、１は内層用絶縁基板、２は半導体チップ、３
は実装用凹部、４は内層材、５は外層用絶縁基板、６は
軟質材、７は多層プリント配線板、１３は孔である。FIG. 11 is a sectional view showing the process of an embodiment of the present invention, FIG. 2 is a sectional view showing mounting of a semiconductor chip on the same chip, FIG. 3 is a sectional view showing a conventional example, and FIG. 4 is a sectional view showing the process of an embodiment of the present invention. 1 is a cross-sectional view showing a method developed during the completion process of
4 is an inner layer material, 5 is an outer layer insulating substrate, 6 is a soft material, 7 is a multilayer printed wiring board, and 13 is a hole.
Claims (1)
積層して表面側に半導体チップの実装用凹部を有する内
層材を形成し、この実装用凹部内のワイヤボンディング
部を粘着テープのような軟質材で被覆し、次いで最外層
となる外層用絶縁基板を内層材の表面に積層して多層成
形し、この後順次孔明け加工、スルーホールめっき、外
層形成を行なって多層プリント配線板を形成し、次いで
最外層の表面側から外層用絶縁基材の内層材の実装用凹
部に対応する部分を切削して実装用凹部を露出させ、粘
着テープを剥離除去し、この後実装用凹部に半導体チッ
プを実装することを特徴とする半導体チップキャリアの
製造方法。(1) A plurality of inner layer insulating substrates on which inner layer circuits are formed are laminated to form an inner layer material having a recess for mounting a semiconductor chip on the front side, and the wire bonding part in the recess for mounting is covered with adhesive tape. Then, an insulating substrate for the outer layer, which is the outermost layer, is laminated on the surface of the inner layer material to form a multilayer. After this, hole drilling, through-hole plating, and outer layer formation are performed in order to form a multilayer printed wiring board. Then, from the surface side of the outermost layer, a portion of the outer layer insulating base material corresponding to the mounting recess of the inner layer material is cut to expose the mounting recess, the adhesive tape is peeled off, and then the mounting recess is removed. A method for manufacturing a semiconductor chip carrier, comprising mounting a semiconductor chip on a semiconductor chip carrier.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61085417A JPS62242342A (en) | 1986-04-14 | 1986-04-14 | Manufacture of semiconductor chip carrier |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61085417A JPS62242342A (en) | 1986-04-14 | 1986-04-14 | Manufacture of semiconductor chip carrier |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS62242342A true JPS62242342A (en) | 1987-10-22 |
Family
ID=13858230
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP61085417A Pending JPS62242342A (en) | 1986-04-14 | 1986-04-14 | Manufacture of semiconductor chip carrier |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS62242342A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH03117881U (en) * | 1990-03-15 | 1991-12-05 |
-
1986
- 1986-04-14 JP JP61085417A patent/JPS62242342A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH03117881U (en) * | 1990-03-15 | 1991-12-05 |
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