JPS62149218A - High breakdown strength cmos circuit - Google Patents

Abstract

PURPOSE:To attain the operation at a high voltage at the time of write or the like by providing a series connection of a P-channel MOS transistor (TR) and an N-channel MOS TR between a P-channel MOS TR and an N-channel MOS TR constituting an inverter. CONSTITUTION:A P-channel MOS TR 1 and an N-channel MOS TR 2 using a voltage VF being the division of a power voltage VP by resistors 5, 6 as a gate voltage is provided between a P-channel MOS TR 3 and an N-channel MOS TR 4 constituting the inverter. Only a voltage being the sum of the voltage VF and a threshold value of the TR 3 at VI=VP is fed to a connecting point S1 of the TRs 1, 3 and only a voltage being the subtraction of a threshold value of the TR 2 from the voltage VF is fed to a connection point S2 of the TRs 2, 4 at VI=0. Even when a voltage is applied at an output (0V-VP), since a voltage VF is fed as a gate voltage of the TRs 1, 2, the dielectric strength of the drain voltage is increased. Thus, a high voltage operation is attained at the time of the write of a CMOSEPROM.

Description

DETAILED DESCRIPTION OF THE INVENTION (Object of the Invention) An object of the present invention is to provide a circuit that operates at a high voltage during writing in a CMO8EFROM.

(Structure of the Invention) In a complementary insulated gate semiconductor (CMOS) integrated circuit, the basic gate that operates at a high power supply voltage VP is a P-type MO.
Between the S transistor and the N type MOS transistor, there is approximately 1
P-type MO with gate voltage set to /2 VP and voltage VF
A high-voltage CMOS circuit characterized by a configuration in which an S transistor 1 and an N-type MOS transistor 2 are connected in series, and a connection point between the P-type MO8 transistor 1 and the N-type MOS transistor 2 is used as an output.

(Function) The drain voltages of the basic gate P-type MOS transistor and N-type MOS transistor are clamped by the P-type MOS transistor 1 and N-type MOS transistor 2 of 1 voltage VF, and the breakdown of the drains of MOS transistors 1 and 2 The voltage is high because the voltage of VF is applied to these gates.

(Effect of the invention) Conventional CMO8EFROM write circuit has a high 12~
A 25V program voltage power supply is required, and high voltage transistors are used as transistors operated by this program power supply. This has resulted in an increase in the number of masks used. The present invention provides a circuit that operates at high voltage without using the above-mentioned high voltage transistors.

(Example) An example of the present invention is shown in FIG. This is applied to an inverter circuit, which is a basic gate. The gate voltage is P, which is the voltage VF obtained by dividing the power supply voltage VP by resistors 5 and 6.
A type MOS transistor 1 and an N type MOS transistor 2 are arranged in series between a P type MOS transistor 3 and an N type MOS transistor 40 forming an inverter.

FIG. 2 shows the operating waveforms of the circuit of FIG. 1. P type MO8h
At the connection point S■ of transistors 1 and 3, vI = VP”RV
Only a voltage of F+lVTPl (PmMO8) is applied, and vI = o v (V at D) is applied to the connection point S2 between the N-type MOS transistors 2 and 4.
F-VTn (Threshold value of N type to 10S transistor)
Even if voltages from 0 to VP are applied, the withstand voltage of the drain voltage increases because the gate voltage of MOS transistors 1 and 2 is VP. FIG. 3(a) shows an embodiment in which the present invention is applied to a level shifter circuit. N-type MO connected to output b and D terminals
The gate voltage of S transistors 23 and 24 is the power supply voltage VP
At what voltage VFN is 1/2 of the power supply voltage, and at what voltage is the output voltage VFP of the P-type MOS transistors 25 and 26 in contact with the D terminal?
It does not have to be VFN. Figure 3(b) shows VFN and VFP.
P-type MOS transistor 31 and N-type MOS transistor for frost and pressure resistance
An example of occurrence caused by an S transistor 32 and a resistor 33 is shown.

(Summary of the Invention) According to the present invention, high voltage transistors are used for CMO8 products such as toss ultraviolet erasable uFROM (UV-BFROM) and electrically erasable PROM (EEPR, OM) that require high voltage during writing. Therefore, the number of masks used is reduced by this amount, and the manufacturing process is shortened.

[Brief explanation of drawings]

FIG. 1 shows an embodiment of the invention. P-type MOS transistor 1.3, N-type MOS transistor 2.4, resistance 5.6
It is. FIG. 2 shows the operating waveform of the input shown in FIG. FIG. 3(a) also shows an embodiment of the present invention. N-type MOS transistor 21.22.23.24, P-type MoS transistor 25.26.27.28, input crab,
Reverse phase type crab, output, D, constant input voltage VFP1VFN
s power supply VP. FIG. 3(b) shows a voltage dividing circuit. They are a P-type MOS transistor 31 for resistance, an N-type MOS transistor 32 for resistance, and a resistor 33. Agent Patent Attorney Susumu Uchihara Figure 2 Figure 3

Claims (1)

[Claims] In complementary insulated gate semiconductor (CMOS) integrated circuits, the basic gate that operates at a high power supply voltage V_P is P-type M
Approximately 1 between the OS transistor and the N-type MOS transistor
A P-type MOS transistor 1 and an N-type MOS transistor 2 with a gate voltage of /2V_P voltage V_F are connected in series, and the connection point between the P-type MOS transistor 1 and the N-type MOS transistor 2 is an output. High voltage CMOS circuit.