JPS621261B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a planar thyristor, and particularly to a structure useful for stabilizing the characteristics of a high voltage planar thyristor.

It can be said that most of the troubles in the actual manufacture of planar thyristors, especially high-voltage planar thyristors exceeding 400V, are caused by surface deterioration phenomena in properly designed products. Among them, DC high temperature bias test (hereinafter referred to as
In many cases, the most common problem is current leakage that occurs in the DCBT.

FIG. 1 shows the surface deterioration phenomenon that is the main problem of the present invention. The surface deterioration occurs as follows. First, forward bias DCBT
As a result, on the surface of N base 1 with a relatively low concentration,
Drift of mobile charges in the insulating film, spread of charges from the electrode to the surface of the insulating film, drift of mobile ions in the resin to the insulating film, hot electrons from the surface depletion layer to the trap level in the insulating film. The P-type inversion layer 2 is formed by various mechanisms such as injection or other mechanisms. In this state, if we consider the case where a negative potential bias V _R is applied to the cathode N layer 4 with reference to the anode P layer 3 as shown in FIG. 1 (reverse blocking state for the planar thyristor), Between the wide depletion layer 5 induced in the reverse-biased anode junction and the P-type inversion layer 2 formed by the above-mentioned DCBT, there is a local gap in the vicinity of the high concentration N ⁺ layer ring (hereinafter referred to as N ⁺ channel stopper) 6. They are in close proximity. P base layer 7
If we consider a parasitic bipolar pnp transistor with the P-type surface inversion layer 2 connected to the emitter, the N base 1 as the base, and the anode P layer 3 as the collector, as shown by the arrow in the figure, its effective base is The width is reduced due to the inversion layer 2.
In other words, the current gain of the parasitic pnp transistor is locally increased. Due to the local surface destruction caused by this, the reverse blocking ability of the planar thyristor is significantly reduced even though stress is applied only to the forward side in DCBT. As is easily intuitive, the degree of the drop is directly related to the current gain of the parasitic bipolar PNP transistor, and as is well known, it is mainly due to
It is determined based on the balance between the effective base width and the diffusion length of minority carriers within the base. That is, in order to suppress the local abnormal increase in the current gain of the parasitic bipolar PNP transistor that becomes apparent due to the formation of the above-mentioned surface inversion layer, the effective base width of the parasitic transistor is widened. That is, it is possible to take measures such as increasing the width w and depth xj of the N ⁺ channel stopper 6, or shortening the diffusion length Lp of minority carriers (holes) in a considerable portion within the N base 1.

FIG. 2 is a sectional view showing the structure of an embodiment according to the present invention. The details of the structure will be explained below based on FIG. 2. The basic structure of the thyristor is an anode P layer, an N base layer, a P base layer, and a cathode N layer.
As shown in FIG. 2, is a P-type diffusion region having a penetration region penetrating the main surface and back surface of the semiconductor substrate. The N base layer 1 is a relatively low concentration N type region in which impurities remain without being diffused in the semiconductor substrate. The P base layer 7 has an anode penetrating P
This is a P-type diffusion layer provided in the N base layer 1 surrounded by the shaped region so as not to come into contact with the anode P layer 3. The cathode N layer 4 is in the P base layer 7.
This is a relatively high concentration N-type diffusion region provided so as not to contact the base layer 1. Further, the N ⁺ stopper layer 6 shown in FIG. 2 is provided near the center of the surface of the N base 1 (often formed by diffusing impurities from the main surface at the same time as the cathode N layer). This is a relatively high concentration N type diffusion region. These have substantially the same structure as a conventional planar type or high voltage withstand planar type thyristor. In Figure 2,
The region designated layer 8 is a recombination region provided in accordance with one embodiment of the invention. The purpose of providing this recombination region 8 is, as explained in detail based on FIG. , the current gain is reduced by the recombination effect of minority carriers within the base, and the blocking ability and stability of the planar thyristor are ensured. The recombination region 8 is suitably formed in the N ⁺ stopper layer 6 portion and its vicinity, but more specifically, it is most suitable for the purpose of installation to be formed in the lower N base of the stopper layer 6. It is more effective if it is formed in a large area and deep. However, care must be taken to avoid contact with the depletion layer generated in the blocking state in both the forward and reverse blocking junctions. If they come into contact, as taught by semiconductor physics, a recombination region under a strong electric field, such as a depletion layer, will turn into a carrier generation region, increasing leakage current in the blocking state.

Finally, as for the method of forming the recombination region, any method may be used as long as it meets the above-mentioned purpose, but specifically, ion implantation of impurities called lifetime killers such as gold atoms or platinum atoms is recommended. Practical methods include local doping by a method or local crystal defect formation by irradiation with a high-energy beam such as an electron beam. The thyristor according to the present invention is not limited to that shown in FIG. 2, and even if each layer is a region of the opposite conductivity type to that shown in FIG. 2, the same effect can be obtained.

[Brief explanation of the drawing]

FIG. 1 is a cross-sectional view of a thyristor for explaining the surface deterioration phenomenon that is the main problem of the present invention, and FIG. 2 is a cross-sectional view of a thyristor showing the structure of an embodiment according to the present invention. In the figure, 1...N base layer, 2...P
shaped surface inversion layer, 3... anode P layer, 4... cathode N layer, 5... anode junction depletion layer, 6...
N ⁺ stopper, 7...P base, 8...recombination region.

Claims (1)

[Claims] 1 P-type anode region with penetration region, N
N-type high concentration impurity comprising four layers of a type base region, a P-type base region, and an N-type cathode region, extending from the side of the N-type base region and surrounding the P-type base region. What is claimed is: 1. A planar thyristor having a recombination region immediately below or in the vicinity of the N-type high concentration impurity region.