JPS6180875A - Semiconductor device - Google Patents

Abstract

PURPOSE:To realize a semiconductor photodetector excellent in both dark current and high-speed response characteristics by a method wherein the formation is prevented of a p-n junction approximating a single-side junction outside the region on top of a mesa and the circumference of a p-n junction approximating such a single-side junction is covered by a p-n junction approximating a slant-type junction. CONSTITUTION:An n-InGaAsP layer (first semiconductor layer) 14 is formed, which is followed by the formation of an n-InP layer (second semiconductor layer) 15. Most of the n-InP layer 15 is removed, whereby a mesa is selectively retained. On top of the mesa, an n<-> - InP layer (third semiconductor layer) 16 is formed. An SiO2 film is formed and then the region along the circumfer ence of the n-InP layer 15 is concentrically removed. After the removal of the photoresist.SiO2 on the wafer, heat treatment is accomplished for the forma tion of a p-InP region 17. This results in the formation of a p-n junction 18 approximating a slant-type junction. Next, an insulating film 21 is formed in the same way and the p-InP region 17 is removed selectively of its internal circumference for the formation of a p<+> - InP region 19. The p<+> - n junction 20 thus formed approximates a single-side junction.

Description

DETAILED DESCRIPTION OF THE INVENTION (Industrial Application Field) The present invention relates to a semiconductor device used in reverse bias operation, and particularly to an avalanche photodiode that is high speed, high sensitivity, low noise, and highly reliable.

(Prior art and its problems) Among semiconductor photodetectors, photodiodes (hereinafter referred to as PD) or avalanche photodiodes (hereinafter referred to as A
PI) and Ibu) are important as photodetectors in optical communication systems, etc.9, and their development is progressing along with semiconductor lasers as light sources. The oscillation wavelength of a semiconductor laser is in the range of 0.8 μm to 1.5 μm, for example, G
aAs-GaA7As system, Arike I n k'-I
The mainstream is the n GaA S P type semiconductor t-hoop. Currently, PDs or APDs using Si single crystals are widely used as photodetectors for the main detection wavelength of 0.8 μm to 0.87 μm for GaAs-GaAJAs lasers, and are supported by 8i IC and LSI technology. By making full use of the technology developed by K, it has shown characteristics that include reliability.

However, with Si, it is impossible to detect light with a wavelength of 914 m or more due to the absorption coefficient of the material, and it cannot be used in the 1.1 μm to 1.6 μtnet length range where the transmission loss of the original fiber is low. Ge-APD is also available for wavelengths of 1.1 μm or more, but it has large current and excessive noise, and it is difficult to detect light with wavelengths of 1.55 μm or more due to the material. I- in this wavelength range
APDs and PDs made of group V compound semiconductor materials and the like are required.

InGaAs is currently being researched and developed as a source detector for the 1.1 and 1.6 μm wavelength range.
, InGaAsP, GaA! 18b, (JaA/AsS
b.

There are reports of a-V group compound semiconductor crystals such as Garb et al., for example, n-type I n (J
Examples include a simple Brenna type device in which a p-type impurity such as lead or cadmium is selectively diffused after epitaxial growth of an aAs layer, or a mesa-type device in which a mesa-etch is performed after full-surface diffusion. In addition, recently, pn junctions have been formed in InP, I n0aA s or InGaAsP.
For example, by forming the avalanche region in the InP layer with the original absorption layer, low dark current and high multiplication can be achieved.
-39169. Reported by Tokusa Sho 54-124975 K. However, it has drawbacks such as a narrow design tolerance and poor yield, and is not satisfactory as a main plug tester for optical communication systems. This improved version can be used, for example, as shown in Figure 2.
-X, Volt, 20. NM, pp158-1
59 (1984)), the n-InGaA3111313 as the original absorption layer on the n''-rnp substrate 11 and the n-TnP layer 15'! A low InP layer 1 is formed to cover the n-InP substrate.
6 was epitaxially grown again, and using this quafer, n-InPM was grown using f3e ion implantation technology.
Inside the p-n junction, which is close to the inclined junction, 18 k +
p+ is formed on the convex plateau region in this inner region.
Attempts have been made to form an n-junction 20 to prevent edge breakdown and improve characteristics. When a high electric field is created in this InGaAs region, a tunnel current is generated.
It has the disadvantage that it is not easy to satisfy both low dark current and high-speed response at the same time.

(Objective of the Invention) An object of the present invention is to eliminate the above-mentioned drawbacks and provide a semiconductor photodetector that satisfies dark current characteristics and high-speed response at the same time.

(Structure of the Invention) According to the present invention, the first conductivity type is formed on the first semiconductor layer exhibiting at least the first conductivity type, and the first conductivity type is the same as the fourth conductivity type and has a band gap larger than the forbidden band width of the first semiconductor layer. The second semiconductor layer has a second semiconductor layer having a convex region with a forbidden band width, and the second semiconductor layer is of the same conductivity type as the first semiconductor layer so as to include the convex region of the second semiconductor layer. A layered structure including a third semiconductor layer having a forbidden band lI@ that is equal to or larger than the forbidden band width of
In the semiconductor device in which the entire p-n junction is formed by selectively forming a region of a conductivity type opposite to the first conductivity type in the second or third semiconductor layer in which the convex region is formed, This semiconductor device is characterized in that a pn junction is formed near the inclined junction button at the periphery of the plateau in the convex region.

(Operation/Principle of the Invention) The present invention has the above-mentioned configuration, that is, it prevents the formation of a p-n junction close to a one-sided junction outside the flat area on the convex plateau, and also prevents the formation of a p-n junction close to a one-sided junction. By blocking the junction periphery with a p-n junction similar to a tilted junction, the dark current characteristics under reverse bias application were improved, and high-speed photoresponse was made possible with low dark current.

(Example) Hereinafter, an example of the present invention will be described in detail with reference to the drawings.

FIG. 1 is a schematic cross-sectional view showing an embodiment of the semiconductor device of the present invention. In this example, all materials are InP-1n (laAs), and first, n
A +-XnP buffer layer 12 with a thickness of several μm is formed on the f-type InP substrate 11 by epitaxial growth (e.g., vapor phase growth) with a thickness of 3 μm and an impurity concentration of 5xl.
Qcm n-type I nGaAs layer (first semiconductor layer) 1
form 3. Next, the film thickness is 1000A, and the impurity concentration is 1xl.
Q"CnL" n-type 1nQaAsP layer (first semiconductor layer)
14, and then a film thickness of 2 μm and an impurity concentration of 1.
A 2×1010l6” n-type InP layer (second semiconductor rfl) 15 is formed.The wafer thus obtained is subjected to a photoresist/alignment process, etc.
r4: Most of the n-1nI' layer 15 is selectively removed using a H3PO42 solution, leaving a plateau-like region.

Here, etching is performed at one degree of decentralization, and the n-
A Jnp layer 15 remains on the periphery of the convex plateau.

Next, washing with an organic solvent and H*8043:Hzol
: 01 by a solution at about 25℃ with a mixing ratio of Hz021
After etching the convex n-InP layer 1
5. Layer 5. Clean and epitaxially grow again. Approximately 2 μm on the white area, impurity source 1×101 S Cw
n--1nPQ of L' (third semiconductor/'ii) 1
Form 6k. SiO
After forming the film, the Si02 film in the region located on the periphery of the n-I n P layer 150 forming the convex plateau is removed concentrically by a photoresist/alignment process 84, and then the ion implantation technique is applied. As a result, B is added to the SiOx removal area.
Atoms of e are implanted at a rate of approximately 5 x IQ"/atl. Next, after removing the 7 photoresist SiO*=i from the wafer, heat treatment is performed at approximately 700°C under phosphorous pressure to form p -I n
A P region 17 is formed. The p-n* junction 18 obtained at this time is close to a tilt-to-head type junction.

Next, a 5 iOz or SiNx insulating film is formed as described above, and the inner peripheral region of the p-InP region 17 is selectively removed.

Next, the above-mentioned wafer was placed in a closed tube that had been evacuated using Cd5Pz as a diffusion source, and heat treatment was applied at about 570°C to selectively diffuse 5Cd into p''-InP region 19.
In this case, a depth of about 1.8 μm is obtained by heat treatment for about 40 minutes, and one piece of potash is formed.
A p-n junction 20 near the side junction is formed. Next, the SiNx or 5iOt film 2 is completely formed by the same method as described above, the electrode extraction window 22 is formed by photoresist/alignment process, etc., and the p-type electrode 23 is formed as shown in FIG. Finally, by forming an n-type electrode 24 on the n''-InP substrate 11, the semiconductor device of the present invention can be completed.

(Effects of the Invention) The device obtained from the above embodiment of the present invention has a breakdown voltage of 100V, a low dark TL of 1011A8 degrees, and a response to light incidence of 20Hz/S with a 3dB deterioration value.
The above shows an extremely high-speed custom order.

FIG. 3 shows the results of an example hfD showing the effects of the present invention.

In other words, in the opposite direction of Figure 3 ゛Fl! The current-voltage characteristics are different from the characteristics (indicated by the dotted line) obtained by the p''-1 film formed on the plateau n-1nPls explained using Figure 1 above. These are the characteristics obtained from an experimental p''-n junction located outside the InP15 region.

From this figure, p+ formed on one plateau n-1nP15
p''-n formed outside the plateau-like n-InP15 region near the breakdown voltage of the n-junction, that is, around 100V.
It can be seen that the dark current obtained by joining is large on the order of .mu.A. This can be understood as follows. That is, the n-In0aAs13 and n-InGa, 5p by applying a reverse bias obtained by the p◆-n junction formed outside the plateau-like n-InP15 region.
14 heterointerface and n-InC+aAs14 and n-1
The internal electric field at the hetero interface of nP15 is plateau-like n - I
It is larger than the heteroelectric field of the similar region obtained by the Ni-Ni bond formed on the nP15 region, and
It is understood that a large dark current was generated due to the generation of tunnel current within 14jg. Compared to this, fL
In the p-n junction 18, which is close to the n/J+M junction, the p region is also depleted with nitrogen, and the rise in the internal electric field at the hetero interface is alleviated, and the breakdown voltage is increased. , it is understood that it serves as a guard ring.

Although the effects of the present invention have been explained above based on one embodiment, it is inevitable that the effects of the present invention can be obtained with this configuration even if the plane orientation of the crystals, the combination of crystals, etc. are different, and it is within the scope of the present invention. It's obvious what's inside.

Incidentally, in FIG. 1, which is an embodiment, the seven I n P units 15 are shown to remain around the convex portion, but there is essentially no change in the surrounding area even if it is removed.

Dimensions. Although the convex region is illustrated to be larger than the p''-InP region 19, it may be smaller than the p''-InP region 19.In short, the peripheral portion of the convex portion of the InP layer 15 is larger than the p--InP layer 17 as shown in the figure. (a region called a guard ring).In addition, the first half n1 layer and two layers (InGaAs fi13. InoaAsP layer 1
Although it was formed in step 4), it may be one layer or a multilayer of three or more layers.

11... n''-InP board,
12...n''-InP epitaxial layer,
13...n-InGaAs layer, 14°--
-= n -I noaAsP layer, 15- n -I
n P Q, L6--・-n--I nP a, 17
...p-I n P region, 18...p
-n envy, 19...pゝ-InP area, 20.
... p = -n delusion, 21 ... SiNx
Or SiO! The membrane, 22...mountain, and wire are the same as in the MX1 diagram, so the same numbers have been added.

Figure 3 shows the effect of the present invention. The solid line is the dark room R characteristic of the conventional structure, and the dotted line is the reverse direction according to the embodiment of the present invention.
An example of current characteristics is shown.

, Figure 71-1 t2 diagram 2゜

Claims (1)

[Claims] a first semiconductor layer exhibiting at least a first conductivity type;
a second semiconductor layer having the same conductivity type as the conductivity type and having a convex region with a forbidden band width larger than the forbidden band width of the first semiconductor layer, and a convex region of the second semiconductor layer; A layer structure including a third semiconductor layer having the same conductivity type as the first conductivity type and having a forbidden band width equal to or larger than the forbidden band width of the second semiconductor layer, In a semiconductor device in which a pn junction is formed by forming a region of a conductivity type opposite to the first conductivity type in a second or third semiconductor layer forming the convex region, A semiconductor device characterized in that a peripheral portion of a partial region plateau is covered with a p-n junction close to an inclined junction.