JPS6053984B2 - Frame synchronizer write protection control circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a frame synchronizer, and more particularly to a write inhibit control circuit for a frame synchronizer.

A frame synchronizer is known as a signal that matches an asynchronous television signal to a standard synchronization signal.

FIG. 1 is a diagram showing a frame synchronizer according to the present invention. In the figure, a sync signal separation circuit 50 that extracts a sync signal from an input NTSC color television video signal, and a 3.58 MH2 signal synchronized with a color burst signal are shown. Obtain burst control oscillator (BCO) 51
, a write clock pulse generation circuit 52 that receives a signal from the BCO 51 and generates a 10.74MH2 write clock pulse, and an A/D converter 53 that converts an input video signal into a digital video signal using the write clock pulse. Memory 54 for storing digital video signals
, a write address generation circuit 55 that controls storage of the digital video signal in the memory 54, and a reference subcarrier (
A read clock pulse generation circuit 56 obtains read clock pulses from the reference synchronization signal (REFSC) and a reference synchronization signal (REFSC).
FSYNC) and read clock pulses'
It is composed of a read address generation circuit 57 that controls reading from the memory 54, and a D/A converter 58 that converts the read digital signal into an analog signal.
These operations etc. are described in, for example, US Pat.
It is shown in the specification of No. 007486. At the input of this frame synchronizer, if the first video signal is switched to a second video signal that is not in synchronization with the first video signal, the second video signal will be the same as the first video signal until the next frame starts after switching. May be written depending on the sequence of signals.

In this case, at the output of the frame synchronizer,
The first and second video signals were sometimes mixed on the screen. In order to eliminate this drawback, it is provided that, after the asynchronous switching, the memory of the frame synchronizer is inhibited from being written until the beginning of the next frame.

As this write prohibition control circuit, Japanese Patent Application No. 53-602
No. 28, write protection control circuit in one-frame synchronizer, this technology adds a circuit that independently detects asynchronous switching to a conventional frame synchronizer, so the circuit configuration is very complicated. It was complicated. SUMMARY OF THE INVENTION Accordingly, an object of the present invention is to provide a write-inhibit control circuit for a frame synchronizer that can generate a write-inhibit control signal by adding only a few components to the frame synchronizer circuit, while eliminating the conventional drawbacks. That's true. According to the present invention, a signal indicating a synchronization signal is generated from a horizontal address counter and a vertical address counter in a write address generation circuit of a frame synchronizer, and these signals are compared with an input synchronization signal to generate a write prohibition control signal. A write-inhibit control circuit that creates

That is, the write address generation circuit generates an address signal based on the input television signal, and the address signal indicates where on the screen the video signal to be written is located. Therefore, by generating signals predicting the horizontal and vertical synchronization signals from the write address generation circuit and comparing these with the horizontal and vertical synchronization signals extracted from the next input television signal, the following results can be obtained. It is possible to reliably detect whether an input television signal is continuous with the previous input television signal or is switched asynchronously. Next, the present invention will be described in detail with reference to the drawings of an embodiment of the present invention.

FIG. 2 is a diagram showing an embodiment of the present invention, and the write address generation circuit 1 corresponds to the write address generation circuit 55 in FIG. 1, and shows a portion related to the present invention. This generator 1 consists of a horizontal address counter 2 and a vertical address counter 3. Horizontal address counter 2 has a burst control onator (BCO).
) is supplied with a subcarrier rate signal Sp. In addition to the address data Dh, the address counter 3 receives a self-clear pulse Hc and a self-clear pulse Hc.
A pulse Hc having a width of one subcarrier period (280r1s) whose phase is advanced by a subcarrier period is output. In order to perform asynchronous switching detection using the horizontal synchronizing signal, first, a pulse having a width of 280 r1s is generated by the extraction circuit 4 from the end of the separated horizontal synchronizing signal h1. As the extraction circuit 4, for example, an SN7474 (Texas Instruments) incorporating two D-type flip-flops may be used. Pulses from the extraction circuit 4 are supplied to a shift register 5. shift register 5
The signals extracted from the three stages of
A window pulse Hw with a width of 3 subcarrier periods
becomes. Therefore, a pulse Sp is supplied to the extraction circuit 4 and the shift register 5 as a shift pulse. The window pulse Hw is supplied to the AND gate 8 via the inverter 7. Pulse Hs from counter 2 is also supplied to AND gate 8. Here, the pulse ratio is window pulse H
If it is not within the width of w, asynchronous switching detection is performed and the detection output H8 is sent to a flip-flop (FF) via an OR gate 9.
) Set 10. That is, horizontal address counter 2
Input horizontal synchronization signal h1 at the position of the horizontal synchronization signal conceived by
If there is no asynchronous switching detection is performed. Here, if the synchronization relationship is normal, the pulse Hs is the window pulse H
Needless to say, the phase of the horizontal synchronizing signal h1 is adjusted so that it is in the center of w. Next, asynchronous switching detection using a vertical synchronization signal will be explained.

In the vertical address counter 3, the vertical address data Dv
In addition, a horizontal synchronous window pulse Vw having a width of about 6 and having a width approximately centered on the vertical clear pulse is generated and is supplied to the AND gate 11 with negative polarity. The vertical synchronizing signal V1 separated from the input signal is converted by the differential pulse generating circuit 12 into a narrow differential pulse 12, and then supplied to the AND gate 11. Here, pulse ■1. is a pulse output approximately at the center of the vertical synchronizing signal V1. When the width of the pulse 12 is not within the width of the window pulse 2W, asynchronous switching detection is performed, and a detection signal Vl is output from the AND gate 11 and passes through the OR gate 9 to set the FF 10. That is, asynchronous switching detection is performed when the input vertical synchronizing signal V1 is not present at the position of the vertical synchronizing signal predicted by the vertical address counter 3. The window pulse Vw is also a signal indicating the memory blanking period here. FFlO
is set by the asynchronous switching detection signal from the OR gate 9, and outputs a write inhibit control signal Si until reset by the next frame pulse Fp.

Here, if the frame synchronizer is a field type, a field pulse is used instead of a frame pulse. In the case where the asynchronous switching occurs in the figure, it is necessary to synchronize the counters 2 and 3 with the new input television signal.

Therefore, the horizontal address counter 2 is the output S of FFLO.
i and a pulse H whose phase is delayed by 6 subcarrier periods from the center of the window pulse Hw from the shift register 5.
It is cleared by AND output with 5. Therefore, the AND gate 13 outputs an AND output between the output Si and the pulse crosspiece. On the other hand, the vertical address counter 3 is cleared by the pulse Vl2 output at the center of the separated vertical synchronizing signal 1. The circuit shown in Fig. 7 uses the output of the address counter on the writing side of the frame synchronizer,
This is much simpler than the circuit shown in No. 0228.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a frame synchronizer according to the present invention, and FIG. 2 is a diagram showing an embodiment of the present invention. In the figure, 1... write address generation circuit,
2...Horizontal address counter, 3...Vertical address counter, 4...Extraction circuit, 5...
...Shift register, 6,9...OR gate, 7...Inverter, 8,11,13...
...And gate, 10...Flip-flop,
12... Differential pulse generation circuit.

Claims (1)

[Claims] 1 Analog to digitize input television signals
a digital converter, a memory for storing a digitized television signal, and a write address generating means for generating an address signal for writing the digitized television signal into said memory in response to a scanning sequence of an input television signal. a read address generating means for generating an address signal for reading a digitized television signal from the memory according to a reference signal; and a digital-to-analog converter for converting the signal read from the memory into an analog signal. In a circuit for generating a write inhibit signal for inhibiting writing to the memory in a frame synchronizer that uses a frame synchronizer, means for generating a first pulse having a predetermined width when an address from the write address generating means specifies a predetermined address. and means for generating a second pulse corresponding to a synchronization signal included in the input television signal, and when the phases of the first and second pulses are compared and a predetermined phase relationship is not established, the write prohibition is performed. A write inhibit control circuit for a frame synchronizer, comprising means for generating a signal.