JPS60261265A - Video signal recorder - Google Patents

Abstract

PURPOSE:To record video signals easily by designating storage positions of a memory, to which horizontal and vertical address inputs separated from each other are sent, with address counters and generating synchronizing signals by address counters. CONSTITUTION:In case of recording, a composite video signal is separated to a video signal and horizontal and vertical synchronizing signals by a signal separating circuit 2, and the video signal is led to a video signal memory 32, and a storage position of the memory 32 is designated by horizontal and vertical address counters 4 and 5. In case of reproducing, reproducing horizontal and vertical synchronizing signals are generated synchronously with counters 4 and 5 by a reproducing synchronizing signal generating circuit 8, and these synchronizing signals are added to the video signal read out from the memory 32 by a reproducing synchronizing signal adding circuit 7. An address counter control circuit 10 is provided to control counters 4 and 5 synchronously with horizontal and vertical synchronizing signals separated by the circuit 2 in case of recording and synchronously with reproducing horizontal and vertical synchronizing signals in case of reproducing.

Description

[Detailed Description of the Invention] [Technical Field of the Invention] The present invention relates to a video signal recording device, and in particular, for example, in a television receiver or a TV receiver, the present invention is a device for recording video signals using a memory. This invention relates to an improvement of a video signal recording device that records several fields.

[Prior Art] Conventionally, as a device for recording video signals as described above,
There are devices that record the composite video signal as it is or as a digital signal using a Δ/D converter. However, when recording the Marodai video signal (which includes a horizontal synchronization signal and a vertical synchronization signal as shown in the first factor) into a memory, the time corresponding to the period of the horizontal and vertical synchronization signals, or the synchronization signal An extra amount of memory is required for the range of the recording signal level corresponding to the level.In contrast, a method has been proposed in which the sync signal portion is recorded to reduce the amount of memory used. During reproduction, a new circuit is required to generate and add a synchronization signal to the reproduced video signal, which has the drawback of making the device complex and inefficient.

[Summary of the Invention] This invention was made to eliminate the drawbacks of the conventional ones as described above, and it separates the address inputs of the memory into two sets, and connects to each address input to specify the storage location of the memory. It is an object of the present invention to provide a simple and inexpensive video signal recording device by installing a designated address counter and simultaneously generating a synchronization signal by the address counter.

The above objects and other objects and features of the present invention will become more apparent from the following detailed description with reference to the drawings.

[Embodiment of the Invention] FIG. 2 is a schematic block diagram showing an embodiment of the invention. In the figure, an input terminal 1 is given a composite video signal a to be recorded. This composite video signal a is given to a synchronization signal separation circuit 2.

The synchronization signal separation circuit 2 converts the applied composite video signal a into
If a video signal does not include a synchronization signal, a horizontal synchronization signal C,
This is a circuit for separating the vertical synchronization signal d and the vertical synchronization signal d. The video signal is given to a video signal memory 3. The video signal memory 3 includes an A/D converter 31 for converting the video signal into a digital signal, a memory 32 for storing the digital video signal output of the A/D converter 31, and a memory 32 for reading data from the memory 32. and a D/A converter 33 for converting the digital video signal into an analog video signal. The address of the memory 32 is specified by a horizontal address AO and a vertical address A1 given from the horizontal address counter 4 and the vertical address counter 5. Horizontal address counter 4 generates horizontal addresses by counting clocks generated from clock generation circuit 6. Further, the vertical address counter 5 generates a vertical address by counting the overflow signal of the horizontal address counter 4.

The output of the video signal memory 3, that is, the analog video signal @Q that does not include a synchronization signal, is provided to a reproduction synchronization signal addition circuit 7. Further, the reproduction synchronization signal adding circuit 7 is supplied with a reproduction horizontal synchronization signal j and a reproduction vertical synchronization signal k from the reproduction synchronization signal generation circuit 8.

The reproduction synchronization signal addition circuit 7 is a circuit for adding a reproduction horizontal synchronization signal j and a reproduction vertical synchronization signal k to the video signal Q to generate a composite video signal.

This composite video signal is output from the output terminal 9.

On the other hand, the horizontal synchronization signal C separated by the synchronization signal separation circuit 2
and the vertical synchronization signal d is the address counter control circuit 1.
given to 0. This address counter control circuit 10 includes a switching circuit 101 and two delay circuits 102 and 10.
3. The switching circuit 101 has terminals +n, n and 0
and a changeover switch having terminals p, q, and r. A horizontal synchronizing signal C is applied to a terminal m, a reproduced horizontal synchronizing signal j is applied to a terminal n', and a terminal 0 is connected to a delay circuit 102. Also, the terminal p
A vertical synchronizing signal d is applied to the terminal q, a reproduced vertical synchronizing signal k is applied to the terminal q, and a terminal r is connected to the delay circuit 103. These two changeover switches are changed over in response to a changeover signal input from the input terminal 11. That is, terminal 0 is connected to either terminal m or n, and terminal r is connected to terminal p.

Connected to either q. The output e of the delay circuit 102 and the output f of the delay circuit 103 are given as reset pulses to the horizontal address counter 4 and the vertical address counter 5, respectively. The reproduction synchronization signal generation circuit 8
includes two delay circuits 81 and 82 and two single pulse generation circuits 83J5 and 84. Delay circuits 81 and 82 are supplied with overflow signals 1 and 1 from horizontal address counter 4 and vertical address counter 5, respectively. The outputs of delay circuits 81 and 82 are
They are applied to single pulse generation circuits 83 and 84, respectively. Single pulse generating circuits 83+15 and 84 output the above-mentioned reproduced horizontal synchronizing signal j and reproduced vertical synchronizing signal k.

Figure 3 shows the signals in each part of the circuit shown in Figure 2 (in particular,
FIG. 3 is a waveform diagram showing signals (a, b, c, e, Ω, h, j, and U). The operation of the embodiment shown in FIG. 2 will be described below with reference to FIG.

First, the operation when recording a video signal will be explained. In this case, the composite video signal a input from the input terminal 1 is input to the video signal memory 3 as a video signal from which the horizontal and vertical synchronization signals have been removed by the synchronization signal separation circuit 2. In the video signal memory 3, the input video signal is converted into a digital signal by the A/D converter 31, and is stored in the memory 32.
is input. On the other hand, the horizontal synchronization signal C and vertical synchronization signal d separated by the synchronization signal separation circuit 2 are input to the address counter control circuit 10, and during recording, the switching circuit 10
1 are terminals - and 0. Since terminals p and r are connected, the signal is guided to delay circuits 102 and 103. Then, after a certain time delay, it is input to the reset manual R of the horizontal address counter 4 and the vertical address counter 5. After being reset by the delayed horizontal synchronization signal e, the horizontal address counter 4 is reset by the clock signal generation circuit 6.
The count value is counted as the horizontal address signal A.
Output as O. In addition, the vertical address counter 5 is
After being reset by the delayed vertical synchronization signal f, the overflow signal of the horizontal address counter 4 is counted and the count value is output as the vertical address signal A1. After the horizontal address counter 4 and the vertical address counter 5 overflow, they do not output a count until they are reset.

Here, the delay times of the delay circuits 1102 and 103 are set to the time from the horizontal synchronization signal C and the vertical synchronization signal d to the start of the video signal 5, and the overflow count of the horizontal address counter 4 and the vertical address counter 5 is set. If the value is set so that overflow occurs at the end of the recording signal, the signal can be recorded in the memory 32 only during the valid period of the video signal. Therefore, the memory 32 can save capacity for storing synchronization signals.

Next, the operation during playback will be explained. In this case, the digital signal read from the memory 32 is transmitted to the D/A converter 3.
3 and output as a reproduced video signal g. Further, overflow signals 1 and 1 of the horizontal address counter 4 and vertical address counter 5 are delayed for a certain period of time by delay circuits 81 and 82, and then converted into horizontal synchronization signal C and vertical synchronization signal d by single pulse generation circuits 83 and 84. A reproduced horizontal synchronizing signal j and a reproduced vertical synchronizing signal having the same pulse length are respectively added to the reproduced video signal Q in the reproduced synchronizing signal adding circuit 7, and the reproduced composite video signal is outputted to the output terminal 9. On the other hand, the reproduced horizontal synchronizing signal j and the reproduced vertical synchronizing signal are input to the address counter control circuit 10, and during reproduction, the switching circuit 10
Since terminals n and 0 and terminals q and r are connected, respectively, 1 is guided to delay circuits 102 and 103.

Then, after a certain time delay, it is input to the reset manual R of the horizontal and vertical address counters 4 and 5. The operations of horizontal and vertical address counters 4 and 5 are the same as during recording.

Here, the delay times of the delay circuits 102 and 103 are set to the time from the horizontal synchronization signal C and the vertical synchronization signal d to the start of the video signal, as in recording, and the delay times of the delay circuits 83 and 840 are set, respectively. Set to the time from the end of the video signal to the next horizontal synchronization signal C and vertical synchronization signal d. In this way, the time from the reproduced horizontal synchronizing signal j and the reproduced vertical synchronizing signal k to the start of the reproduced video signal g becomes equal to the time from the horizontal synchronizing signal C and the vertical synchronizing signal d to the start of the video signal The time from the end of the playback video signal 9 to the next playback horizontal synchronization signal j and playback vertical synchronization signal k is equal to the time from the end of the video signal S to the next horizontal and vertical synchronization signals C and d, and the playback horizontal synchronization signal The period of the signal j and the reproduced vertical synchronization signal is equal to the period of the horizontal synchronization signal C and the vertical synchronization signal d.

Therefore, the reproduced composite video signal U becomes a signal equal to the composite video signal a.

[Effects of the Invention] As described above, according to the present invention, the address input of the video signal memory is separated into two sets, and the horizontal and vertical synchronization during playback is achieved by using an address counter that specifies the storage and successive positions in the memory. Since the signal is generated, only the video signal can be stored in the memory without using a special synchronization signal generation circuit, making the circuit configuration simple and inexpensive, and reducing the memory capacity. .

[Brief explanation of the drawing]

FIG. 1 is a waveform diagram of a composite video signal. FIG. 2 is a schematic block diagram showing one embodiment of the present invention. FIG. 3 is a waveform diagram of signals at various parts of the device shown in FIG. 2. In the figure, 1 is an input terminal, 2 is a synchronization signal separation circuit, and 3
4 is a video signal memory, 4 is a horizontal address counter, 5 is a vertical address counter, 6 is a clock generation circuit, 7 is a reproduction synchronization signal addition circuit, 8 is a reproduction synchronization signal addition circuit, and 10 is an address counter control circuit. Agent Masuo Oiwa Figure 1 / April 1999 J-No. 3 Figure e Procedural amendment (voluntary) Commissioner of the Japan Patent Office 1, Indication of the case Patent Application No. 117760/1982 2, Title video of the invention Relationship between signal recording device 3 and the person making the amendment Patent applicant address 2-3 Maruno Gakko-chome, Chiyoda-ku, Tokyo Name
(601) Mitsubishi Electric Corporation Representative - Hitoshi Katayama Part 4, Agent 5, Column for detailed explanation of the invention in the specification subject to amendment and Drawing 6, Contents of amendment (1) Specification, page 4 Correct "effect" in line 3 to "expensive." (2) Figure 2 of the drawings should be corrected as shown in the attached Figure 2. that's all

Claims (2)

[Claims] (1) Composite video signal input means for inputting a composite video signal to be recorded; signal separation means for separating the composite video signal into a video signal, a horizontal synchronization signal, and a vertical synchronization signal;
A video signal memory in which a storage location is designated by a set of address inputs and records the video signal separated by the signal separation means; and a storage location connected to the horizontal and vertical address inputs of the video signal memory respectively; Horizontal and vertical address counters that specify the location, and playback horizontal synchronization signals in synchronization with each of the horizontal and vertical address counters? and reproduction synchronization signal generating means for outputting a reproduction vertical synchronization signal, reproduction synchronization signal adding means for adding the reproduction horizontal synchronization signal and reproduction vertical synchronization signal to the video signal read from the video signal memory, and during recording, the reproduction synchronization signal in synchronization with the horizontal synchronization signal and vertical synchronization signal separated by the separation means, and in synchronization with the reproduction horizontal synchronization signal and reproduction vertical synchronization signal during reproduction,
and address counter control means for controlling the horizontal and vertical address counters. (2) The above-mentioned reproduction synchronization signal generating means outputs the reproduction horizontal synchronization signal and the reproduction vertical synchronization signal after a certain period of time after the overflow of the horizontal address counter and the vertical address counter occurs. The video signal recording device according to item 1. (3) The address counter control means receives the horizontal synchronization signal @a5 separated by the signal separation means during recording.
and a vertical synchronization signal, and during reproduction, the horizontal address counter and the vertical address counter are reset after a certain period of time by the reproduction horizontal synchronization signal and the reproduction vertical synchronization signal. The video signal recording device described above.