JPS6436049A - Semiconductor integrated circuit and manufacture thereof - Google Patents
Semiconductor integrated circuit and manufacture thereofInfo
- Publication number
- JPS6436049A JPS6436049A JP19160087A JP19160087A JPS6436049A JP S6436049 A JPS6436049 A JP S6436049A JP 19160087 A JP19160087 A JP 19160087A JP 19160087 A JP19160087 A JP 19160087A JP S6436049 A JPS6436049 A JP S6436049A
- Authority
- JP
- Japan
- Prior art keywords
- wiring
- metal
- insulating film
- pattern
- resist
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title abstract 2
- 238000004519 manufacturing process Methods 0.000 title 1
- 239000002184 metal Substances 0.000 abstract 5
- 238000010292 electrical insulation Methods 0.000 abstract 1
- 238000000034 method Methods 0.000 abstract 1
- 239000000758 substrate Substances 0.000 abstract 1
Landscapes
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
PURPOSE:To make the electrical insulation good by a method wherein two kinds of wiring parts having different wiring widths exist in an identical metal wiring layer on a semiconductor substrate and the central part of the wiring width in the wider wiring part is formed to be step-like and thick so that a cavity part is hard to produce inside an insulating film and that a tip part of the metal wiring part hardly falls. CONSTITUTION:Resist patterns 5, 5' corresponding to buried wiring patterns are formed on a metal film 3; the resist pattern 5' for ordinary single wiring use is formed as a narrow pattern on a second-thickness part of the metal film 3; the resist pattern 5 requiring an especially low resistance value covers a first-thickness part and is formed as a wide pattern extended to the second- thickness part on both sides. Then, an exposed part is removed completely by making use of said resist patterns 5, 5' as masks. By removing the resist patterns 5, 5', it is possible to obtain a metal wiring part where a narrow wiring part 6 and a thick wiring part 7 having stepped parts exist in an identical wiring layer. After that, if an insulating film is deposited, a cavity is hard to produce inside the insulating film; accordingly, the reliability is enhanced.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP19160087A JPS6436049A (en) | 1987-07-31 | 1987-07-31 | Semiconductor integrated circuit and manufacture thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP19160087A JPS6436049A (en) | 1987-07-31 | 1987-07-31 | Semiconductor integrated circuit and manufacture thereof |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6436049A true JPS6436049A (en) | 1989-02-07 |
Family
ID=16277335
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP19160087A Pending JPS6436049A (en) | 1987-07-31 | 1987-07-31 | Semiconductor integrated circuit and manufacture thereof |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6436049A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5512514A (en) * | 1994-11-08 | 1996-04-30 | Spider Systems, Inc. | Self-aligned via and contact interconnect manufacturing method |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS57101668A (en) * | 1980-12-17 | 1982-06-24 | Matsushita Electric Ind Co Ltd | Etching method |
| JPS5818941A (en) * | 1981-07-27 | 1983-02-03 | Nec Corp | Manufacture of semiconductor device |
| JPS6295857A (en) * | 1985-10-22 | 1987-05-02 | Nec Corp | Manufacture of semiconductor device |
-
1987
- 1987-07-31 JP JP19160087A patent/JPS6436049A/en active Pending
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS57101668A (en) * | 1980-12-17 | 1982-06-24 | Matsushita Electric Ind Co Ltd | Etching method |
| JPS5818941A (en) * | 1981-07-27 | 1983-02-03 | Nec Corp | Manufacture of semiconductor device |
| JPS6295857A (en) * | 1985-10-22 | 1987-05-02 | Nec Corp | Manufacture of semiconductor device |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5512514A (en) * | 1994-11-08 | 1996-04-30 | Spider Systems, Inc. | Self-aligned via and contact interconnect manufacturing method |
| WO1997039478A1 (en) * | 1994-11-08 | 1997-10-23 | Spider Systems, Inc. | Self-aligned via and contact interconnect manufacturing method |
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