JPS59200464A - Method for manufacturing bipolar semiconductor device - Google Patents

Abstract

PURPOSE:To enable fabrication of the shallowed high-speed transistors with high accuracy by performing the heat treatment after implantation of impurities in plural regions together at a time as well as by performing ion implantation of collectors. CONSTITUTION:As for the N type epitaxial growth Si semiconductor layer 2 which is the upper layer of the P type Si semiconductor substrate 1, the sides and the bottom are isolated electrically by an isolation region 3 and P-N junction of an N<+> type buried layer 4 and the substrate 1 respectively. In the semiconductor layer 2, an N-P-N transistor is formed, in which an N<+> type emitter 10, a P<+> type base 8 and an N<+> type collector 11 are arranged in this order. By the existance of the N<+> type collector 11 and the heat treatment performed for the regions 8, 10 and 11 at a time after the ion implantation, the base 8 has the high impurity concentration as high as the emitter 10 whereas the base width is made extremely small.

Description

[Detailed Description of the Invention] [Technical Field] The present invention relates to a technology for manufacturing bipolar semiconductor devices having vertical transistors, and in particular to a technology that is effective for use in high-speed devices with shallow bases and emitters. be.

[Background Art] Ion implantation is an extremely effective technique for making bases and emitters shallow, and is often used to obtain high-speed devices.

However, in the ion implantation method, accelerated impurity ions are directly implanted into the semiconductor, so heat treatment is performed after implantation to eliminate defects caused by implantation and to electrically activate the implanted region. It is necessary to

In this regard, conventionally, when forming a plurality of regions such as a base and an emitter, the base was implanted and heat treated, and then the emitter was implanted and heat treated.

However, in such conventional methods, heat treatment is performed each time each region is formed, so at the time of implantation,
The thickness of the oxide film on the surface tends to vary. Therefore, variations occur in the ion implantation performed through the oxide film, and variations in the current amplification factor h FE of the transistor and the base resistance r b5- directly below the emitter are unavoidable.

On the other hand, with the trend of shallower
When it becomes about 0.2 μnl, a problem arises in that the width of the base directly under the emitter varies due to the effect of extruding the base by the emitter. This problem is caused by the base resistance r
b) This is particularly noticeable when the base concentration is increased to reduce -.

[Object of the Invention] An object of the present invention is to provide a new manufacturing technique that can form a shallow high-speed I-range metal with high precision.

The above and other objects and novel features of the present invention will become apparent from the description of this specification and the accompanying drawings.

[Summary of the Invention] Among the inventions disclosed in this application, a brief outline of typical inventions is as follows.

That is, in the present invention, the heat treatment after implanting impurities into a plurality of regions is performed all at once, thereby shortening the process and reducing variations in ion implantation. Furthermore, by performing ion implantation into the collector, each impurity in the emitter and collector suppresses the diffusion of the base impurity, thereby preventing the above-mentioned extrusion effect.

[Example] FIG. 1 shows a cross-sectional structure of a bipolar semiconductor device including an NPN transistor, and FIG. 2 shows an impurity distribution of the transistor structure.

There is an N-type epitaxially grown silicon semiconductor layer 2 on the upper surface of a P-type silicon semiconductor substrate l, and the semiconductor Wj2 is
A buried layer 4 whose side surface is formed by an isolation region 3 and whose bottom surface is of N1 type.
and the substrate 1 are electrically isolated from each other by a PN junction. In this case, one isolation region 3 is composed of a deep groove 5 formed by reactive ion etching and an insulator 6 such as silicon dioxide buried in the groove 5. Such an isolation region 3 is similar to a collector contact isolation region 9 that isolates an N+ type collector contact region 7 from a P+ type base 8.

In the electrically isolated semiconductor layer 2, an NPN transistor is formed in which an N+ type emitter 10, a P+ type base 8, and an N+ type collector 11 are arranged in this order from the surface. All of these regions are shallow, with the emitter 10 being approximately 0.1-0.27 zm, the base 8 being approximately 0.3 μm, and the collector 11 being approximately 0.4-0.5 μm.
Each has a joining depth of about m.

Here, the base 8 has a high impurity concentration comparable to that of the emitter 10, and its base width is extremely small, about 0.1 to 0.2 μm. In general, it is quite difficult to obtain a base with a high impurity concentration and a small base width, but the existence of the N+ type collector 11 and the heat treatment after ion implantation are performed for each region 8, 1.0° 11 at the same time. By doing so, the base 8 as shown above can be obtained. The heat treatment performed at one time is, for example, about 50 minutes at 1000°C. In addition, 12 is a bagcivation film made of phosphorus 1 to glass, 13, ], 4,
], , 5 are emitter 10, base 8 and collector 1
This is a metal electrode such as aluminum for 1.

[Effects] According to the present invention, since the heat treatment performed after ion implantation is performed simultaneously on a plurality of regions 8, 10. Since ion implantation is performed and each impurity in the emitter 1.0 and collector 11 suppresses the diffusion of impurities in the base 8, the influence of the above-mentioned extrusion effect can be eliminated. Therefore, according to the invention, low r 1. High speed with i-.

In addition, a transistor with good high frequency characteristics can be obtained.

The invention made by this inventor has been specifically explained above based on Examples, but it goes without saying that this invention is not limited to the Examples and can be modified in various ways without departing from the gist thereof. Nor. For example, emitter 1
Regarding the ion implantation for forming each region of 0, base 8, and collector 11, the order of implantation can be changed. Further, the isolation region 3 can be formed of a silicon oxide film formed by selective oxidation, but a trench-buried structure that does not require heat treatment is more advantageous.

In addition, if the above-mentioned extrusion effect is not a problem, the idea of performing heat treatment after ion implantation in this invention at once can be applied to the formation of only the emitter and base [Field of Application] Although the present invention can be widely used as a method for manufacturing bipolar semiconductor devices having vertical transistors, it is particularly effective for devices having shallow high-speed 1-range metals.

[Brief explanation of drawings]

FIG. 1 is a sectional view showing an embodiment of a bipolar semiconductor device obtained by applying the present invention. FIG. 2 is a diagram showing the impurity distribution of the transistor structure. DESCRIPTION OF SYMBOLS 1... Semiconductor substrate, 2... Semiconductor layer, 3... Isolation region, 4... Buried layer, 5... Groove, 6... Insulator,
7... Collector contact area, 8... Base, 9
... Collector contact isolation region, 10 ... Emitter, 11 ... Collector, 12 ... Passivation film, 13, 14.15 ... Metal electrode. Agent Patent Attorney Akio Takahashi

Claims (1)

[Claims] 1. A bipolar semiconductor device characterized in that a bipolar semiconductor device having transistors arranged in the order of emitter, base, and collector from the surface of the semiconductor layer is formed through the following steps. A method for manufacturing a semiconductor device. (A) A step of doping impurities into the semiconductor layer by ion implantation to form each of the emitter, base, and collector regions. (B) After the step (A), the impurities in the doped emitter, base, and collector regions are simultaneously heat-treated. 2. The semiconductor layer is an epitaxial layer grown on one surface of a semiconductor substrate of the first conductivity type, and the epitaxial layer has a separation region made of an insulator on the side surface and a PN junction between the buried layer and the substrate on the bottom surface. 2. A method for manufacturing a bipolar semiconductor device according to claim 1, wherein the bipolar semiconductor device is electrically isolated from each other by. 3. The method for manufacturing a bipolar semiconductor device according to claim 1 or 2, wherein the width of the base directly below the emitter is such a small value that it is affected by extrusion of the base by the emitter. .