JPS59175214A - Generating circuit of two-phase synchronizing signal - Google Patents

Abstract

PURPOSE:To realize small power consumption, high-speed operation, and a circuit suitable for compact IC formation and to set the period between active periods of a two-phase synchronizing signals to minimum safety length by controlling two series circuits of P channel and N channel MOSFETs by a four- phase signal generating circuit. CONSTITUTION:An input basic clock signal phi is inputted to the four-phase signal generating circuit 61 to generate the 1st or 4th four-phase control pulse, which is applied to gates of P channel MOSFETs 53 and 57, and N channel MOSFETs 55 and 58 to obtain two phase clock signals phi1 and phi2 at output terminals 52 and 56. Those MOSFETs 53 and 55, and 57 and 58 are not turned on at the same time, so the power consumption is reduced to realize the high integration and high-speed operation; and the period between periods where the two-phase clock signals phi1 and phi2 are at a level ''1'' is set to the minimum safety length without any difficulty in circuit designing.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a complementary MO8 type integrated circuit device.
The present invention relates to a phase synchronization signal generation circuit, and particularly to a two-phase synchronization signal generation circuit that generates two-phase basic synchronization signals having the same frequency as a one-phase synchronization signal from a one-phase synchronization signal.

[Technical background of the invention and its problems]

Conventionally, the input basic clock signal φ has the same frequency as the input basic clock signal φ and is at an active level (for example, an N-channel MO8F
In case of ET, ``1# level, P channel MO8FET
As a circuit that generates two-phase clock signals whose phases are shifted in such a way that the periods of "0" level overlap in the case of /
/'i There is a circuit as shown in Figure 1.

The conventional two-phase synchronous signal generation circuit shown in FIG. 1 includes an inverter 21 that inverts the input basic clock signal φ, an even number of inverters connected in series, and delays the output signal of the inverter 1 by a predetermined time. Delay circuit 12, this delay circuit 1
2 and the output signal of the inverter 11 are respectively input in parallel to the NOR+''- gate 13 and NAN.
D f-t14. An inverter 15 inverts the output signal from the NOR'i'' gate 13 and outputs the clock signal φl for one of the two phases, and an inverter 15 inverts the output signal from the NOR'i'' gate 14 to output the clock signal φl for one of the two phases It consists of an inverter 16 that outputs the other clock signal φ2.In this circuit, as shown in the timing chart of FIG.
By using the signal delay time in the delay circuit 12,
K is set so that the "O" level period of 1 does not overlap with the "1" level period of the signal φ2.

However, in this circuit, it is necessary to set a sufficient signal delay time in the delay circuit 12 in consideration of the driving ability of the load capacitance of the signal -<'Hzφ, and the circuit design is not easy. Also, signal - Ishiichi.

If there is a difference in the load capacitance of φ, this signal φl,
There is a drawback that the period between the 0" level period and the "1" level period of φ2 (this is a period in which both are not at the active level, and this period will be referred to as the off-off period hereinafter) cannot be secured reliably. .

Figures 3 and 5 respectively show circuits of a conventional 2' phase synchronous signal generating circuit that overcomes the drawbacks of the circuit in Figure 1, namely the difficulty in circuit design and the inability to ensure off-off periods. It is a diagram. The circuit of FIG. 3 consists of two inverters 22 and 23 connected in series to the output terminals of the NOR gate 2 and the output terminal of the NOR gate 21, and two inverters 22 and 23 connected in series to the output terminal of the NOR gate 24 and the output terminal of the NOR gate 24. The two connected inverters 25 and 26 constitute a 79217121 circuit 11, and the input basic clock signal φ is input as one input signal of this free-lag frog circuit 11, and the signal φ is input as the other input signal to the inverter 28. This is the one that was set to be input via the K. Two-phase clock signals φl and φ2 are obtained as output signals of the free-lag frog circuit 27.

This circuit operates so that the signals φ2 and φ change to @1 level after mutually confirming the "0 level" of the signals φ1 and φ2. Therefore, even if there is a difference in the load capacitance of the signals φ1 and φ2, , a total of three stages of dirt delay time is automatically secured as an off-off period, including the part to the N0Rr gate 21 or 24 and the two stages of the two inverters 22, 23 or 25.26. Therefore, an off-off period can be ensured without any difficulty in circuit design.

Incidentally, FIG. 4 shows a timing chart of the circuit shown in FIG. 3.

The circuit in Figure 5 is the NOR dart 21.24 in the circuit in Figure 3.
(The above-mentioned free-lag floating circuit υ is constructed by using NAND gates 29 and 30 in the D-side, respectively.
The difference is that after mutually confirming the "1" level of the two-phase output clock signals (fis and d't), the signal stone "changes to the "O" level.The operation of this circuit is as follows. This is the sequence shown in the timing chart of FIG.

As mentioned above, in the conventional circuits of FIGS. 3 and 5, the first
It is possible to eliminate the drawbacks of the diagram circuit. However, both of these circuits have the following problems.

In recent years, the problem of power consumption has arisen as LSIs have become larger in scale.In particular, CMO8 type L, which features low power consumption,
SI is attracting attention. CMO clock signal generation circuit
Considering the case where it is built into an 8LSI, almost no power is consumed in the LSI when the clock signal output operation is stopped.

However, when the clock signal is output, the CM
Even though it is an O8LSI, power is consumed. In particular, the clock signal generation circuit always operates at the highest frequency in the LSI, and the power consumption in this part is large. On the other hand, it is well known that the power consumption in the 0M08 circuit can be roughly divided into the following two types. The first is due to charging/discharging current of internal capacitance and various leakage currents, and the second is due to P channel and N channel M connected in series.
This is due to the fact that both MO8FETs are turned on when the O8FET is switched, a DC current path is created between the power supplies, and a current (through current) K flows there.

The power consumption due to each of the above-mentioned currents, apart from that due to leakage current, increases as the frequency increases.

For this reason, C is used in devices that require high-speed, high-frequency operation, such as microconverter systems.
The power consumption of MO8LSI is becoming a problem. On the other hand, as the scale of LSI increases, the load capacity of internal clock lines increases, and the drive MOS transistors that generate the internal basic p rough signals need to have large current drive capacity and large dimensions. Furthermore, in order to perform high-speed operation, it is necessary to increase the l1m value (conductance) of the drive MO8) transistor. In such a situation, 7 of the MOSFETs constituting each of the final stage inverters 23 and 26 in the circuit of FIG. 3 or FIG.
If you try to increase the 7m value to cope with the increase in the scale and speed of the LSI as described above, you will end up with the inverter 2 in the previous stage.
If the load capacity of 2.25 is increased, the input signal waveform of the inverters 23 and 26 becomes dull, and the period during which the through current flows in each of the inverters 23 and 26 becomes long. MO within
Since the 1m value of the SFET is also increased, the power consumption in each of the two inverters 23 and 26 becomes large.

Therefore, in order to prevent the input signal waveforms to the two inverters 23, 26 from becoming distorted, if the 1m value of the MOSFET in the previous stage inverter 22, 25 is also increased, the inverters 22 and 23 and 25 and 26 in each of the two stages It is not possible to ensure sufficient dart delay time for each dart. As a result, the off-off periods of the signals φ1 and φ2 or the signals ``and φ2'' become shorter, making it impossible to maintain a safe minimum off-off period.

For this purpose, conventionally, as shown in FIG. 7, in place of each inverter 22, 25 in the circuit of FIG. 5, an even number of inverters are connected in series to form a grid buffer. A sufficient delay time is obtained by providing delay circuits 31 and 32 which also serve as the two functions.

However, even this circuit cannot essentially eliminate the through current in the final stage inverters zz, xi;
It is necessary to design the values and the number of inverter stages in the delay circuits 31 and 32 in consideration of through current and delay time, which makes circuit design difficult.

In each case, the conventional circuits shown in FIGS. 1, 3, 5, and 7 have two-phase clock signals φ1 and φ2, which have the same frequency as the input basic clock signal φ. φ1 and φ! Alternatively, although it is for generating φ1 and φ2, it is also conceivable to generate a two-phase lock signal using signals obtained by sequentially frequency-dividing the input basic clock signal φ. A conventional circuit based on this system has a configuration shown in FIG. 8, for example. The multi-input basic clock signal φ is frequency-divided by the frequency dividing circuit 41 using this circuit-based shift register, counter, etc. to produce two-phase signals, and each signal is input to a Nori buffer input 42. By supplying the driving inverters 44 and 45 through the respective driving inverters 44 and 43, two-phase clock signals φ1 and φ are generated. The off-off period of the signals φl and φ generated by this circuit is as shown in the timing chart of FIG.
It is formed using the width or period of the wave.

However, even in this circuit, a through current occurs. Moreover, the off-off period of the two-phase clock signals φ1 and φ2 is determined by the input basic clock signal φ, and there is a possibility that it becomes longer than necessary. This off-off period is used to prevent data racing malfunction (data leakage is a phenomenon) caused by the clock when the CMO8 circuit to which the two-phase clock signals φl and φ2 are supplied includes, for example, a shift reno star, or This is provided to prevent malfunctions due to interference between grid charges and discharges in dynamic circuits. In view of the operating speed of the circuit that operates based on the signals .phi.

[Object of the Invention] This invention was made in consideration of the above circumstances, and its purpose is to provide a method that consumes less power, is suitable for high-speed operation and high integration, and is free from the difficulty of circuit design. Zuni 2
An object of the present invention is to provide a two-phase synchronization signal generation circuit that can set the period between active periods of phase synchronization signals to the minimum safe length.

[Summary of the invention]

According to this invention, a P-channel first MQSFET is inserted between the high potential supply terminal and the first output terminal to which one of the two-phase lock signals is output, and the first output terminal an N-channel second MQ between
A third P-channel MQSFET is inserted between the high potential supply terminal and the second output terminal to which the other of the two-phase lock signals is output, and the second output terminal A fourth N-channel MQSFET is inserted between the terminal and the low potential supply terminal, and one synchronizing signal is input to the ff-) of the first to fourth MQSFETs that are supplied to the dart of each MO8FET. A 4-phase signal generation circuit is provided to generate the first to fourth four-phase control signals to be supplied, and the 0" level period of the first control signal generated by the four-phase signal generation circuit is a second period. The two-phase homologous control signal does not overlap with the "1" level period of the control signal, and the 0" level period of the third control signal does not overlap with the 1" level period of the fourth control signal. A period signal generation circuit is provided.

[Embodiments of the invention]

An embodiment of the present invention will be described below with reference to the drawings. FIG. 10 is a circuit diagram showing the configuration of an embodiment of a two-phase synchronous signal generating circuit according to the present invention. In the figure, terminals 5 (first terminal) and 2 are supplied with a positive polarity power supply voltage vDD.
One of the phase lock signals (two-phase synchronization signals) φ! A P-channel OMQSFET 53 (first OMQSFET) is connected between the output terminal 52 (third terminal) where
) is inserted. The output terminal 52 and the ground voltage V,
An N-channel MQSFET s s (second MO8
F'ET) is inserted. A P-channel MQSFET 5-' is connected between the terminal 51 and the output terminal 56 (fourth terminal) to which the other signal φ2 of the two-phase lock signal is output.
y (third MO8F'ET) is inserted. An N-channel MQS is connected between the output terminal 56 and the terminal 54.
FET s s (40th MOsrgT) is inserted.

Furthermore, in FIG. 10, the four-phase signal generation circuit (four-phase signal generation means) 61 generates an
The four-phase first to fourth control signals (first to fourth control signals) shown in the timing chart in the figure +1'P
1, <"n 1 t 5 t d n 2, respectively, and these control/rus'I"
” n5. Horse 5rφn2 each of the above 4 MQS
It is supplied to each dart of FET 5B, 55, 57, and 58.

Of the 4-phase control signals generated by the 4-phase signal generation circuit 6, the control signal ``0#rehe/''+7)
The period tri is set so as not to overlap with the 11" level period of the control/f pulse φn1, and the period of the control pulse 5 "0" level is the "1" level period of the control pulse φn2.
``It is set so that the period of the level does not overlap with each other.

Moreover, after the control pulse φn1 changes from the "0" level to the "1" level, and after a predetermined period of delay, the control pulse is inverted from the -1" level to the 0" level, and the control signal φn2 is changed from the -1" level to the 0" level. After changing from the "0#" level to the "1" level and after a predetermined period of delay, the control and pulse ends are inverted to the "0" level and the "0" level.

In such a configuration, the control pulse +16. , is at the 10” level, MQSFET 53
is turned on, and the signal φl at the output terminal 52 is set to the ``1'' level as shown in FIG. During the period until the mother pulse φn1 changes from the O" level to the "l-level", the MOSFETs 53, 55
Both are turned off. Therefore, in this period, the signal φ
l is held at the ``1# level.Next, during the period when the control/4' pulse φゎ is at the ``1n level, the MOSF
ET 55 is turned on and the signal φ1 at output terminal 52
is now set to the "0" level. Next, the control i4 pulse φ. , changes from the "1# level" to the "0" level and until the control pulse φp1 changes from the "1# level to the "o" level K, the MOSFET changes again.
53 and 55 are both turned off. Therefore, during this period, signal φl is maintained at the "O" level.

On the other hand, during the period when the control signal d,, is at "0" L/peltona, the MOSFET 57 is turned on, and the signal φ2 at the output terminal 56 is changed to "1" as shown in FIG.
1" level. Next, after the control pulse presentation changes from the "0# level to the "1" level, the control pulse φn2
MO8FETs 57 and 58 are unenviably turned off during the period until the voltage changes from the II On level to the "1" level. Therefore, during this period, the signal φ2 is held at the “1#” level.Next, during the period when the control pulse φn2 is at the “P1” level, the MOSFETs 5, ! ? is turned on, and the signal φ2 at the output terminal 56 is now ``0#''.
set to the level. Next, the control pulse φn2 is
During the period after the 1" level changes to the 0" level and until the control/main pulse changes from the "1" level to the "0" level, both MO8FETs 57 and 58 are turned off again. Therefore, in this period, the signal φ2/d, ” 0
``It will remain at level 1.

Here, the control/4' pulse φn1 changes from the PaOs level to ''
The timing at which the control signal changes from the "1" level to the °'0" level (timing at t2) is delayed by a predetermined period with respect to the timing at which it changes to the 1# level (timing at tl in FIG. 11). Oshi, control, gurusu φn2
The timing at which the control pulse η changes from the "1" level to the PA0 level (timing at t4) is also delayed by a predetermined period with respect to the timing at which the control pulse η changes from the "0" level to the "1" level (timing at ts). .

Therefore, the two output terminals 52, 56 of this example circuit
As shown in FIG.
is output. Furthermore, MOSFETs 53 and 55 and 57 and 58 are used to output signals φ2 and φ2, respectively.
MOSFET 5 is inserted in series between terminals 5 and 54 because they are not turned on at the same time.
,? .

No through current occurs in MOSFET 55 and MOSFETs 57 and 58, and power consumption can be reduced. Moreover, MOSFET 53, 55 and MOS
Since no through current occurs in FETs 57 and 58, there is no need to consider the power consumption here.
The current drive capability of the FET can be increased, and thereby the load capacitance connected to each of the output terminals 52 and 56 can be rapidly charged and discharged. That is, this enables high integration and high speed operation. In addition, the control pulse φ. , changes to the "1" level, and then the control pulse φn changes to the "O" level (period from tr to t2).
By setting the period (period from t3 to t4) until the control pulse changes to the ``0'' level after 2 changes to the ``0'' level, the two-phase The period between the periods in which the clock signals φ1 and φ2 are at w 1 n level (active level) can be safely made to the minimum length without causing any difficulty in circuit design.

FIG. 12 is a circuit diagram showing the configuration of a two-phase synchronous signal generation circuit according to another embodiment of the present invention.

The difference between Jin's embodiment circuit and the embodiment circuit shown in FIG.
Phase control/Ladleless 〒、φ. ,.

(' p 2 + φn In place of the 4-phase signal generation circuit 61 that generates 2, a new 4-phase signal generation circuit 62 is provided.And this 4-phase signal generation circuit 6
2 has the input basic clock signal φ and the output terminal 52.5.
The two-phase clock signal φ1 output from each of the six
φ2 is input. The four-phase signal generating circuit 62 generates the four phases according to the three types of clock signals φl and φ2 inputted above.

Further, the four-phase signal generation circuit 62 in FIG. 12 includes two circuit blocks 62A as shown in FIG. 13.

It consists of 6 songs 'B'. One of the above circuit blocks 6
2, the two-phase control pulse 91φn1 is generated from the input basic clock signal φ and one clock signal φ2 output from the one output terminal 56. Further, the other circuit block 62B generates the two-phase control pulse signal ``n2'' from the input basic clock signal φ and the other clock signal φ1 outputted from the other output terminal 52.

FIG. 14 is an overall circuit diagram specifically showing the two circuits 62 and 62B shown in FIG. 13 above.

As shown in the figure, one circuit clock 62 includes three inverters 71 and 72.

73, one NOR gate each 74, NAND
It is equipped with a gate 75 and an OR dart 76. Above N
0R) i′″-Inverter 71 is installed at one input end of door 4.
An input basic clock signal φ is inputted via the input basic clock signal φ. This N
The output signal of OR gate 74 is passed through inverter 72 to N
It is input to one input terminal of AND gate 75. This NA
The output signals from the ND keys are input to the input terminal 73.
The above-mentioned N0R)lA- is inputted to the other input terminal of the door 4 through the above. The above Ingutav 1 is still in OR gate 76.
The black output signal and the black signal φ2 are input,
The output signal from this OR gate 76 is input to the other input terminal of the NAND date 75. That is, this circuit block 62 includes a substantial OR-type f-to circuit 7 consisting of a NOR gate 74 and an input gate 72.
7 (first dirt circuit), a NAND gate 75, an inverter 73, and d-.
- dart circuit ys (second dart circuit) constitutes a 7 lipfrog circuit 1J, and an OR dart 76 (third dart circuit) which inputs clock signals T and φ2 is provided at the front stage of dart circuit L1. There is.

The other circuit block 62B is the same as the one circuit block 62B.
Innoguita 72゜73, NOR installed in A
Gate 74, NAND Dart 75. OR gate 7
In i4-E82゜8B corresponding to each of 6,
NOR dart 84, NAND gate 85, OR gate
- SE and SE respectively. This circuit block 6
Similarly to the circuit block 62 in 2B, there is a substantial OR-type dart circuit L1 (first dart circuit) consisting of a NOR dart 84 and an inverter 82, and a NAN circuit block 62.
A substantially AND type f-) circuit consisting of a D dart 85 and an inverter 83, L! (second dart circuit) constitutes a 7-rip-frog circuit L, and the OR dart circuit 8 inputs clock signals φ and φ1 at the front stage of the dart circuit U.
6 (third dirt circuit) is provided.

The output signals of the inverters 72 and 73 are outputted as the control/main pulse <'p 1 + +1' n 1, and the inverters 82 and 8 in the other circuit block 62B
3. Each output signal is connected to the control 9. φn
Output as 2.

Next, the operation of the circuit configured as shown in FIG. 14 will be explained using the timing chart shown in FIG. 15. First of all, control/gurus T attack, φ. , are both at the "o" level, and the control/e# pins p21φn2 are both at the "1" level. At this time, the MOSFET 53 is turned on, the MOSFET 55 is turned off, and the signal φl at the output terminal 52 is set to the "1" level.
FET 57 is off, MO8FET58 is off,
The signal φ2 at the output terminal 56 is set to the 'O' level.
The control/cruise 6 at the °'l'' level is input to the D dart 85, and '1#' is input via the OR dart 86.
The signal φ! is input, so its output signal is fixed at the "0# level. Moreover, the control signal φ1□, which is at the "1# level, is input to the NOR dart 84 in the circuit block 62B. Therefore, regardless of the signal φ, the output signal of this NOR gate 84 is also '
It is fixed at the “O” level. In other words, the signal φl is “
During the 1'' level period, the operation of the circuit block 62B is fixed regardless of the level change of the signal φ, and the control pulse 5;
Each of φn2 is fixed at the "1# level. Therefore, the signal φ2 remains at the "0# level.

Next, when φ1=“1” level and φ2=“0” level, the input basic clock signal φ is “1# level color Q'
Change in level. As a result, the output signal of the inverter 71 within the circuit block 62A changes from "O" level to "
Changes to 1” level.Furthermore, NOR dirt 74
The output signal changes from “1” level to “0” level,
After this, the output signal of the inverter 72 is also inverted, and the control signal changes from the "0# level" to the "1# level." Then, MOSFET 53, which has been turned on until now, is turned off. Since the output signal of the OR gate 76 has already been set to the 1'' level by the clock signal φ by the time the control signal 7- changes to the ``1# level, the NAND gate 76 changes after the control signal 7- changes to the 1'' level. The output signal of 75 is ゛1
The output signal of the inverter 73 is also inverted and the control pulse φn1 becomes 610.
1 Ruberkara” Changes to 1” level. Then MOSFET 65, which had been off until now, is turned on and the signal φ
l is set to 0'' level. Here, the first circuit block 62 in response to the level change of the input basic clock signal φ
The clock signal φ1 is changed from the ``1'' level to the ``0# level'' by the control/routine from k and φn1, but the control/routine is changed from the ``0# level to °'1''.
When the level changes and MOSFET 53 turns on,
The control pulse φn1 is kept at “0” level.
SFET s s is off. The MOSFET 55 is turned on only when the change in control pulse distribution is transmitted through the dart circuit 7B consisting of the NAND gate 75 and the inverter 23. To this end,
MOSFET5,? , 55 go from the on/off state to the off/on state, both pass through the off state for a period corresponding to the signal delay time by the dart circuit 2, and the MOSFET 53.

No through current occurs at 55.

Next, when the signal φ1 reaches the 10" level, the output signal of the O1'l'-tote 86 in the second circuit block 62B becomes "1".
The output signal of NAND ff - ) 85 changes from the ``0# level to @1# level, and then the output signal of NAND ff - The output signal is inverted and the control/gurus φn
2 changes from the "1" level to the "0# level. Then, the MOSFET 5B, which has been turned on until now, is turned off. After the control 2 arm φn2 changes to the "0" level, the output signal of the NOR gate 84 from '0' level to '''
After that, the output signal of the inverter 82 is also inverted, and the control/4' pulse φ,2 changes from the 1" level to the "'0# level. As a result, MOSFET 57, which had been off until now, is turned on, and the signal φ
2 is set to the 'l' level. In this way, the clock signal φ2 output from the second circuit block 62B is equal to the clock signal φ2 output from the first circuit block 62A.
!・After changing from "1# level" to "0# level"
When the clock signal φ2 changes from the "0#" level to the "1" level, that is, MO8FF, T57, 5
When B moves from the off/on state to the on/off state, the control/gusus φn
Both MOSFETs 57 and 58 go through the OFF state for a period in which the change in 2 corresponds to the signal delay time by the Y-to circuit L1. Therefore, even when the level of the clock signal φ2 changes, no through current occurs in the MOSFETs 57 and 58.

During this period, when the clock signal φ2 reaches the "1#" level, the operation of the first circuit block 62A is fixed regardless of the level change of the signal φ, and the control signal (II, φp1 nl is Each is fixed at the ``1'' level. Therefore, the signal φl is at the ``0'' level.

Next φ! input basic clock signal φ changes from 0” level to “1” level when φ2=11” level. As a result, in the second circuit block 62B, the output signal of the NOR controller 84 changes from the "1" level to the "0" level, and then the output signal of the input controller 82 is inverted and controlled. The pulse also goes from 5 to 6 from the ``0'' level.
Change to 1# level. Then, MO8FF and T57 are first turned off. By the time the control stone 5 changes to the "1" level, the output signal of the 0Rr-to 86 has already been set to the "1" level by the clock signal φ.
After the control signal generator 5 changes, the output signal of the NAND gate 85 changes to the level ``1#l# level 0'', and after this, the output signal of the inverter 83 is also inverted and the control signal φn2 changes to ``1#1# level 0'' level. Changes from 0'' level to 1# level.

Then, the MOSFET ss, which had been turned off until then, is turned on, and the signal φ2 is inverted from the “1” level to the 0 level. The control pulse stone from 62B, φn2, and the clock signal φ2 are II 1
It is MOSFET 57 which is changed from #l level to "0" level.

When the MOSFET 58 changes from the on/off state to the off/on state, the MOSFET 57 goes through the off state for a period corresponding to the signal delay time by the dart circuit 8B. , 58, no through current occurs.

Next, when the signal φ2 reaches the "0" level, the output signal power of the OR dart 76 in the first circuit block 62A is "1".
The level is reversed to "0" level. Then, following this, the output signal of the NAND gate 75 changes from the "0" level to "
1″ level, and following this, inverter 7
The output signal of 3 is inverted and controlled (Rus φ., is ″′1″
level changes to ``Ω'' level. Then, MOSFET 55, which has been turned on until now, is turned off. Control pulse φ. , changes to 0” level, then NOR dirt 7
The output signal of Inno-Tough 2 changes from the "0# level" to the "1" level, and then the output signal of the Inno-Tough 2 is also inverted, and the control pulse Shiliu changes from the "1# level" to the "0" level. Due to this, the MOSFE, which had been turned off until now,
T53 is turned on and signal φ1 is set to the "1" level. In this way, the clock signal φ1 output from the first circuit block 62A is transmitted to the second circuit block 62B.
The clock signal φ2 output from
After changing to '0# level, it is changed from '0# level to "1# level. Then, this clock signal φ!"
When changing from 0 level to 1# level, that is, CHM
When the O8FETs 53 and 55 move from the off/on state to the on/off state, the control signal φ is controlled in the same manner as described above. , for a period corresponding to the signal delay time due to the dart circuit L].
, 55 both transition through the off state. therefore,
Even when the clock signal φl changes from the '0'' level to the 111# level, no through current occurs in the MOSFETs 53 and 55.

During this period, when the clock signal φl reaches the "1" level, the second circuit block 62B is activated for the same reason as above.
The operation of is fixed regardless of the level change of the signal φ, and the control/2 pulses d and 2 + dn2 are each fixed at the '1# level. Therefore, the signal φ2 is at the "0" level up to t'.

From then on, the same operations as above are repeated.

As described above, according to this embodiment circuit, it is possible to obtain two-phase clock signals φl and φ2 whose P1# level periods do not overlap with each other, as shown in FIG. 15. Moreover, the signal φ! , φ2, respectively.
Since 53 and 55 and 57 and 58 are not turned on at the same time, MOSFETs 53 and 55 are inserted in series between terminals 5 and 54.
57.

58, no through current is generated, and power consumption can be reduced. Also, clock signals φ1, φ
The period between the periods in which 2 are each "1 level" is a period that is similar to the sum of the signal delay times in the dart circuit 77 and Iotto J- or the sum of the signal delay times in the dart circuits U and Ll. It will be set automatically.For this reason,
The above clock signals φ1, φ
The above period can be set to a safe length and a minimum value in which malfunctions due to interference between racing, precharge, and discharge do not occur in a circuit using No. 2. Further, between the control pulse TF and φn1, and between the tag 7 and φn2, dart circuits 7 and 7B are connected.
, 87.88 creates a period in which both MOSFETs s ,
No through current is generated in each of s s and MO8F'ET 57 and 58, and the current drive capability of each MOSFET can be increased while the power consumption is minimized. This allows the load capacitors connected to each of the output terminals 52 and 56 to be rapidly charged and discharged, thereby making it possible to achieve high integration and high-speed operation without increasing power consumption.

It can be seen that the timing chart in FIG. 15 showing the operation of the 14th circuit is the same as the timing chart shown in FIG. 11 above.

Also, when comparing the tyranno size when the circuit in Figure 14 and the conventional circuit, for example the circuit in Figure 7, are integrated,
At first glance, the circuit of FIG. 14 appears to have a larger number of elements. However, the turn area can be made the same considering the wiring, and since the circuit is symmetrical, the tyranno size can be made almost the same as the conventional one.

Figure 16 and Figures 1 and 7 are respectively 4 in Figure 13.
This is a circuit diagram showing another example of the phase signal generation circuit 62, and such circuits can also be used.

The four-phase signal generating circuit 62 shown in FIG. 16 is composed of two circuit blocks 62C and 62D.

One circuit block 62C is a substantial logical OR type r-
gate circuit 97, NAND gate 95 and inverter 9
71 horn frog circuit port consisting of a substantial AND-type dirt circuit consisting of 3, the dirt circuit L1
An ANDf-) 96 is provided at the front stage of the circuit and receives the clock signal φ and the shoulder as inputs. The other circuit block 62D includes a substantial logical gate type dart circuit 107 consisting of a NOR card 5104 and an inverter 102, and a NAND dart circuit 105 and an inverter 102.
3, an in-theta circuit 101 that inverts the input basic clock signal φ, and an in-theta circuit 101 that is provided at the front stage of the above-mentioned gate circuit 107. Self Inno 9-Yu 10
It has an output signal from 1 and an AND dart 106 whose input is <6 and -. That is, this 1st degree C
In the circuit blocks 62C and 62D, these pl n are substituted for the control i4 pulses T-2φ and -φ-2φ
Pulse φpi ' rnl 'φp2 with opposite phase to l p2 n2 , 5
is output, so the lifespan signal φ2 is different from that in the case of Fig. 14.
, φ1, respectively, are obtained at the output terminals 52, 56, and these two signals are input as control signals to the first and second circuit blocks 62C, 62D.

The four-phase signal generation circuit 62 shown in FIG. 17 is also composed of two circuit blocks 62B and 62F.

One circuit block 62E includes a substantial OR type dart circuit 117 consisting of a NOR gate 114 and an inverter 112, and a substantial AND type dart circuit 11 consisting of a NAND gate 115 and an inverter JL3.
Frizzo Fronno circuit 119 consisting of B, signal φ
Inverter 111 for inverting 2 and the dirt circuit 1
An AND gate 116 is provided in front of the input/jump 17 and inputs the output signal stone from the input/jump 111 and the signal φ. The other circuit block 62F is N
0R)Ik-) 124 and an inverter 122, and a substantial AND-type f-t circuit 128 consisting of a NAND gate 125 and an inverter 123. frig 7
The circuit includes an inverter 12 for inverting the signal n, and an OR dart 126 which is provided at the front stage of the dart circuit 128 and receives the output signal φl from the inverter 121 and the signal φ. That is, this first
In the circuit shown in FIG. 7, from the first circuit block 62E, the control pulses [f pulses φ1. .

Since pl nl flat is output, a multi-signal φ different from the case of FIG. 14 is output.
1 and a signal −1)− having a phase opposite to that of 1 is obtained at the output terminal 52,
This signal φ is inputted to the second circuit block 62F as a control signal.

The same effects as described above can also be obtained by using the four-phase signal generation circuit 62 having the configuration shown in FIGS. 16 and 17.

〔Effect of the invention〕

As explained above, the present invention has low power consumption, is suitable for high-speed operation and high integration, and can safely maintain the period between the active periods of two-phase synchronization signals without the difficulty of circuit design. Therefore, it is possible to provide a two-phase synchronous signal generation circuit whose length can be set to a minimum.

[Brief explanation of drawings]

Stripe 1 is a circuit diagram of the conventional circuit, Figure 2 is a timing chart of the circuit in Figure 1, Figure 3 is a circuit diagram of the conventional circuit, Figure 4 is a timing chart of the circuit in Figure 3, and Figure 5 is a conventional circuit. 6 is a timing chart of the circuit shown in FIG. 5, FIGS. 7 and 8 are circuit diagrams of conventional circuits, FIG. 9 is a timing chart of the circuit shown in FIG. 8, and FIG. 10 is a timing chart of the circuit shown in FIG. FIG. 11 is a circuit diagram showing the configuration of one embodiment of the first embodiment.
Fig. 0 is a timing chart of the circuit, Fig. 12 is a circuit diagram showing the configuration of another embodiment of the present invention, Fig. 13 is a circuit diagram embodying a part of Fig. 12, and Fig. 14 is Fig. 13. 15 is a circuit diagram showing a part of the circuit in detail, FIG. 15 is a timing chart of the circuit in FIG. 14, and FIGS. 16 and 17 are circuit diagrams showing other examples of the partial circuit in FIG. 13. be. 53.57...P channel MOSFET, 55
. 58...N-channel MOSFET, 61, 62
...4-phase signal generation circuit, 621.62B, 62C, 6
2D, 62E62F...Circuit block. Applicant's Representative Patent Attorney Takehiko Suzue Figure 1 Figure 2 Figure 3 Figure 4 Figure 11! 1t4

Claims (1)

[Claims] (Li) A first terminal to which a first potential is supplied, a second terminal to which a second potential is supplied, and a third terminal to which one of the two-phase synchronous signals is output. , a fourth end 4' to which the other of the two-phase synchronous signals is output, and a first MOSFE of one channel inserted between the first terminal and the third terminal.
T, a second MOSFET of the other channel inserted between the third terminal and the second terminal, and a second MOSFET of the one channel inserted between the first terminal and the fourth terminal. 3 MOSFET, a fourth MOSFET inserted between the fourth terminal and the second terminal, and one synchronization signal is inputted and supplied to each dart of the first to fourth MOSFETs. 4-phase signal generation means for generating first to fourth four-phase control signals, the first MOSFET
The period of one level of the first control signal that turns on the second MOSFET does not overlap with the period of one level of the second control signal that turns on the second MOSFET, and
The period of one level of the third control signal that turns on the FET does not overlap with the period of one level of the fourth control signal that turns on the fourth MOSFET, and the second control signal After the third control signal changes to a level that turns on the second MOSFET, the third control signal changes to a level that turns on the third MOSFET, and the fourth control signal changes to a level that turns on the third MOSFET, and the fourth control signal changes to a level that turns on the third MOSFET.
A two-phase synchronous signal generation circuit characterized in that the first control signal changes to a level that turns on the first MOSFET after the first control signal changes to a level that turns on the first MOSFET. (2) A first terminal to which the first potential is supplied, a second terminal to which the second potential is supplied, a third terminal to which one of the two-phase synchronization signals is output, and two-phase synchronization. a fourth terminal from which the other of the signals is output; and a one-channel first MOSFET inserted between the first terminal and the third terminal.
and a second MO, 5FET of the other channel inserted between the third terminal and the second terminal, and a second MO, 5FET of the one channel inserted between the first terminal and the fourth terminal. A third MOSFET, a fourth MOSFET inserted between the fourth terminal and the second terminal, one synchronization signal, and a two-phase synchronization signal output from the third and fourth terminals. and four-phase signal generating means for generating first to fourth four-phase control signals supplied to each dart of the first to fourth uosrETs, so as to turn on the first MOSFET. The period of one level of the first control signal does not overlap with the period of one level of the second control signal that turns on the second MOSFET, and
The period of one level of the third control signal that turns on the FET does not overlap with the period of one level of the fourth control signal that turns on the fourth MOSFET, and the second control signal after the third control signal changes to a level that turns on the third MOSFET, and the fourth control signal changes to a level that turns on the third MOSFET, and the fourth control signal changes to a level that turns on the third MOSFET.
A two-phase synchronous signal generation circuit characterized in that the first control signal changes to a level that turns on the first MOSFET after the first control signal changes to a level that turns on the first MOSFET. (3) The four-phase signal generating means is the first. The first circuit block receives the one synchronization signal and one of the two-phase synchronization signals output from the fourth terminal. A second circuit block generates a second control signal from the one synchronization signal and the other of the two-phase synchronization signals output from the third terminal. The two-phase synchronous signal generation circuit according to claim 2, which is configured to generate the fourth control signal. (4) Above 1. The second circuit block is the fourth and third circuit block.
The control signals are 22-phase synchronization signals outputted from each of the terminals of the terminals, and when each of these control signals is at one level, the first and second
The first to fourth control signals are controlled so that one of the third and fourth MOSFETs is turned on and the other is turned off, and then both are turned off, and then one is turned off and the other is turned on. When the levels are set, and each control signal of the two-phase synchronization is at the other level, one of the first and second MOSFETs, and one of the third and fourth MOSFETs is selected regardless of the level change of the one synchronization signal. One MO
4. The two-phase synchronous signal generation circuit according to claim 3, wherein the level setting of the first to fourth control signals is performed so as to fix the SFET in an off state. (5) Above 1. Each of the second circuit blocks has two
A free-lag frog circuit consisting of a first dart circuit of a manual logical sum type and a second dart circuit of a two manual logical product type;
and a third dart circuit of a manual logical product type or a two-human logical sum type, and one of the two-phase synchronizing signals as the control signal and the one synchronizing signal are input to the third dart circuit. However, the above-mentioned free-lag frog circuit has the above-mentioned third
5. The two-phase synchronizing signal generating circuit according to claim 4, wherein the output signal of the dart circuit and the one synchronizing signal are input.