JPS57162169A - Control system for buffer memory - Google Patents
Control system for buffer memoryInfo
- Publication number
- JPS57162169A JPS57162169A JP56047782A JP4778281A JPS57162169A JP S57162169 A JPS57162169 A JP S57162169A JP 56047782 A JP56047782 A JP 56047782A JP 4778281 A JP4778281 A JP 4778281A JP S57162169 A JPS57162169 A JP S57162169A
- Authority
- JP
- Japan
- Prior art keywords
- register
- data
- stage
- way number
- move
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
- G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
- G06F12/0804—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches with main memory updating
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Memory System Of A Hierarchy Structure (AREA)
Abstract
PURPOSE:To reduce the hardware, by obtaining a move-out address after accessing a tag section again in reading data from a data section of a buffer memory. CONSTITUTION:In a data transfer flow (move-out flow) to a main storage, control information of a main storage access port 12 is set to a stage T1. In this case, the way number is also transferred to a register T1RWAY. A tag data is again read from a tag section 4 with the stage T1 and set to a register ARO. The control information of the stage T1 is moved to a stage T2 and the way number of the register T1RWAY is moved to a register T2RWAY. At the same time when the data block is read from the data section, the way number of the register T2RWAY is given to a selector 16, which selects one address with this way number and sets it to a move-out address register.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP56047782A JPS6029985B2 (en) | 1981-03-30 | 1981-03-30 | Buffer memory control method |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP56047782A JPS6029985B2 (en) | 1981-03-30 | 1981-03-30 | Buffer memory control method |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS57162169A true JPS57162169A (en) | 1982-10-05 |
JPS6029985B2 JPS6029985B2 (en) | 1985-07-13 |
Family
ID=12784936
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP56047782A Expired JPS6029985B2 (en) | 1981-03-30 | 1981-03-30 | Buffer memory control method |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS6029985B2 (en) |
-
1981
- 1981-03-30 JP JP56047782A patent/JPS6029985B2/en not_active Expired
Also Published As
Publication number | Publication date |
---|---|
JPS6029985B2 (en) | 1985-07-13 |
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