[go: up one dir, main page]
More Web Proxy on the site http://driver.im/

JPS57162169A - Control system for buffer memory - Google Patents

Control system for buffer memory

Info

Publication number
JPS57162169A
JPS57162169A JP56047782A JP4778281A JPS57162169A JP S57162169 A JPS57162169 A JP S57162169A JP 56047782 A JP56047782 A JP 56047782A JP 4778281 A JP4778281 A JP 4778281A JP S57162169 A JPS57162169 A JP S57162169A
Authority
JP
Japan
Prior art keywords
register
data
stage
way number
move
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP56047782A
Other languages
Japanese (ja)
Other versions
JPS6029985B2 (en
Inventor
Hidehiko Nishida
Akira Hattori
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP56047782A priority Critical patent/JPS6029985B2/en
Publication of JPS57162169A publication Critical patent/JPS57162169A/en
Publication of JPS6029985B2 publication Critical patent/JPS6029985B2/en
Expired legal-status Critical Current

Links

Classifications

    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02Addressing or allocation; Relocation
    • G06F12/08Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0804Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches with main memory updating

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Memory System Of A Hierarchy Structure (AREA)

Abstract

PURPOSE:To reduce the hardware, by obtaining a move-out address after accessing a tag section again in reading data from a data section of a buffer memory. CONSTITUTION:In a data transfer flow (move-out flow) to a main storage, control information of a main storage access port 12 is set to a stage T1. In this case, the way number is also transferred to a register T1RWAY. A tag data is again read from a tag section 4 with the stage T1 and set to a register ARO. The control information of the stage T1 is moved to a stage T2 and the way number of the register T1RWAY is moved to a register T2RWAY. At the same time when the data block is read from the data section, the way number of the register T2RWAY is given to a selector 16, which selects one address with this way number and sets it to a move-out address register.
JP56047782A 1981-03-30 1981-03-30 Buffer memory control method Expired JPS6029985B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP56047782A JPS6029985B2 (en) 1981-03-30 1981-03-30 Buffer memory control method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP56047782A JPS6029985B2 (en) 1981-03-30 1981-03-30 Buffer memory control method

Publications (2)

Publication Number Publication Date
JPS57162169A true JPS57162169A (en) 1982-10-05
JPS6029985B2 JPS6029985B2 (en) 1985-07-13

Family

ID=12784936

Family Applications (1)

Application Number Title Priority Date Filing Date
JP56047782A Expired JPS6029985B2 (en) 1981-03-30 1981-03-30 Buffer memory control method

Country Status (1)

Country Link
JP (1) JPS6029985B2 (en)

Also Published As

Publication number Publication date
JPS6029985B2 (en) 1985-07-13

Similar Documents

Publication Publication Date Title
US4633440A (en) Multi-port memory chip in a hierarchical memory
US4339804A (en) Memory system wherein individual bits may be updated
US4115855A (en) Buffer memory control device having priority control units for priority processing set blocks and unit blocks in a buffer memory
GB1245601A (en) Data storage apparatus
KR860000601A (en) Memory access control system
JPS6476600A (en) Semiconductor memory device
US4020470A (en) Simultaneous addressing of different locations in a storage unit
EP0217479A2 (en) Information processing unit
JPS57162169A (en) Control system for buffer memory
GB1087575A (en) Communications accumulation and distribution
JPS5466727A (en) Access control system for buffer memory
JPS5621261A (en) Processing system for memory unit read/write
US5546592A (en) System and method for incrementing memory addresses in a computer system
JPS57182247A (en) Buffer memory device
JPS623504B2 (en)
JPS55119745A (en) Information processing unit
JPS5533282A (en) Buffer control system
JPS5748149A (en) Memory device
JPS5677967A (en) Buffer memory control system
JPS57162168A (en) Memory access control system
SU680052A1 (en) Memory unit
JPS5577072A (en) Buffer memory control system
JPS57176464A (en) Data transfer system
JPS6136854A (en) Memory switching device
EP0377886A3 (en) Arrangement for the transfer of data words subdivided into several parts