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JPS5471986A - Semiconductor device and production thereof - Google Patents

Semiconductor device and production thereof

Info

Publication number
JPS5471986A
JPS5471986A JP13870677A JP13870677A JPS5471986A JP S5471986 A JPS5471986 A JP S5471986A JP 13870677 A JP13870677 A JP 13870677A JP 13870677 A JP13870677 A JP 13870677A JP S5471986 A JPS5471986 A JP S5471986A
Authority
JP
Japan
Prior art keywords
substrate
hole
adhesive tape
semiconductor element
tape
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP13870677A
Other languages
Japanese (ja)
Other versions
JPS5620704B2 (en
Inventor
Kenji Miyajima
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, Tokyo Shibaura Electric Co Ltd filed Critical Toshiba Corp
Priority to JP13870677A priority Critical patent/JPS5471986A/en
Publication of JPS5471986A publication Critical patent/JPS5471986A/en
Publication of JPS5620704B2 publication Critical patent/JPS5620704B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/568—Temporary substrate used as encapsulation process aid
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L21/6835—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45144—Gold (Au) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
    • H01L2224/48465—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H01L2924/1815—Shape
    • H01L2924/1816—Exposing the passive side of the semiconductor or solid-state body
    • H01L2924/18165—Exposing the passive side of the semiconductor or solid-state body of a wire bonded chip
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/301—Electrical effects
    • H01L2924/3025—Electromagnetic shielding

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)

Abstract

PURPOSE: To realize amall-sized, thin, and light weight design, and to be suitable for use in wristwatches, by opening a through-hole to insert a semiconductor element into a printed wiring substrate, and covering the back with adhesive tape, resin- sealing the substrate and the element by wire bonding, and then removing the adhesive tape.
CONSTITUTION: A wiring 23 made of copper or the like is formed on a substrate made of glass, epoxy, paper phenol, or the like, to compose a printed wiring substrate 21, and a through-hole to store a semiconductor element is machined at a specified position. The back of the substrate 21 is coated with a heat resistant adhesive tape, and a semiconductor element 22 is inserted into the through-hole being in contact with the tape and is secured by adhesion. Using a gold wire 25, the wiring 23 is bonded with ultrasonic waves. Then, the gap between the element 22 and the substrate 21 is filled with epoxy resin 24 or the like, coating also the bonding surface and the gold wire 25. And the tape now unnecessary is removed. Thus, shielding from the atmosphere is sufficient, and the weight may be also reduced.
COPYRIGHT: (C)1979,JPO&Japio
JP13870677A 1977-11-18 1977-11-18 Semiconductor device and production thereof Granted JPS5471986A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP13870677A JPS5471986A (en) 1977-11-18 1977-11-18 Semiconductor device and production thereof

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP13870677A JPS5471986A (en) 1977-11-18 1977-11-18 Semiconductor device and production thereof

Publications (2)

Publication Number Publication Date
JPS5471986A true JPS5471986A (en) 1979-06-08
JPS5620704B2 JPS5620704B2 (en) 1981-05-15

Family

ID=15228214

Family Applications (1)

Application Number Title Priority Date Filing Date
JP13870677A Granted JPS5471986A (en) 1977-11-18 1977-11-18 Semiconductor device and production thereof

Country Status (1)

Country Link
JP (1) JPS5471986A (en)

Cited By (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0273740U (en) * 1988-11-25 1990-06-05
US5273938A (en) * 1989-09-06 1993-12-28 Motorola, Inc. Method for attaching conductive traces to plural, stacked, encapsulated semiconductor die using a removable transfer film
WO1997039482A1 (en) * 1996-04-18 1997-10-23 Tessera, Inc. Methods for manufacturing a semiconductor package
US6583444B2 (en) 1997-02-18 2003-06-24 Tessera, Inc. Semiconductor packages having light-sensitive chips
US7165316B2 (en) 1996-04-18 2007-01-23 Tessera, Inc. Methods for manufacturing resistors using a sacrificial layer
JP2007235791A (en) * 2006-03-03 2007-09-13 Epson Toyocom Corp Piezoelectric device
US7288739B2 (en) * 2001-02-26 2007-10-30 Sts Atl Corporation Method of forming an opening or cavity in a substrate for receiving an electronic component
EP1856733A2 (en) * 2004-09-28 2007-11-21 AgiLight, Inc. Method for micropackaging of leds and micropackage
EP1914803A1 (en) * 2006-10-20 2008-04-23 Broadcom Corporation Low profile ball grid array (BGA) package witth exposed die and method of making same

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0467905U (en) * 1990-10-22 1992-06-16

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5441671A (en) * 1977-09-08 1979-04-03 Sharp Corp Semiconductor device

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5441671A (en) * 1977-09-08 1979-04-03 Sharp Corp Semiconductor device

Cited By (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0273740U (en) * 1988-11-25 1990-06-05
US5273938A (en) * 1989-09-06 1993-12-28 Motorola, Inc. Method for attaching conductive traces to plural, stacked, encapsulated semiconductor die using a removable transfer film
WO1997039482A1 (en) * 1996-04-18 1997-10-23 Tessera, Inc. Methods for manufacturing a semiconductor package
US6001671A (en) * 1996-04-18 1999-12-14 Tessera, Inc. Methods for manufacturing a semiconductor package having a sacrificial layer
US7165316B2 (en) 1996-04-18 2007-01-23 Tessera, Inc. Methods for manufacturing resistors using a sacrificial layer
US7095054B2 (en) 1997-02-18 2006-08-22 Tessera, Inc. Semiconductor package having light sensitive chips
US6888168B2 (en) 1997-02-18 2005-05-03 Tessera, Inc. Semiconductor package having light sensitive chips
US6583444B2 (en) 1997-02-18 2003-06-24 Tessera, Inc. Semiconductor packages having light-sensitive chips
US7288739B2 (en) * 2001-02-26 2007-10-30 Sts Atl Corporation Method of forming an opening or cavity in a substrate for receiving an electronic component
EP1856733A2 (en) * 2004-09-28 2007-11-21 AgiLight, Inc. Method for micropackaging of leds and micropackage
EP1856733A4 (en) * 2004-09-28 2009-09-23 Agilight Inc Method for micropackaging of leds and micropackage
JP2007235791A (en) * 2006-03-03 2007-09-13 Epson Toyocom Corp Piezoelectric device
EP1914803A1 (en) * 2006-10-20 2008-04-23 Broadcom Corporation Low profile ball grid array (BGA) package witth exposed die and method of making same
US8169067B2 (en) 2006-10-20 2012-05-01 Broadcom Corporation Low profile ball grid array (BGA) package with exposed die and method of making same

Also Published As

Publication number Publication date
JPS5620704B2 (en) 1981-05-15

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