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JPH11204551A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

Info

Publication number
JPH11204551A
JPH11204551A JP10007156A JP715698A JPH11204551A JP H11204551 A JPH11204551 A JP H11204551A JP 10007156 A JP10007156 A JP 10007156A JP 715698 A JP715698 A JP 715698A JP H11204551 A JPH11204551 A JP H11204551A
Authority
JP
Japan
Prior art keywords
tape
substrate
dicing
bonding
adhesive
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP10007156A
Other languages
Japanese (ja)
Inventor
Hideo Yamanaka
英雄 山中
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sony Corp
Original Assignee
Sony Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sony Corp filed Critical Sony Corp
Priority to JP10007156A priority Critical patent/JPH11204551A/en
Publication of JPH11204551A publication Critical patent/JPH11204551A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L21/6835—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L21/6836—Wafer tapes, e.g. grinding or dicing support tapes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/27—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L24/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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    • H01L24/74—Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies
    • H01L24/741—Apparatus for manufacturing means for bonding, e.g. connectors
    • H01L24/743—Apparatus for manufacturing layer connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
    • H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L2221/68327—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used during dicing or grinding
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
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    • H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L2221/68327—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used during dicing or grinding
    • H01L2221/68336—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used during dicing or grinding involving stretching of the auxiliary support post dicing
    • H—ELECTRICITY
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    • H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L2221/6834—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used to protect an active side of a device or wafer
    • H—ELECTRICITY
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    • H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L2221/68359—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used as a support during manufacture of interconnect decals or build up layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/27—Manufacturing methods
    • H01L2224/274—Manufacturing methods by blanket deposition of the material of the layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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    • H01L2224/743—Apparatus for manufacturing layer connectors
    • H—ELECTRICITY
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    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/83001—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector involving a temporary auxiliary member not forming part of the bonding apparatus
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8319—Arrangement of the layer connectors prior to mounting
    • H01L2224/83191—Arrangement of the layer connectors prior to mounting wherein the layer connectors are disposed only on the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/838—Bonding techniques
    • H01L2224/8385—Bonding techniques using a polymer adhesive, e.g. an adhesive based on silicone, epoxy, polyimide, polyester
    • H01L2224/83855—Hardening the adhesive by curing, i.e. thermosetting
    • H—ELECTRICITY
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    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01004—Beryllium [Be]
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    • H01L2924/06—Polymers
    • H01L2924/078—Adhesive characteristics other than chemical
    • H01L2924/07802—Adhesive characteristics other than chemical not being an ohmic electrical conductor
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    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1515—Shape
    • H01L2924/15153—Shape the die mounting substrate comprising a recess for hosting the device
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    • H01L2924/15165—Monolayer substrate
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    • H01L2924/181—Encapsulation

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Die Bonding (AREA)
  • Dicing (AREA)

Abstract

PROBLEM TO BE SOLVED: To prevent the chips of an adhesive layer for die bond which is generated at cutting and dividing of a substrate from being attached directly to the surface of a chip member. SOLUTION: A transparent protecting tape 3 is attached to a functional element forming part 2 of a substrate 1, and the functional element is protected by the transparent tape 3, and the back face of the substrate 1 is cut so that the substrate is made into a prescribed thickness. Then, a dicing die bond tape 4 in which an ultraviolet irradiation curing adhesive 4b and a thermosetting type resin 4c are laminated on a base film 4a is attached to the back face of the substrate 1. Then, a chip part is formed by cutting the substrate 1 without cutting or dividing the base film 4a. Then, the chip part is irradiated with ultraviolet ray, and the ultraviolet irradiation curing type adhesive 4b is hardened. Then, the chip part is picked-up loaded, and temporarily bonded on a package member by the use of the thermosetting resin 4c as an adhesive. Thereafter, the thermosetting type resin 4c is heated and hardened, and the chip member is bonded and fixed to the package member.

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【０００１】[0001]

【発明の属する技術分野】本発明は、機能素子の動作検
査を終了した後、チップ部品に形成してこれをパッケー
ジ部材に搭載する、半導体装置の製造方法に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, which comprises forming a chip component and mounting it on a package member after an operation test of a functional element is completed.

【０００２】[0002]

【従来の技術】一般に半導体装置を製造するにあたって
は、シリコン等の基板（ウエハ）に多数の機能素子を形
成し、その後基板の状態でこれら機能素子の動作試験を
行っている。また、動作試験を行った後には、この基板
を各機能素子毎に分割してチップ部品とし、このチップ
部品を所定のパッケージ部材に固定・搭載して電気的な
配線を行い、モールド樹脂による封止や中空パッケージ
での気密封止等のパッケージを行って製品を完成させて
いる。2. Description of the Related Art In general, in manufacturing a semiconductor device, a large number of functional elements are formed on a substrate (wafer) made of silicon or the like, and thereafter, operation tests of these functional elements are performed on the substrate. After performing the operation test, the substrate is divided into functional elements to form chip components. The chip components are fixed and mounted on a predetermined package member, and electrical wiring is performed. The product is completed by performing packaging such as sealing and airtight sealing with a hollow package.

【０００３】ところで、基板を各機能素子毎に分割する
にあたっては、分割により形成されたチップがバラバラ
にならないよう、基板の裏面側に予めダイシング用粘着
テープを貼合しておき、その状態で該粘着テープを切断
分離することなくダイサーによって基板を切断分割し、
チップ部品を形成している。そして、この後必要があれ
ばダイシング用粘着テープを延伸してチップ部品間の間
隙を拡張し、ダイボンダーの角錐コレットまたは平コレ
ットでチップ部品をピックアップする。When the substrate is divided for each functional element, an adhesive tape for dicing is pasted on the back surface of the substrate in advance so that the chips formed by the division do not fall apart. Cut and split the substrate with a dicer without cutting and separating the adhesive tape,
Chip components are formed. Then, if necessary, the adhesive tape for dicing is stretched to expand the gap between the chip components, and the chip components are picked up by the pyramid collet or the flat collet of the die bonder.

【０００４】また、このチップ部品をパッケージ部材に
固定・搭載して電気的な配線を行う場合、予めディスペ
ンサーによってリードフレームのダイパッド部に導電ペ
ースト、例えば銀ペーストを塗布しておき、そのうえに
チップ部品をマウントして仮接着し、銀ペーストを加熱
硬化して本接着を行っている。しかしながら、このよう
なディスペンサーによる塗布方式では吐出量の安定性に
問題があり、導電性または絶縁性ペーストのはみだしや
チップ汚染、接着面積のバラツキ、接着強度のバラツキ
等の不都合を招いてしまう。In the case where the chip component is fixed and mounted on a package member to perform electrical wiring, a conductive paste, for example, a silver paste is applied to a die pad portion of a lead frame by a dispenser in advance, and the chip component is further placed thereon. It is mounted and temporarily bonded, and the silver paste is heated and cured to perform the actual bonding. However, such a dispenser-based coating method has a problem in the stability of the discharge amount, and causes problems such as protrusion of the conductive or insulating paste, chip contamination, uneven bonding area, and uneven bonding strength.

【０００５】このような背景から、近年、ダイシングテ
ープとしての機能とダイボンディング材としての機能を
兼ね備えたダイシング−ダイボンド用テープが提供さ
れ、実用に供されている。このダイシング−ダイボンド
用テープは、ベースフィルム上に紫外線照射硬化型接着
剤と熱硬化型樹脂とがこの順に積層されて構成されたも
ので、その熱硬化型樹脂側が貼着側として前記基板の裏
面に貼合され用いられるようになっている。そして、こ
のようにして貼合されその後基板が切断分割されると、
ダイボンディング材として機能する熱硬化型樹脂はベー
スフィルムおよび紫外線照射硬化型接着剤から分離して
チップ部品の裏面にそのまま残り、パッケージ部材とチ
ップ部品との間の接着剤となる。[0005] From such a background, in recent years, a dicing-die bonding tape having both a function as a dicing tape and a function as a die bonding material has been provided and put to practical use. This dicing-die bonding tape is formed by laminating an ultraviolet ray-curable adhesive and a thermosetting resin on a base film in this order, and the thermosetting resin side is the bonding side and the back side of the substrate. It is intended to be used after being pasted on. And when the substrate is cut and divided after being bonded in this way,
The thermosetting resin functioning as a die bonding material is separated from the base film and the ultraviolet radiation-curable adhesive and remains as it is on the back surface of the chip component, and becomes an adhesive between the package member and the chip component.

【０００６】したがって、基板の切断分割（ダイシン
グ）直後に、すでにチップ部品の裏面全体に熱硬化型樹
脂からなるダイボンド用の接着層が均一の厚みで確実に
存在していることから、このチップ部品をパッケージ部
材に固定・搭載する際に導電性または絶縁性ペーストを
リードフレームに塗布する必要がなくなり、したがって
高精度のディスペンサーなどが必要なくなり、もちろん
前述したようなペーストのはみだしやチップ汚染、接着
面積のバラツキ、接着強度のバラツキ等もなくなる。な
お、ダイボンド用の接着層を構成する熱硬化型樹脂とし
ては、導電性のものと非導電性のものがあり、それぞれ
必要に応じて適宜選択使用されるようになっている。[0006] Therefore, immediately after the substrate is cut and divided (diced), the die-bonding adhesive layer made of a thermosetting resin is surely present with a uniform thickness on the entire back surface of the chip component. There is no need to apply a conductive or insulating paste to the lead frame when fixing and mounting the package on the package member.Therefore, a high-precision dispenser is not required. And variations in adhesive strength are also eliminated. The thermosetting resin constituting the adhesive layer for die bonding includes a conductive resin and a non-conductive resin, and each is appropriately selected and used as needed.

【０００７】[0007]

【発明が解決しようとする課題】しかしながら、前記の
ようなダイシング−ダイボンド用テープを用いても、基
板を切断分割（ダイシング）した際、該ダイシング−ダ
イボンド用テープのうち少なくとも熱硬化型樹脂からな
るダイボンド用の接着層がフルカットされるので、その
切削屑がチップ部品表面に残ってしまうことがある。す
ると、ダイボンド用の接着層が導電性の銀含有エポキシ
系接着剤からなる場合には、電気的な特性の不良を招い
てしまい、結果として歩留、品質が低下してしまう。ま
た、ダイボンド用の接着層が非導電性エポキシ系接着剤
からなる場合でも、これがＡｌパッドの表面に残るとワ
イヤボンド付き不良を引き起こしてしまう。However, even when the above dicing-die bonding tape is used, when the substrate is cut and divided (diced), at least the dicing-die bonding tape is made of a thermosetting resin. Since the adhesive layer for die bonding is fully cut, the cutting chips may remain on the chip component surface. Then, when the adhesive layer for die bonding is made of a conductive silver-containing epoxy-based adhesive, the electrical characteristics are deteriorated, and as a result, the yield and quality are reduced. Further, even when the adhesive layer for die bonding is made of a non-conductive epoxy adhesive, if this remains on the surface of the Al pad, it causes a failure with wire bonding.

【０００８】本発明は前記事情に鑑みてなされたもの
で、その目的とするところは、基板を切断分割した際に
発生するダイボンド用の接着層の切削屑に起因する不都
合を解消した、半導体装置の製造方法を提供することに
ある。SUMMARY OF THE INVENTION The present invention has been made in view of the above circumstances, and an object of the present invention is to eliminate the inconvenience caused by cutting chips of an adhesive layer for die bonding generated when a substrate is cut and divided. It is to provide a manufacturing method of.

【０００９】[0009]

【課題を解決するための手段】本発明の半導体装置の製
造方法では、複数の機能素子を表面に形成し、これら機
能素子の動作検査を済ませた後の基板の機能素子形成部
に透明保護テープを貼合する工程と、前記透明保護テー
プで前記機能素子を保護しつつ前記基板の裏面研削また
は裏面研削と裏面エッチングで該基板を所定の厚さにす
る工程と、ベースフィルム上に紫外線照射硬化型接着剤
と熱硬化型樹脂とをこの順に積層してダイシングテープ
としての機能とダイボンディング材としての機能を兼ね
備えたダイシング−ダイボンド用テープを、その熱硬化
型樹脂側を貼着側として前記基板の裏面に貼合する工程
と、前記ダイシング−ダイボンド用テープのベースフィ
ルムを切断分離することなく、前記基板を切断して複数
の機能素子毎に分割し、チップ部品を形成する工程と、
前記チップ部品の少なくとも裏面側に紫外線を照射処理
して前記ダイシング−ダイボンド用テープの紫外線照射
硬化型接着剤を硬化させる工程と、前記紫外線照射処理
後のチップ部品を前記ダイシング−ダイボンド用テープ
からピックアップし、前記ダイシング−ダイボンド用テ
ープの熱硬化型樹脂を接着剤として所定のパッケージ部
材に搭載し仮接着する工程と、前記熱硬化型樹脂を加熱
硬化させてチップ部品を前記パッケージ部材に接着固定
する工程と、を備えてなることを前記課題の解決手段と
した。According to the method of manufacturing a semiconductor device of the present invention, a plurality of functional elements are formed on a surface, and after a functional inspection of these functional elements is completed, a transparent protective tape is formed on a functional element forming portion of a substrate. Bonding the substrate, grinding the back surface of the substrate or grinding the back surface and etching the back surface of the substrate to a predetermined thickness while protecting the functional element with the transparent protective tape, and curing the substrate with ultraviolet irradiation. A dicing-die bonding tape having a function as a dicing tape and a function as a die bonding material by laminating a mold adhesive and a thermosetting resin in this order, the substrate having the thermosetting resin side as the sticking side. Laminating the base film of the dicing-die bonding tape and separating the base film into a plurality of functional elements without separating the base film. And a step of forming a chip component,
Irradiating at least the back surface side of the chip component with ultraviolet light to cure the ultraviolet irradiation-curable adhesive of the dicing-die bonding tape, and picking up the chip component after the ultraviolet irradiation treatment from the dicing-die bonding tape Then, a step of mounting the thermosetting resin of the dicing-die bonding tape as an adhesive on a predetermined package member and temporarily bonding the same, and heating and curing the thermosetting resin to bond and fix a chip component to the package member. And a step for solving the above-mentioned problem.

【００１０】この半導体装置の製造方法によれば、基板
を切断して複数のチップ部品を形成するに先立ち、基板
の機能素子形成部に透明保護テープを貼合するので、該
基板を切断分割してチップ部品を形成した際にダイボン
ド用の接着層の切削屑が発生しても、この切削屑がチッ
プ部品の表面に直接付着することがなく、したがってこ
の切削屑に起因する不都合が防止される。According to this method of manufacturing a semiconductor device, before the substrate is cut to form a plurality of chip parts, the transparent protective tape is attached to the functional element forming portion of the substrate. Even if chips are generated in the adhesive layer for die bonding when chip parts are formed by cutting, the chips do not directly adhere to the surface of the chip parts, thereby preventing inconvenience caused by the chips. .

【００１１】[0011]

【発明の実施の形態】以下、本発明の半導体装置の製造
方法をその一実施形態例に基づいて詳しく説明する。こ
の実施形態例では、まず、図１（ａ）に示すように基板
（ウエハ）１の表層部に予め多数の機能素子を設けて素
子形成部（機能素子形成部）２を形成し、これら機能素
子の動作検査を済ませた後の基板１を用意する。ここ
で、機能素子として具体的には、シリコンのバイポーラ
ＩＣ、ＭＯＳＩＣ、ＣＣＤや化合物半導体（ＧａＡｓ）
ＩＣなどが挙げられる。なお、機能素子の動作検査にお
いて不良マーキングとしてはＢａｄインクマーク方式で
なくマッピング方式が採用される。DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, a method for manufacturing a semiconductor device according to the present invention will be described in detail based on an embodiment. In this embodiment, first, as shown in FIG. 1A, a large number of functional elements are provided in advance on a surface layer of a substrate (wafer) 1 to form an element forming section (functional element forming section) 2, and these functions are formed. The substrate 1 after the operation inspection of the device is prepared. Here, as the functional element, specifically, silicon bipolar IC, MOSIC, CCD or compound semiconductor (GaAs)
IC and the like. In the operation inspection of the functional element, as a defective marking, a mapping method is adopted instead of the Bad ink mark method.

【００１２】次に、このような構成の基板１の素子形成
部２に、図１（ｂ）に示すように保護テープ３を貼合す
る。この保護テープ３としては、ダイシングおよびダイ
ボンドオートアライメントを行う上で透明のものが用い
られ、またこの例においては紫外線照射硬化型接着剤で
あり、かつ熱収縮自己剥離型ベースフィルムのものが用
いられている。すなわち、この保護テープ３は、例えば
厚さ４０μｍ程度のベースフィルム３ａに厚さ２０μｍ
程度の紫外線照射硬化型樹脂からなる接着層３ｂを形成
したものである。ベースフィルム３ａとしては、例えば
ポリオレフィン系やポリプロピレン系などの熱収縮性が
ありしたがって自己剥離性があるものが用いられ、また
接着層３ｂとしては、アクリル系のものなどが用いら
れ、糊残りのないタイプが必要である。Next, as shown in FIG. 1B, a protective tape 3 is bonded to the element forming portion 2 of the substrate 1 having such a configuration. As the protective tape 3, a transparent one is used for performing dicing and die bond auto-alignment, and in this example, an ultraviolet irradiation-curable adhesive and a heat-shrinkable self-peeling base film are used. ing. That is, the protective tape 3 is, for example, a base film 3a having a thickness of about 40 μm and a thickness of 20 μm.
An adhesive layer 3b made of an ultraviolet irradiation curable resin is formed. As the base film 3a, for example, a heat-shrinkable, self-peeling material such as polyolefin or polypropylene is used, and an acrylic film or the like is used as the adhesive layer 3b. Type is required.

【００１３】次に、図１（ｃ）に示すように保護フィル
ム３を貼合した状態のままで、すなわち該保護テープ３
で素子形成部２の機能素子を保護しつつ、前記基板１の
裏面研削（バックグラインド）を行い、該基板１を所定
の厚さにする。このバックグラインドでは、まず＃３２
０番手の砥石で粗研削を行い、その後精密研削（例えば
＃２０００番手の砥石）で４００μｍの厚さにまで研削
を行う。そして、必要に応じて基板１の裏面にＨＦ−Ｈ
ＮＯ3 系エッチング液でのシリコンエッチングを施し、
研削で生じた基板１の歪みを取り除いておく。なお、シ
リコン裏面エッチングする場合は、耐酸性の保護テープ
とすることが必要である。また、シリコンエッチング液
に長く触れないような方法、例えばスピンエッチングが
望ましい。Next, as shown in FIG. 1 (c), the protective film 3 is kept bonded,
The back surface grinding (back grinding) of the substrate 1 is performed while protecting the functional elements of the element forming section 2 by the above, so that the substrate 1 has a predetermined thickness. In this back grind, first, # 32
Rough grinding is performed with a 0th grinding wheel, and then grinding is performed to a thickness of 400 μm by precision grinding (for example, a # 2000 grinding wheel). Then, if necessary, HF-H
Silicon etching with NO 3 type etching solution,
The distortion of the substrate 1 caused by the grinding is removed. When etching the back surface of silicon, it is necessary to use an acid-resistant protective tape. Also, a method that does not touch the silicon etchant for a long time, for example, spin etching is desirable.

【００１４】このようにして裏面研削を行ったら、図２
（ａ）に示すようにこの研削後の基板１の裏面（研削
面）にダイシング−ダイボンド用テープ４を貼合する。
このテープ４は、厚さ９０μｍ程度のベースフィルム４
ａ上に厚さ１０〜３０μｍ程度の紫外線照射硬化型接着
剤４ｂと厚さ１０〜３０μｍ程度の熱硬化型樹脂４ｃと
をこの順に積層し、ダイシングテープとしての機能とダ
イボンディング材としての機能を兼ね備えたもので、そ
の熱硬化型樹脂４ｃ側を貼着側として前記基板１の裏面
に貼合されたものである。ベースフィルム４ａはポリオ
レフィン系樹脂等からなり、紫外線照射硬化型接着剤４
ｂは不飽和結合を２個以上有する付加重合性化合物やエ
ポキシ基を有するアルコキシシラン等の光重合性化合物
と、光重合開始剤とを配合してなるものであり、熱硬化
型樹脂４ｃはエポキシ樹脂等からなるものである。After grinding the back surface in this manner, FIG.
As shown in (a), the dicing-die bonding tape 4 is bonded to the back surface (ground surface) of the substrate 1 after the grinding.
This tape 4 is made of a base film 4 having a thickness of about 90 μm.
a) A UV curable adhesive 4b having a thickness of about 10 to 30 μm and a thermosetting resin 4c having a thickness of about 10 to 30 μm are laminated in this order, and the function as a dicing tape and the function as a die bonding material are performed. The thermosetting resin 4c is bonded to the back surface of the substrate 1 with the thermosetting resin 4c side as the bonding side. The base film 4a is made of a polyolefin resin, etc.
b is a mixture of an addition polymerizable compound having two or more unsaturated bonds, a photopolymerizable compound such as an alkoxysilane having an epoxy group, and a photopolymerization initiator, and the thermosetting resin 4c is an epoxy resin. It is made of resin or the like.

【００１５】次いで、図２（ｂ）に示すようにダイシン
グ−ダイボンド用テープ４のベースフィルム４ａを切断
分離することなく、前記基板１をフルカットダイシング
して複数の機能素子毎に分割し、多数のチップ部品５…
を形成する。なお、このフルカットダイシングについて
は、ベースフィルム４ａを３０〜４０μｍ程度切り込む
ように行うことで、基板１の切断残りが生じたり、ベー
スフィルム４ａが切断によって分断（分離）されてしま
うといった不都合を回避することができる。Next, as shown in FIG. 2B, the substrate 1 is fully cut and diced into a plurality of functional elements without cutting and separating the base film 4a of the dicing-die bonding tape 4 to obtain a large number of functional elements. Chip parts 5 ...
To form In this full-cut dicing, by cutting the base film 4a by about 30 to 40 μm, it is possible to avoid inconveniences that the substrate 1 is left uncut or the base film 4a is cut (separated) by cutting. can do.

【００１６】このようにして基板１をフルカットダイシ
ングすると、当然基板１の切削屑が生じるものの、基板
１の素子形成部２側には予め保護テープ３が貼合されて
いるので、生じた切削屑がチップ部品５に残ってその素
子形成部２上に付着してしまうといったことが回避され
る。When the substrate 1 is subjected to full-cut dicing in this manner, although chips of the substrate 1 are naturally generated, since the protective tape 3 is bonded to the element forming portion 2 side of the substrate 1 in advance, the resulting cutting is performed. It is avoided that the debris remains on the chip part 5 and adheres to the element forming part 2.

【００１７】次いで、ベースフィルム４ａの残っている
多数のチップ部品５…に対し、特にダイシング−ダイボ
ンド用テープ４と保護フィルム３とに照射するべく紫外
線を所定量（例えば−各々２００ｍＪ／ｃｍ2 程度）で
照射し、ダイシング−ダイボンド用テープ４の紫外線照
射硬化型接着剤４ｂおよび保護テープ３の接着層３ｂを
硬化させる。Next, a predetermined amount of ultraviolet rays (for example, about 200 mJ / cm 2 each) is applied to the many chip parts 5... Where the base film 4 a remains, particularly to irradiate the dicing-die bonding tape 4 and the protective film 3. ) To cure the ultraviolet irradiation-curable adhesive 4b of the dicing-die bonding tape 4 and the adhesive layer 3b of the protective tape 3.

【００１８】このようにして紫外線照射処理を行った
ら、図２（ｃ）に示すようにチップ部品５を前記ダイシ
ング−ダイボンド用テープ４からピックアップし、図３
（ａ）に示すようにモールドパッケージ用のリードフレ
ームにおけるダイパッド部（パッケージ部材）６上に、
あるいは図４（ａ）に示すように中空パッケージのダイ
パッド部（パッケージ部材）７上に搭載し仮接着する。
このとき、この仮接着にあたっては、前記ダイシング−
ダイボンド用テープ４の熱硬化型樹脂４ｃを接着剤とし
てチップ部品５とダイパッド部６（あるいはダイパッド
部７）との間を接着させるので、従来のごとく銀ペース
トをディスペンサーで塗布するといった必要がなくな
る。After performing the ultraviolet irradiation treatment in this manner, the chip parts 5 are picked up from the dicing-die bonding tape 4 as shown in FIG.
As shown in (a), on a die pad portion (package member) 6 in a lead frame for a mold package,
Alternatively, as shown in FIG. 4A, it is mounted on a die pad portion (package member) 7 of a hollow package and temporarily bonded.
At this time, for the temporary bonding, the dicing-
Since the chip component 5 and the die pad portion 6 (or the die pad portion 7) are bonded to each other by using the thermosetting resin 4c of the die bonding tape 4 as an adhesive, there is no need to apply a silver paste with a dispenser as in the related art.

【００１９】なお、リードフレームや中空パッケージに
ついては、そのダイパッド部６（７）にチップ部品５を
搭載するに先立って６０〜８０℃程度に加熱しておき、
前述した熱硬化型樹脂４ｃによる仮接着を促進してお
く。したがって、ガラス転移温度が低めのタイプを選択
することが望ましい。また、チップ部品５のピックアッ
プについては、図２（ｃ）に示したように平コレット８
を用いて行っている。このように平コレット８を用いる
と、角錐コレットを用いた場合にはチップ部品５のサイ
ズに応じて専用のコレットが必要となっていたものの、
平コレット８はサイズに関係なく使用することができる
ことから、コレットを専用化する必要がなくなり、この
ためチップ部品サイズの種類に応じて多数のコレットを
用意しておく必要がなくなる。また、このピックアップ
を行う際、チップ部品５にはその素子形成部２を覆った
状態に保護テープ３が貼合されているので、素子形成部
２が平コレット８に直接当接することがなく、したがっ
て素子形成部２にキズがついたり汚れが付着するといっ
たことが防止される。The lead frame and the hollow package are heated to about 60 to 80 ° C. before mounting the chip component 5 on the die pad portion 6 (7).
Temporary adhesion by the above-mentioned thermosetting resin 4c is promoted. Therefore, it is desirable to select a type having a lower glass transition temperature. Further, as shown in FIG. 2C, the pickup of the chip component 5 is a flat collet 8.
It is performed using. As described above, when the flat collet 8 is used, a dedicated collet is required according to the size of the chip component 5 when the pyramid collet is used.
Since the flat collet 8 can be used irrespective of its size, it is not necessary to specialize the collet, and thus it is not necessary to prepare a large number of collets according to the type of chip component size. Also, when performing this pickup, since the protective tape 3 is bonded to the chip component 5 so as to cover the element forming part 2, the element forming part 2 does not directly contact the flat collet 8, Therefore, it is possible to prevent the element forming portion 2 from being scratched or stained.

【００２０】次いで、図３（ｂ）あるいは図４（ｂ）に
示すようにチップ部品５上の保護テープ３に１００〜１
２０℃程度の熱風をブローし、該保護テープ３をその熱
シュリンク性（自己剥離性）によって自己剥離させる。
同時に、自己剥離した保護テープは吸引除去する。そし
て、このようにして保護テープ３を自己剥離させたら、
チップ部材５をパッケージごと１８０℃で３０〜６０分
間程度オーブンベークし、チップ部品５とダイパッド部
６（７）との間を仮接着している熱硬化型樹脂４ｃを加
熱硬化させ、チップ部品５を前記ダイパッド部（パッケ
ージ部材）６（７）に接着固定する。その後、ワイヤー
ボンド、モールドを行い、さらに従来と同様の工程を経
ることによって半導体装置を得る。Next, as shown in FIG. 3B or FIG. 4B, 100 to 1
Blowing hot air of about 20 ° C., the protective tape 3 is self-peeled by its thermal shrink property (self-peeling property).
At the same time, the self-peeled protective tape is removed by suction. And when the protective tape 3 is self-peeled in this way,
The chip member 5 together with the package is oven-baked at 180 ° C. for about 30 to 60 minutes, and the thermosetting resin 4 c temporarily bonding the chip component 5 and the die pad portion 6 (7) is heated and cured. To the die pad portion (package member) 6 (7). Thereafter, wire bonding and molding are performed, and the semiconductor device is obtained through the same steps as those in the related art.

【００２１】このような半導体装置の製造方法にあって
は、基板１をフルカットダイシングするに先立ち、基板
１の素子形成部２に保護テープ３を貼合するので、フル
カットダイシング時に発生する切削屑がチップ部品の表
面に直接付着することがなく、したがってこの切削屑に
起因する不都合を防止することができる。また、フルカ
ットダイシング後、チップ部品５の表面に保護テープ３
が残るので、これをピックアップする際コレットによる
キズの発生や汚れの付着がなく、平コレット８の使用を
可能にすることができる。そして、このように平コレッ
ト８を使用することにより、チップサイズ毎に交換する
必要がある角錐コレットに比べ、約３０％ダイボンディ
ングの生産性を向上することができる。また、保護テー
プ３が熱収縮自己剥離型であることから、ダイボンド時
における熱硬化型樹脂４ｃの加熱の際に該保護テープ３
が自己収縮により自己剥離するようになり、したがって
作業性が良くなり生産性が向上する。In such a method of manufacturing a semiconductor device, the protective tape 3 is bonded to the element forming portion 2 of the substrate 1 before the substrate 1 is subjected to full-cut dicing. The debris does not directly adhere to the surface of the chip component, so that inconvenience caused by the debris can be prevented. After the full cut dicing, a protective tape 3 is applied to the surface of the chip component 5.
The flat collet 8 can be used without any scratches or dirt attached by the collet when picking up the flat collet 8. By using the flat collet 8 as described above, the productivity of die bonding can be improved by about 30% as compared with a pyramid collet that needs to be replaced for each chip size. Further, since the protective tape 3 is a heat-shrinkable self-peeling type, when the thermosetting resin 4c is heated during die bonding, the protective tape 3 is removed.
Self-exfoliates due to self-shrinkage, thus improving workability and improving productivity.

【００２２】なお、前記実施形態例では保護テープ３を
熱収縮自己剥離型としたが、本発明はこれに限定される
ことなくしたがって保護テープが熱収縮自己剥離型でな
くてもよく、その場合には、フルカットダイシングし、
さらにピックアップしてダイパッド部６（７）に仮接着
した後、熱硬化型樹脂４ｃの加熱硬化に先立って保護テ
ープを剥離テープで剥離するようにすればよい。また、
前記実施形態例では、保護テープ３をＵＶ照射硬化型接
着剤としたが、本発明はこれに限定されることなく、粘
着型接着剤でもよい。このときは、糊残りのないような
低接着力タイプとすることが必要である。なお、フルカ
ットダイシング後に保護テープを剥離テープで剥離し、
キズのつかない平コレットまたは角錐コレットでピック
アップしてもよい。In the above embodiment, the protective tape 3 is a heat-shrinkable self-peeling type. However, the present invention is not limited to this. Therefore, the protective tape may not be a heat-shrinkable self-peeling type. Is full cut dicing,
Further, after being picked up and temporarily bonded to the die pad portion 6 (7), the protective tape may be peeled off with a peeling tape prior to the heat curing of the thermosetting resin 4c. Also,
In the above-described embodiment, the protective tape 3 is a UV irradiation-curable adhesive. However, the present invention is not limited to this, and may be an adhesive adhesive. In this case, it is necessary to use a low-adhesion type without leaving adhesive residue. After full-cut dicing, peel off the protective tape with a release tape,
It may be picked up by a flat collet or a pyramid collet that does not scratch.

【００２３】[0023]

【発明の効果】以上説明したように本発明の半導体装置
の製造方法は、基板を切断して複数のチップ部品を形成
するに先立ち、基板の機能素子形成部に保護テープを貼
合するようにした方法であるから、該基板を切断分割し
てチップ部品を形成した際にダイボンド用の接着層の切
削屑が発生しても、この切削屑がチップ部品の表面に直
接付着することがなく、したがってこの切削屑に起因し
て特性不良やワイヤボンディング付き不良などが起こる
のを確実に防止することができる。As described above, in the method of manufacturing a semiconductor device according to the present invention, a protective tape is attached to a functional element forming portion of a substrate before cutting the substrate to form a plurality of chip components. Therefore, even if cutting chips of the adhesive layer for die bonding are generated when the substrate is cut and divided to form a chip component, the cutting chips do not directly adhere to the surface of the chip component, Therefore, it is possible to reliably prevent the occurrence of a characteristic defect, a defect with wire bonding, or the like due to the cutting chips.

【図面の簡単な説明】[Brief description of the drawings]

【図１】（ａ）〜（ｃ）は、本発明の製造方法を工程順
に説明するための要部側断面図である。FIGS. 1 (a) to 1 (c) are side sectional views for explaining a manufacturing method of the present invention in the order of steps.

【図２】（ａ）〜（ｃ）は、本発明の製造方法を説明す
るための図であり、図１（ｃ）に続く工程を順に説明す
るための要部側断面図である。FIGS. 2 (a) to 2 (c) are views for explaining the manufacturing method of the present invention, and are main-part side sectional views for sequentially explaining steps subsequent to FIG. 1 (c).

【図３】（ａ）、（ｂ）は、図２（ｃ）に示した工程に
続いて、モールドパッケージに搭載する場合の例を説明
するための要部側断面図である。FIGS. 3 (a) and 3 (b) are cross-sectional side views of essential parts for explaining an example of a case where the semiconductor device is mounted on a mold package following the process shown in FIG. 2 (c).

【図４】（ａ）、（ｂ）は、図２（ｃ）に示した工程に
続いて、中空パッケージに搭載する場合の例を説明する
ための要部側断面図である。4 (a) and 4 (b) are cross-sectional side views of an essential part for explaining an example of mounting in a hollow package following the step shown in FIG. 2 (c).

【符号の説明】[Explanation of symbols]

１…基板、２…素子形成部（機能素子形成部）、３…保
護テープ、４…ダイシング−ダイボンド用テープ、４ｂ
…紫外線照射硬化型接着剤、４ｃ…熱硬化型樹脂、５…
チップ部品、６，７…ダイパッド部（パッケージ部
材）、８…平コレットDESCRIPTION OF SYMBOLS 1 ... Substrate, 2 ... Element formation part (functional element formation part), 3 ... Protection tape, 4 ... Dicing-die bonding tape, 4b
... ultraviolet radiation curing adhesive, 4c ... thermosetting resin, 5 ...
Chip parts, 6, 7 ... die pad part (package member), 8 ... flat collet

Claims (5)

【特許請求の範囲】[Claims] 【請求項１】 複数の機能素子を表面に形成し、これら
機能素子の動作検査を済ませた後の基板の機能素子形成
部に透明保護テープを貼合する工程と、 前記透明保護テープで前記機能素子を保護しつつ前記基
板の裏面研削または裏面研削と裏面エッチングにより該
基板を所定の厚さにする工程と、 ベースフィルム上に紫外線照射硬化型接着剤と熱硬化型
樹脂とをこの順に積層してダイシングテープとしての機
能とダイボンディング材としての機能を兼ね備えたダイ
シング−ダイボンド用テープを、その熱硬化型樹脂側を
貼着側として前記基板の裏面に貼合する工程と、 前記ダイシング−ダイボンド用テープのベースフィルム
を切断分離することなく、前記基板を切断して複数の機
能素子毎に分割し、チップ部品を形成する工程と、 前記チップ部品の少なくとも裏面側に紫外線を照射処理
して前記ダイシング−ダイボンド用テープの紫外線照射
硬化型接着剤を硬化させる工程と、 前記紫外線照射処理後のチップ部品を前記ダイシング−
ダイボンド用テープからピックアップし、前記ダイシン
グ−ダイボンド用テープの熱硬化型樹脂を接着剤として
所定のパッケージ部材に搭載し仮接着する工程と、 前記熱硬化型樹脂を加熱硬化させてチップ部品を前記パ
ッケージ部材に接着固定する工程と、を備えてなること
を特徴とする半導体装置の製造方法。1. A step of forming a plurality of functional elements on a surface and bonding a transparent protective tape to a functional element forming portion of a substrate after the operation inspection of the functional elements has been completed; A step of grinding the backside of the substrate or a backside grinding and backside etching of the substrate to a predetermined thickness while protecting the element, and laminating an ultraviolet irradiation-curable adhesive and a thermosetting resin on the base film in this order. Bonding a dicing-die bonding tape having both a function as a dicing tape and a function as a die bonding material to the back surface of the substrate with its thermosetting resin side as a bonding side; and Cutting the substrate without cutting and separating the base film of the tape, dividing the substrate into a plurality of functional elements, and forming chip components; Wherein by irradiation treatment with ultraviolet rays to at least the back side of the part dicing - curing the tape of the ultraviolet radiation curable adhesive for die bonding, the dicing the chip component after the ultraviolet irradiation treatment -
Picking up from the die-bonding tape, mounting the thermosetting resin of the dicing-die-bonding tape on a predetermined package member as an adhesive and temporarily bonding the same, and heat-curing the thermosetting resin to package the chip component into the package. A method of bonding and fixing to a member. 【請求項２】 前記透明保護テープが紫外線照射硬化型
であり、 前記チップ部品に紫外線を照射処理して前記ダイシング
−ダイボンド用テープの紫外線照射硬化型接着剤を硬化
させる工程において、前記透明保護テープをも紫外線を
照射処理してその接着層を硬化させることを特徴とする
請求項１記載の半導体装置の製造方法。2. The step of irradiating the chip component with an ultraviolet ray to cure the ultraviolet ray-curing adhesive of the dicing-die bonding tape, wherein the transparent protective tape is of an ultraviolet ray curing type. 2. The method for manufacturing a semiconductor device according to claim 1, further comprising irradiating ultraviolet rays to cure the adhesive layer. 【請求項３】 前記透明保護テープが熱収縮自己剥離型
であり、 前記熱硬化型樹脂を加熱硬化させる工程に先立ち、ある
いはこの加熱硬化工程において、加熱により前記透明保
護テープを自己剥離させることを特徴とする請求項１記
載の半導体装置の製造方法。3. The method according to claim 1, wherein the transparent protective tape is a heat-shrinkable self-peeling type, and the self-peeling of the transparent protective tape by heating is performed prior to or in the heat curing step of the thermosetting resin. The method for manufacturing a semiconductor device according to claim 1, wherein: 【請求項４】 前記の透明保護テープに熱風をブロー
し、自己剥離した透明保護テープ吸引除去することを特
徴とする請求項３記載の半導体装置の製造方法。4. The method of manufacturing a semiconductor device according to claim 3, wherein hot air is blown to said transparent protective tape, and the self-peeled transparent protective tape is suctioned and removed. 【請求項５】 前記紫外線照射処理後のチップ部品を前
記ダイシング−ダイボンド用テープからピックアップす
る際、平コレットを用いて行うことを特徴とする請求項
１記載の半導体装置の製造方法。5. The method of manufacturing a semiconductor device according to claim 1, wherein the chip component after the ultraviolet irradiation treatment is picked up from the dicing-die bonding tape using a flat collet.
JP10007156A 1998-01-19 1998-01-19 Manufacture of semiconductor device Pending JPH11204551A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP10007156A JPH11204551A (en) 1998-01-19 1998-01-19 Manufacture of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP10007156A JPH11204551A (en) 1998-01-19 1998-01-19 Manufacture of semiconductor device

Publications (1)

Publication Number Publication Date
JPH11204551A true JPH11204551A (en) 1999-07-30

Family

ID=11658218

Family Applications (1)

Application Number Title Priority Date Filing Date
JP10007156A Pending JPH11204551A (en) 1998-01-19 1998-01-19 Manufacture of semiconductor device

Country Status (1)

Country Link
JP (1) JPH11204551A (en)

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