JPH10144878A - Semiconductor integrated circuit device and fabrication thereof - Google Patents

Abstract

PROBLEM TO BE SOLVED: To enhance the reliability while decreasing the resistance of interconnection and the unit memory cell area. SOLUTION: A contact plug (10a, 13a, 16a, 19a) has elliptical plan view having long axes in the direction causing no interference with adjacent lines (11, 14, 17). A plurality of such contact plugs are then stacked sequentially crosswise while intersecting the long axes perpendicularly thus interconnecting them directly. According to the structure, contact holes are filled easily and patterned finely and since the effect of positional shift is suppressed at the time of matching the mask, fabrication of multilayer interconnection can be facilitated while enhancing the reliability and the performance. Furthermore, fabrication yield of the hip per wafer is increased and the fabrication cost is reduced.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a semiconductor integrated circuit device and a method of manufacturing the same, and more particularly, to a semiconductor integrated circuit device having extremely fine multilayer wiring and a method of manufacturing the same.

[0002]

2. Description of the Related Art In order to improve the degree of integration of a semiconductor integrated circuit device, it is important to make a multilayer wiring finer. In order to miniaturize multilayer wiring, not only reducing the line width of wiring but also, for example, DRAM (Dynamic Random Acceleration)
In the memory cell array portion of the ss memory, it is necessary to improve the connection structure of the wiring layer connection plug for connecting the wiring layers or the wiring layer and a predetermined portion of the semiconductor substrate surface to each other. As such a connection plug, Japanese Patent Laid-Open Publication No.
In No. 0447, the side surface is not vertical to connect the diffusion layer of the MOS transistor and the capacitor lower electrode.
It has been proposed to use a structure in which two inclined connection plugs are directly electrically connected.

[0003]

In the above prior art, since the side surfaces of the connection plug are inclined, the size of the upper surface and the lower surface of the connection plug parallel to the surface of the underlying substrate are not the same, and the size of the upper surface is not equal. Is larger than the size of the lower surface. In the above prior art, the side surface of the connection plug is inclined.
When a contact hole for forming a connection plug is formed in an insulating film by dry etching, if the hole diameter of the contact hole is small, the portion closer to the bottom of the contact hole is more difficult for etching gas to enter, and as a result, the bottom This is because the closer the part is, the smaller the etching amount becomes and the smaller the hole diameter becomes.

When the side surface of the connection plug is inclined as described above, the contact area on the lower surface of the connection plug becomes small, and the wiring resistance including the contact resistance of the connection plug increases. Also, as the cross-sectional area of the upper surface of the connection plug increases, the unit memory cell area of the DRAM increases,
Problems such as a limited degree of freedom in wiring design occur.

In general, when the size of the connection plug is small, it is difficult not only to form a contact hole for the connection plug with high accuracy and precision by photolithography and dry etching, but also in this case. It is difficult to embed a conductive film in a fine contact hole. Therefore, problems such as an increase in wiring resistance including the contact resistance of the connection plug and the occurrence of disconnection occur, and it is difficult to obtain a fine wiring structure having high reliability.

SUMMARY OF THE INVENTION An object of the present invention is to solve the above-mentioned problems of the prior art, and to achieve low resistance and high design freedom without undesired obstacles such as an increase in the unit memory cell area and restrictions on design flexibility. By providing a semiconductor integrated circuit device capable of realizing wiring having high reliability and high reliability, and a method of manufacturing a semiconductor integrated circuit device capable of easily manufacturing such a semiconductor integrated circuit device with high accuracy. is there.

[0007]

According to the present invention, there is provided a semiconductor integrated circuit device, comprising: a base substrate; an interlayer insulating film formed on a surface of the base substrate; A connection plug made of a conductive film,
The planar shape of the connection plug is an elliptical shape.

[0008] That is, in the present invention, the greatest feature is that the planar shape of the connection plug penetrating the interlayer insulating film is elliptical. It is preferable to set the direction so as not to interfere with the adjacent wiring.

As is well known, conventionally, the plane shape is a regular circle.
(Mask pattern is square) connection plugs are generally used, but connection plugs with an elliptical planar shape (mask pattern is rectangular) cannot reduce the electrical contact resistance due to the increase in plane area. Needless to say, as will be described later, since the mask pattern of the connection hole is easily transferred to the resist film, the formation of the connection hole is facilitated. There is a case where multiple connection plugs are formed in a stack.
Compared to a connection plug having a circular planar shape, there is a remarkable advantage that the influence of positional deviation during alignment is small.

[0010] The length of the minor axis of the elliptical shape can be extremely small, and can be reduced to the minimum processing size in the used photo-etching technique. In a normal case, the width of the gate electrode of the MOS transistor formed on the base substrate is equal to this minimum processing size, so that the length of the minor axis of the elliptical shape is substantially equal to the width of the gate electrode. be able to.

The effect of facilitating the transfer of the mask pattern is obtained when the length of the major axis of the elliptical shape is five times or less the resolution wavelength, and the major axis is at least 1.2 times the minor axis. , 2
It is recognized when it is less than double.

It is preferable that the major axis direction of the elliptical shape of the connection plug is the same as the direction of the wiring arranged near the connection plug. It is preferable that the upper surface and the lower surface of the plug are parallel to the surface of the base substrate, and that the side surface of the connection plug is substantially perpendicular to the surface of the base substrate, in view of a required plane area and resistance between the plugs.

The two upper and lower connection plugs respectively formed on the two interlayer insulating films stacked opposite to each other are formed so that the major axes of the elliptical shapes are orthogonal to each other, and are directly electrically connected to each other. It is connected. With this configuration, when a positional shift occurs during mask alignment, the contact area between the upper and lower connection plugs is larger than in the case where the planar shape of both connection plugs is a perfect circle, and the low contact resistance. It is extremely advantageous for

When the semiconductor integrated circuit device of the present invention has a peripheral circuit section (I / O control section and decoder section) and a memory cell array section, the plurality of interlayer insulating films are formed in the memory cell array section. A MOS transistor and a capacitor are formed below and above a plurality of interlayer insulating films, respectively, and a diffusion layer of the MOS transistor is electrically connected to an electrode of the capacitor via the plurality of connection plugs. Can be. This semiconductor integrated circuit device can further include a logic circuit section in addition to the peripheral circuit section and the memory cell array section. In this logic circuit section, extremely miniaturization like the memory cell array section is not possible. Since a large current value is not required, a more preferable result can be obtained if at least two connection plugs adjacent to each other are electrically connected to each other via a wiring or a wiring connection pad.

The same applies to the peripheral circuit portion, and it is preferable that at least two connection plugs adjacent to each other be electrically connected to each other via a wiring or a wiring connection pad.

It is preferable that the material of the connection plug formed in the memory cell array portion and the peripheral circuit portion or in the memory cell array portion and the logic circuit portion is formed of the same conductive film for each layer. If you do this,
The connection plugs for the memory cell array and the peripheral circuit, or the connection plugs for the memory cell array and the logic circuit can be formed simultaneously. As the conductive film, at least one selected from the group consisting of a tungsten film, a tungsten nitride film, a titanium film, a titanium nitride film, an aluminum film, and a copper film can be used.

If the memory cell array is a memory cell array of a DRAM, preferable results can be obtained. DR above
The unit memory cell of the AM memory cell array is one MOS
The memory cell has an area of 8.times.f.times. (F + a) or less (where f is a minimum processing dimension and a is a process margin).

[0018] The memory cell array may be a memory cell array of a ferroelectric memory.

In the memory cell array section, the capacitor can be arranged above the bit line,
Further, the capacitor can be arranged above all the wirings.

The capacitor insulating film of the capacitor may be a well-known capacitor insulating film such as a tantalum oxide film, a PZT (composite oxide of lead, zirconium and titanium) film and a BST (composite oxide of barium, strontium and titanium) film. In the case of the ferroelectric memory, a known ferroelectric film such as a PZT film or a BST film can be used as an insulating film of the ferroelectric capacitor.

When a second insulating film having an etching rate different from that of the interlayer insulating film is disposed below the wiring, the second insulating film functions as an etching stopper film, as will be described later. Insulation between the connection plug penetrating the film and the wiring is performed without any trouble. Further, by arranging a third insulating film having a different etching rate from that of the interlayer insulating film on a side portion of the wiring, insulation between the wiring and a connection plug adjacent to the wiring can be performed without any trouble. Further, by disposing a fourth insulating film having a different etching rate from that of the interlayer insulating film on the wiring, insulation between the wiring and a connection plug adjacent to the wiring can be performed without any trouble. As these second, third and fourth insulating films, silicon nitride films can be used, and favorable results can be obtained.

According to the semiconductor integrated circuit device of the present invention, a step of forming a first interlayer insulating film on a base substrate;
Forming a first connection hole having a planar shape of an elliptical shape, penetrating through the interlayer insulating film, and forming a first connection plug by filling the first connection hole with a conductive film. Forming a first-layer wiring, forming a second interlayer insulating film, and forming a second connection hole penetrating the second interlayer insulating film and having an elliptical planar shape. Forming a second connection plug by filling a conductive film in the second connection hole, and forming the second connection plug in the second connection hole.
Wherein the long axis of the connection hole is formed in a direction orthogonal to the long axis of the first connection hole in a plane parallel to the surface of the base substrate. .

That is, in the method of manufacturing a semiconductor integrated circuit device according to the present invention, after the first connection plug penetrating through the first interlayer insulating film and having an elliptical planar shape is formed,
A second connection plug penetrating the second interlayer insulation film formed on the first interlayer insulation film and having an elliptical planar shape is connected to the long axis of the second connection plug and the first connection plug. The major axis of the connection plug is formed in a direction orthogonal to a plane parallel to the surface of the base substrate.

When the second connection plug is formed, it is inevitable that a positional shift of photoetching occurs.
Since the planar shape of each of the first and second connection plugs is an elliptical shape, as described above, the distance between the first and second connection plugs is smaller than when the planar shape is a perfect circle. The contact area is remarkably large, and the influence of the displacement during the photoetching is much smaller.

If the step of forming a connection plug by filling the connection hole with a conductive film is performed by using a selective CVD method, the deposition of a conductive substance on portions other than the inside of the connection hole can be extremely reduced. Although it is possible and preferable, it is also possible to use a blanket CVD method in which a conductive film is formed on the entire surface.

After the conductive film is filled in the connection hole, the upper portion of the conductive film is polished to remove a portion formed outside the connection hole, and the conductive film is left only in the connection hole. This is preferable for the subsequent steps.

If the second connection hole is formed after forming the second interlayer insulating film on a film having an etching rate lower than that of the second interlayer insulating film, the film having the lower etching rate is formed. Acts as an etching stopper film, so that the margin of etching is increased. If a silicon nitride film is used as a film having a lower etching rate than the second interlayer insulating film, preferable results can be obtained.

The connection plug having an elliptical planar shape according to the present invention has the following advantages at the time of formation as compared with the conventional connection plug having a perfect circular shape. The first advantage is that, when the mask pattern of the connection holes is transferred onto the wafer, the shape of the mask pattern is not a hole pattern but a shape close to a line pattern. What you can do. A second advantage is that, when forming the connection hole, if the plane area of the connection plug is increased, the etching gas can easily enter the bottom of the connection hole, and the connection hole is easily formed. In addition, the side surfaces of the connection plug do not have an inclination, and it is easy to process the connection plug so that the upper surface and the lower surface have the same size. As a third advantage, when the conductive film is buried in the connection hole, the sputtered particles or C
Since VD gas molecules can easily enter the bottom of the connection hole, embedding is also facilitated. Therefore, blanket CVD
Even when the conductive film is buried in the connection hole by the method, a connection plug can be formed without inconvenience such as generation of a cavity or a state. Further, even when the conductive film is embedded in the connection hole by the selective CVD method, the connection plug can be stably formed without inconvenience such as a variation in the grown film thickness of the conductive film. Also, when the CMP method is used at the time of forming the connection plug,
There is no problem that the connection plug is broken or abrasive particles remain in the cavities or holes in the connection plug.

[0029]

DESCRIPTION OF THE PREFERRED EMBODIMENTS In the present invention, the planar shape of a connecting plug is not limited to an elliptical shape and a rectangular shape. For example, as shown in FIG. It is possible to use shapes having different lengths and various shapes obtained by combining these shapes with other shapes. These shapes are collectively referred to herein as elliptical shapes.

If the side surface of each connection plug is substantially perpendicular to the bottom and the size of the top surface is substantially equal to the size of the bottom surface, contact resistance can be prevented by the small bottom surface and the required area by the large top surface. It is preferable because both of them are prevented from increasing.

In the memory cell array section, the connection plugs are directly connected in sequence, while in the peripheral circuit, wires or wiring pads can be interposed between the connection plugs. In this way, the required area of the memory cell array can be reduced and the required current in the peripheral circuit can be secured at the same time.

Examples of the connection plug include tungsten, tungsten nitride, titanium and titanium nitride.
Known metals used as electrodes and connection plugs can be used.

The thickness of each interlayer insulating film is 1.0 μm or less,
If it is 0.3 μm, the aspect ratio is not large,
It is preferable because the formation of the connection hole is easy and there is no fear of generating a pinhole.

[0034]

【Example】

<Embodiment 1> This embodiment is an example in which the present invention is applied to a DRAM semiconductor integrated circuit device, and a 256 Mb DRAM having a unit memory cell size of 0.8 × 0.6 μm is formed.
The minimum processing size was 0.2 μm.

FIG. 1 shows the overall configuration of the DRAM of this embodiment. As is apparent from FIG. 1, the DRAM 1 of the present embodiment
000 denotes a memory cell array unit 1001, an I / O control circuit unit 1002, a column decoder unit 1003, and a row decoder unit 1
004 and an input / output interface unit 1005.

FIG. 2 shows an equivalent circuit for two bits of a memory cell constituting the memory cell array unit 1001. As is apparent from FIG. 2, one memory cell is one MO cell.
It comprises an S-type transistor 2001 and one charge storage capacitor 2002.

FIGS. 3 to 5 are cross-sectional views of main parts of the DRAM. 3A to 5, FIG. 3A and FIG.
5A shows a memory cell array section, and FIG. 3B shows a sectional structure of a peripheral circuit section. 6 to 9 are mask patterns showing a planar arrangement of each layer where connection plugs are respectively formed in the memory cell array section. The cross-sectional structure of the first layer in FIG.
4A is a cross-sectional structure of the first layer in FIG. 4A, the cross-sectional structure of the first layer in FIG. 4A is the cross-sectional structure of the BB ′ part, and the cross-sectional structure of the first layer in FIG. The cross-sectional structures are respectively shown. The same applies to FIGS. 7 and 8, which are mask patterns representing the planar arrangement of the second layer and the third layer having the cross-sectional structures shown in FIGS. 4A and 5A, respectively.

FIG. 6 shows the diffusion layer 3, the gate electrode 4 and the first connection plug 10a, FIG. 7 shows the first layer wiring 11 and the second connection plug 13a, and FIG.
In FIG. 9, the third connection plug 16a and the third layer wiring 1 and the fourth connection plug 19a are shown by solid lines, respectively, and the other parts are shown by broken lines. 6 to 9 show mask patterns, but the mask pattern of the connection plug drawn in a rectangular shape has a rounded corner and a substantially elliptical shape when transferred onto a substrate.

As shown in FIG. 3 to FIG.
In the RAM, a silicon oxide film 2 for element isolation, a diffusion layer 3, a gate electrode 4, and the like are formed on a silicon substrate 1 using a known method. The wirings 11, 14, 17 of the first to third layers, the first to fourth connection plugs 10
a, 10b, 13a, 13b, 16a, 16b, 19
a, 19b and the first to fourth interlayer insulating films 8, 12, 1
A wiring layer composed of 5 and 18 is formed.

In the memory cell array section, the first-layer wiring 11 functions as a bit line disposed orthogonal to the gate electrode 4, and the second-layer wiring 14 is disposed in the same direction as the gate electrode 4. Functions as a sub-word line.
Above these wiring layers, a lower electrode 20, a capacitor insulating film 2
1 and an upper electrode 22 are formed. In the memory cell array portion, in order to connect the diffusion layer 3 and the lower electrode 20, the first to fourth connection plugs 10a, 13a, 16a, and 19a are directly electrically connected to each other without through a wiring or a wiring connection pad. It is connected.

Next, the connection plug having an elliptical planar shape used in the present invention will be described. In the present invention, FIGS.
As shown in FIG. 9, the first to fourth connection plugs 10a, 1
The planar shapes of 3a, 16a, and 19a are elliptical (mask pattern is rectangular), not regular circles (mask pattern is square) conventionally used in general. In this embodiment,
The mask pattern has a long side of 0.45 μm and a short side of 0.3 μm.
The pattern to be transferred on the substrate has a major axis of 0.3 μm (1.5 times the minimum processing size) and a minor axis of 0.2 μm.
m (minimum processing size).

The first connection plug 10a has the long axis in the same direction (x direction) as the gate electrode 4, and the second connection plug 13a has the long axis in the same direction (y direction) as the first layer wiring 11. To avoid interference with adjacent wiring. Further, since the length of the short axis is the minimum processing size as in the conventional case, the unit memory cell area is the same as in the conventional case.

It goes without saying that the electrical contact resistance is reduced by increasing the plane area of such an elliptical connection plug. However, as will be described later, the mask pattern of the connection hole is transferred. This facilitates the formation of the connection hole, and also facilitates the filling of the continuous hole with the conductive film. Therefore, it is effective for reducing the wiring resistance and improving the stability of forming the connection plug. The effect of facilitating the transfer of the mask pattern is obtained when the long axis of the connection plug is 5 times or less the resolution wavelength and when the long axis is 1.2 times or more and 2 times or less the short axis. It was remarkable.

Next, the connection method of each connection plug will be described. As shown in FIGS. 6 to 9, in the memory cell array portion, a first connection plug 10 a and a third connection plug 1
6a has a long axis in the x direction, and the second connection plug 13a and the fourth connection plug 19a have a long axis in the y direction.
Therefore, the first connection plug 10a and the second connection plug 13a, the second connection plug 13a and the third connection plug 16a, the third connection plug 16a and the fourth connection plug 1
9a is arranged in a cross shape with its long axes orthogonal to each other and is directly electrically connected.

When the connection is made in this manner, the margin for aligning the mask is significantly increased as compared with the case where the planar shape of the connection plug is a perfect circle. For example, as shown in FIG. 11, two elliptical connection plugs 10a and 13a having a short axis of 0.2 μm and a long axis of 0.3 μm are designed to be directly electrically connected with the center of gravity coincident. In this case, even if a mask misalignment occurs, the contact area between the two connection plugs is much larger than that of a conventional connection plug having a regular circular planar shape, which is practically sufficient.

As described above, by using the connection plug and the connection method according to the present invention, the planar shape of which is elliptical,
Even when the capacitor is provided above the bit line or all the wiring, the unit memory cell area remains the same as when using the conventional round connection plug, the wiring resistance is reduced, and the diffusion layer and the capacitor lower electrode are connected. Can be connected stably.
By providing a capacitor above the wiring layer, the BST
A high dielectric film such as a film or a PZT film can be stably used as a capacitor insulating film of a capacitor. That is, the capacitor insulating film made of such a high dielectric film has a problem that its characteristics are deteriorated due to heat history after forming the capacitor. In this embodiment, however, the capacitor is formed after forming the wiring layer. Therefore, such a problem of characteristic deterioration is significantly reduced, and the reliability of the capacitor is improved.

Since the same effect can be obtained even if the capacitor of the ferroelectric memory is provided above the wiring layer, the present invention can be effectively applied to the ferroelectric memory. Further, the structure of this embodiment in which the capacitor is provided above the wiring layer has a DR
AM, ferroelectric memory, SRAM, logic LSI,
Furthermore, since a multifunctional LSI (FIG. 12) in which a DRAM and a logic circuit are mixed on the same chip can be formed on the same manufacturing line, the cost can be reduced by standardizing the process.

The elliptical connection plug and the connection method according to the present invention can be applied not only to DRAMs and the like but also to multilayer wiring of logic LSIs, and similarly, the reliability of the wiring is improved. .

In this embodiment, a plurality of connection plugs are directly connected to each other only in the memory cell array section.
In the peripheral circuit section, a plurality of connection plugs were connected to each other via wiring or wiring pads. In other words, a plurality of connection plugs are directly connected to each other only in the memory cell array where the wiring and connection plugs are dense and extremely miniaturization is required, so that the low resistance of the wiring such as the peripheral circuit and the logic circuit is reduced. In parts that are not important and do not require a high degree of miniaturization, a plurality of connection plugs were connected to each other via wiring or wiring pads. As described above, two types of plug connection structures can be simultaneously formed on the same LSI chip as required by fineness and low resistance of wiring. Also in this case, the first connection plugs 10a, 10b, the second connection plugs 13a, 1
3b, the third connection plugs 16a, 16b, and the fourth connection plugs 19a, 19b can be simultaneously formed of the same conductive material common to the memory cell array section and the peripheral circuit section (or logic circuit section), respectively.
The number of required steps can be reduced.

As shown in FIG. 13, the connection plug may be made of, for example, one kind of conductive material selected from the group of conductive materials A, and two kinds of conductive materials selected from the group of conductive materials B and C. It may be made of a material. Further, three or more conductive materials obtained by combining these materials may be used.

Next, the manufacturing process of the DRAM of this embodiment will be described with reference to FIGS. On a p-type (100) silicon substrate 1, a 350-nm-thick device-isolated silicon oxide film 2 and a diffusion layer are formed on a p-type (100) silicon substrate 1 by a known technique such as thermal oxidation, photolithography, dry etching, wet etching, or ion implantation. Region 3, a well layer, a channel layer, and the like were formed.

Next, in order to form the gate electrode 4, a gate oxide film (not shown) having a thickness of 7 nm is formed by a known thermal oxidation method, and then a polysilicon film having a thickness of 70 nm to which phosphorus is added is formed. A tungsten silicide film having a thickness of 120 nm
Each is sequentially formed by a low-pressure CVD method, and further, a silicon oxide film having a thickness of 10 nm and a thickness of 100
The laminated insulating film 5 made of a silicon nitride
They were formed by the D method and the plasma low pressure CVD method, respectively.

The stacked insulating film 5 on the connection region 6 between the stacked film of the polysilicon film and the tungsten silicide film and the first connection plugs 110a and 110b is selectively formed by a known photolithography technique and a dry etching technique. After removal, the surface of the tungsten silicide film was exposed.

Next, the polysilicon film, the tungsten silicide film, the silicon oxide film and the silicon nitride film are patterned into a predetermined shape by a photolithography technique and a dry etching technique to form a gate electrode 4 having a processing length of 0.2 μm. Was formed.

Using the gate electrode 4 as a mask, an impurity ion having a conductivity type opposite to that of the silicon substrate is implanted, and then a silicon nitride film having a thickness of 80 nm is formed. To form a gate electrode side wall spacer 7 having a spacer length of 50 nm.
Was formed. Further, after the impurity ions having the opposite conductivity type were ion-implanted again, heat treatment was performed to form the diffusion layer 3.

Next, after a BPSG film having a thickness of 700 nm is formed on the entire surface, a heat treatment is performed to reflow the film, and the film is polished by a well-known CMP method so that the film thickness of the element isolation region 2 on the gate electrode 4 is 300 nm. Then, a first interlayer insulating film 8 having a flat upper surface was formed.

By the well-known photolithography technique and dry etching technique, it penetrates the first interlayer insulating film 8 and has a major axis (x direction) of 0.3 μm and a minor axis (y direction) of 0.3 μm. A first connection hole having an elliptical planar shape of 2 μm was formed on the diffusion layer 3 and the gate electrode 4 at the same time.

Next, a titanium film having a thickness of 20 nm and a thickness of 30
After a titanium nitride film having a thickness of 100 nm is formed on the entire surface by a well-known sputtering method, a thickness of 100 nm is formed by a blanket CVD method.
A tungsten film having a thickness of nm was laminated thereon. After that, of these films, portions formed on the first interlayer insulating film 8 are polished and removed by a CMP method, and are left only in the first connection holes. Are simultaneously formed.

Next, a 50-nm-thick tungsten film, a 300-nm-thick aluminum film, and a 50-nm-thick titanium nitride film were sequentially laminated by a well-known sputtering method. These films were patterned by a known photolithography technique and a dry etching technique to form first-layer wirings 11.

At this time, in the memory cell array section (a),
The first wiring layer at the connection between the first connection plug 10a and the second connection plug 13a is removed by etching.
The first connection plug 10a and the second connection plug 13a are directly electrically connected to each other. On the other hand, in the peripheral circuit portion (b), the first connection plug 10b and the second connection plug 13b are connected via a wiring connection pad which is a part of the first wiring layer 11.

After a silicon oxide film is formed on the entire surface by the high-density plasma CVD method and the first layer wiring is buried, the silicon oxide film is polished by the CMP method to form a film on the first layer wiring 11. To a thickness of 200 nm,
A second interlayer insulating film 12 was formed. Next, a 200-nm-thick silicon oxide film was formed over the entire surface by a plasma CVD method using TEOS gas.

After forming a second connection hole penetrating the second interlayer insulating film 12 by a known photolithography technique and a dry etching technique, a 1 μm-thick tungsten film is formed by a well-known selective CVD method. 2 was formed in the connection hole. At this time, the tungsten film overfilled the connection hole in both the memory cell portion and the peripheral circuit portion. Thereafter, the tungsten film overfilled on the second interlayer insulating film 12 and the tungsten nuclei formed on the second interlayer insulating film 12 due to the reduced selectivity are polished and removed by a CMP method to form a contact hole. The tungsten film is left only inside the second connection plug 1
3a and 13b were formed.

The first layer wiring 11 and the second interlayer insulating film 1
Using the same method as that for forming the second and second connection plugs 13a and 13b, the second layer wiring 14, the third interlayer insulating film 1
5, third connection plugs 16a, 16b, third layer wiring 1
7. Fourth interlayer insulating film 18 and fourth connection plug 19
a and 19b were sequentially formed.

Next, a charge storage capacitor was formed. First, a platinum film having a thickness of 100 nm is formed by a well-known sputtering method, and then this is 0.6 × 0.6 by photoetching.
It is processed into a 4 μm electrode shape, and the capacitor lower electrode 20 is formed.
And A capacitor insulating film 21 made of a 100 nm thick BST film and a capacitor upper electrode 22 made of a 100 nm thick platinum film are sequentially laminated thereon. The amount of charge stored per cell of the capacitor thus obtained is 20 fF (femto-Farad), and 25
This was sufficient as the charge storage amount of the 6 Mb DRAM. Further, the platinum film used as the capacitor lower electrode 20 functions as a wiring layer in the peripheral circuit portion, and the degree of freedom in wiring design can be improved. Thus, the structure shown in FIGS.

<Embodiment 2> A second embodiment in which the present invention is applied to a DRAM semiconductor integrated circuit device will be described. This embodiment is an example in which, in addition to a connection plug having an elliptical planar shape and its connection, an insulating film having an etching rate different from that of an interlayer insulating film is provided below the wiring in order to insulate the connection plug from the wiring. In this embodiment, a silicon nitride film is used as the insulating film.

FIGS. 14 to 16 are views showing the sectional structure of the main part of the DRAM formed according to the present embodiment. Also in this embodiment, as in the case of the first embodiment, FIGS. 14A, 15A and 16A show a memory cell array portion, and FIG. 14B shows a peripheral circuit portion. Is shown.

FIGS. 17 to 20 are mask patterns showing a planar arrangement of each layer where connection plugs are formed in the memory cell array portion. FIG.
The cross-sectional structure of the first layer in (a) is the cross-sectional structure of the AA ′ part in FIG. 17, and the cross-sectional structure of the first layer in FIG. 15 (a) is the cross-sectional structure of the BB ′ part in FIG. The cross-sectional structure of the first layer in FIG. 16A shows a cross section taken along the line CC ′ in FIG. 18 to 20 are also similar, each being a mask pattern representing the planar arrangement of the second, third, and fourth layers of the memory cell array section.

In this embodiment, for example, as shown in FIG. 15A, the silicon nitride films 141 and 14 are formed under the first layer wiring 111, the second layer wiring 114 and the third layer wiring 117.
2, 143 are provided respectively. Therefore, between the connection plug and the wiring (for example, the second plug shown in FIG.
Even if a positional shift occurs during mask alignment between the connection plug 113a and the second layer wiring 114), the connection plug and the wiring are formed of a silicon nitride film (the silicon nitride film 114 in the case of FIG. ), It is possible to reduce the unit memory cell area since they are insulated from each other and there is no possibility that they are connected to each other.

As shown in FIGS. 17 to 20, the size of the unit memory cell is 4 × f in the y direction and 2 × (f +
As a), the unit memory cell area was set to 8 × f × (f + a). Here, f represents the minimum processing dimension, and a represents the alignment margin. In this embodiment, f = 0.2 μm and a = 0.04.
μm. Needless to say, in order to realize a fine unit memory cell area as in the present embodiment, the connection plug does not have an inclination, that is, the cross section of the connection plug is equal between the upper surface and the lower surface. Not even. Also,
As in the first embodiment, also in this embodiment, the planar shape of the connection plug is an ellipse, and the connection plugs are arranged such that the major axes of the ellipses are orthogonal to each other and are cross-shaped.
It is electrically connected. Therefore, by using such a connection plug and the above-mentioned stacked structure together with a structure in which a silicon nitride film or the like is provided below the wiring, a fine memory cell with extremely low wiring resistance can be stably formed. .

Next, a method of manufacturing the DRAM according to the present embodiment will be described with reference to FIGS. First, Example 1
Similarly, a silicon oxide film 102 for element isolation, a diffusion layer 103, a gate electrode 104, a first interlayer insulating film 108, first connection plugs 110a,
10b was formed using a known method.

Next, a silicon nitride film 141 is formed, and a portion of the silicon nitride film 141 formed in the peripheral circuit portion is removed using a usual photolithography technique and dry etching technique. Wiring 111
Was formed. In the memory cell array section, the first connection plug 110a and the first layer wiring 111 are insulated from each other by the silicon nitride film 141.

Next, after forming the second interlayer insulating film 112 in the same manner as in the first embodiment, the second connection plug 113 is formed.
Connection holes for forming a and 113b were formed. At this time, the silicon nitride film 141 formed in the memory cell array was used as a dry etching stopper film.

That is, after the second interlayer insulating film 112 made of a silicon oxide film is etched using the silicon nitride film 141 as an etching stopper film to form an opening, the exposed portion of the silicon nitride film 141 is selected. It was etched away. In the case of the first embodiment, when forming the connection hole, the first interlayer insulating film 8 and the first connection plug 10a are over-etched, so that the etching conditions are narrowly limited. Since the silicon nitride film acts as an etching stopper film as described above, such a problem is reduced, and the etching conditions can be made much wider than in the case of the first embodiment.

Subsequently, as in the first embodiment, the second connection plugs 113a and 113b, the second layer wiring 114, the third interlayer insulating film 115, the third connection plugs 116a and 116b,
Third layer wiring 117, fourth interlayer insulating film 118, and fourth
After the connection plugs 119a and 119b were sequentially formed, a capacitor including the capacitor lower electrode 120, the capacitor insulating film 121, and the capacitor upper electrode 122 was formed.
At this time, in the memory cell array portion, similarly to the case where the silicon nitride film 141 is provided under the first layer wiring 114, the silicon nitride film 142 is also formed under the second layer wiring 114.
To provide a second layer wiring 114 and a second connection plug 113
a are insulated from each other by the silicon nitride film 142,
A silicon nitride film 143 was also provided below the third layer wiring 117 to insulate the third layer wiring 117 from the third connection plug 116a. Thus, the structure shown in FIGS. 14 to 16 was obtained.

<Embodiment 3> In the above embodiment 2, an insulating film (silicon nitride film) having an etching rate different from that of the interlayer insulating film.
Is provided only below the wiring, but an insulating film (such as a silicon nitride film) having an etching rate different from that of the interlayer insulating film may be provided not only below the wiring but also above or on the side of the wiring. 21 to 23 show examples in which a silicon nitride film is provided below and on the side of a wiring. As in the first and second embodiments, FIGS. 21 (a), 22 (a) and 23 (a) show the cross-sectional structure of the main part of the memory array section, and FIG. Show. The first layer wiring 111 and the first connection plug 110a are insulated from each other by the silicon nitride film 141 formed below the first layer wiring 111,
The first layer wiring 111 and the second connection plug 113a are insulated from each other by the silicon nitride film 151 formed on the side of the first layer wiring 111. Therefore, the influence of the misalignment of the mask alignment is small, a fine wiring structure is obtained, and the reliability is improved.

FIGS. 24 to 26 show examples in which a silicon nitride film is provided on the lower, side and upper portions of the wiring. in this case,
Silicon nitride film 14 formed below first layer wiring 111
1, the first layer wiring 111 and the first connection plug 11
0a are insulated from each other, and the silicon nitride film 151 formed on the side of the first layer wiring 111 and the first layer wiring 1
11, the silicon nitride film 161 formed on
The first layer wiring 111 and the second connection plug 113a are insulated from each other. Further, the influence of misalignment of the alignment of the mask is small, a fine wiring structure is obtained, and the reliability is improved.

According to this embodiment, the unit memory cell area of the memory cell array section can be further reduced from 8 × f × (f + a), which is extremely useful in practice.

[0078]

As described above, according to the present invention,
Since the connection plug can be formed stably and the wiring resistance including the connection resistance of the connection plug can be reduced, the reliability and performance of the semiconductor integrated circuit device can be improved. Further, since the area of the unit memory cell in the memory cell array section is reduced, the number of chips obtained per wafer increases, and the manufacturing cost of the semiconductor integrated circuit device can be reduced.

[Brief description of the drawings]

FIG. 1 is a diagram showing an overall configuration of a DRAM chip.

FIG. 2 is a diagram showing an equivalent circuit of a memory cell array section of the DRAM;

FIG. 3 is a sectional view of a main part of the DRAM according to the first embodiment of the present invention;

FIG. 4 is a sectional view of a main part of the DRAM according to the first embodiment of the present invention;

FIG. 5 is a sectional view of a main part of the DRAM according to the first embodiment of the present invention;

FIG. 6 is a top view of a memory cell array section of the DRAM according to the first embodiment of the present invention;

FIG. 7 is a top view of a memory cell array section of the DRAM according to the first embodiment of the present invention;

FIG. 8 is a top view of a memory cell array section of the DRAM according to the first embodiment of the present invention;

FIG. 9 is a top view of a memory cell array section of the DRAM according to the first embodiment of the present invention;

FIG. 10 is a diagram showing an example of a planar shape of a connection plug according to the present invention;

FIG. 11 is a view showing a connection structure of a connection plug having an elliptical planar shape according to the present invention;

FIG. 12 is a diagram showing an entire configuration of an LSI chip in which a DRAM and a logic circuit are mounted,

FIG. 13 is a view showing a cross-sectional structure and constituent materials of a connection plug;

FIG. 14 is a sectional view of a main part of a DRAM according to a second embodiment of the present invention;

FIG. 15 is a sectional view of a main part of a DRAM according to a second embodiment of the present invention;

FIG. 16 is a sectional view of a main part of a DRAM according to a second embodiment of the present invention;

FIG. 17 is a top view of a memory cell array portion of a DRAM according to Embodiment 2 of the present invention;

FIG. 18 is a top view of a memory cell array section of a DRAM according to Embodiment 2 of the present invention;

FIG. 19 is a top view of a memory cell array section of a DRAM according to Embodiment 2 of the present invention;

FIG. 20 is a top view of a memory cell array section of a DRAM according to Embodiment 2 of the present invention;

FIG. 21 is a sectional view of a main part of a DRAM according to a third embodiment of the present invention;

FIG. 22 is a sectional view of a main part of a DRAM according to a third embodiment of the present invention;

FIG. 23 is a sectional view of a main part of a DRAM according to a third embodiment of the present invention;

FIG. 24 is a sectional view of a main part of a DRAM according to a third embodiment of the present invention;

FIG. 25 is a sectional view of a main part of a DRAM according to a third embodiment of the present invention;

FIG. 26 is a sectional view of a main part of a DRAM according to Embodiment 3 of the present invention.

[Explanation of symbols]

1, 101: silicon substrate, 2, 102: silicon oxide film for element isolation, 3, 103: diffusion layer, 4, 104: gate electrode, 5, 105: laminated film of silicon oxide film and silicon nitride film, 6, 106 ... Connection region, 7, 107 gate electrode side wall spacer, 8, 108 first interlayer insulating film, 1
0a, 10b, 110a, 110b ... first connection plug, 11, 111 ... first layer wiring, 12, 112 ... second interlayer insulating film, 13a, 13b, 113a, 113b ... second connection plug, 14, 114: second layer wiring, 15, 1
15 ... third interlayer insulating film, 16a, 16b, 116a,
116b: Third connection plug, 17, 117: Third layer wiring, 18, 118: Fourth interlayer insulating film, 19a, 19
b, 119a, 119b... fourth connection plug, 20, 1
Reference numeral 20: capacitor lower electrode, 21, 121: capacitor insulating film, 22, 122: capacitor upper electrode, 141, 14
2,143,151,152,153,161,16
2, 163: silicon nitride film, 1000: DRAM chip, 1101: mixed chip of DRAM and logic circuit,
1001, 1101 ... memory array section, 1002, 1
102: I / O control circuit unit, 1003, 1103: column decoder unit, 1004, 1104: row decoder unit, 100
5, 1105: input / output interface unit, 1106: logic circuit, 2001: MOS transistor, 200
2 ... Charge storage capacitor.

 ──────────────────────────────────────────────────続 き Continuing on the front page (72) Inventor Masayoshi Saito 5-2-1, Josuihonmachi, Kodaira-shi, Tokyo Inside the Semiconductor Division, Hitachi, Ltd. Gochome No. 20, No. 1 Semiconductor Division, Hitachi, Ltd.

Claims (30)

[Claims] A connection plug comprising an underlying substrate, an interlayer insulating film formed on a surface of the underlying substrate, and a conductive film penetrating the interlayer insulating film, wherein the planar shape of the connecting plug is elliptical. A semiconductor integrated circuit device having a mold shape. 2. The semiconductor integrated circuit according to claim 1, wherein the length of the minor axis of the elliptical shape is substantially equal to the width of the gate electrode of the MOS transistor formed on the base substrate. Circuit device. 3. The elliptical shape according to claim 1, wherein the length of the major axis is not more than five times the resolution wavelength.
3. The semiconductor integrated circuit device according to 1. 4. The method according to claim 1, wherein the length of the major axis of the elliptical shape is at least 1.2 times and at most twice the length of the minor axis. Semiconductor integrated circuit device. 5. The semiconductor integrated circuit according to claim 1, wherein a major axis direction of the elliptical shape is the same as a direction of a wiring disposed near the connection plug. Circuit device. 6. The connection plug according to claim 1, wherein an upper surface and a lower surface of said connection plug are parallel to a surface of said base substrate, and side surfaces of said connection plug are substantially perpendicular to a surface of said base substrate. 6. The semiconductor integrated circuit device according to any one of 5. 7. A plurality of said interlayer insulating films are laminated on said base substrate, and said connection plugs formed on said adjacent interlayer insulating films facing each other are connected to said major axis of said elliptical shape. 2. The semiconductor integrated circuit device according to claim 1, wherein the semiconductor integrated circuit devices are formed in directions orthogonal to each other and are directly electrically connected to each other. 8. A memory cell array section comprising a peripheral circuit section having an I / O control circuit section and a decoder section and a memory cell array section, wherein an MO formed under the plurality of interlayer insulating films of the memory cell array section.
8. The device according to claim 7, wherein the diffusion layer of the S transistor is electrically connected to the electrode of the capacitor formed on the plurality of interlayer insulating films via the plurality of connection plugs. Semiconductor integrated circuit device. 9. The semiconductor integrated circuit device according to claim 8, further comprising a logic circuit unit. 10. The logic circuit section according to claim 9, wherein at least two adjacent connection plugs are electrically connected to each other via a wiring or a wiring connection pad. Semiconductor integrated circuit device. 11. The semiconductor according to claim 8, wherein in the peripheral circuit portion, at least two adjacent connection plugs are electrically connected to each other via a wiring or a wiring connection pad. Integrated circuit device. 12. The memory cell array section and a peripheral circuit section,
12. The semiconductor integrated circuit device according to claim 8, wherein the connection plugs formed in the memory cell array section and the logic circuit section are made of the same conductive material for each layer. 13. The conductive film according to claim 1, wherein the conductive film is at least one selected from the group consisting of a tungsten film, a tungsten nitride film, a titanium film, a titanium nitride film, an aluminum film, and a copper film.
13. The semiconductor integrated circuit device according to claim 1, wherein the device is a seed. 14. The memory cell array according to claim 8, wherein said memory cell array is a DRAM memory cell array.
3. The semiconductor integrated circuit device according to 1. 15. A unit memory cell of the DRAM memory cell array includes one MOS transistor and one capacitor, and the area of the memory cell is 8 × f × (f +
a) or less (however, f is the minimum processing dimension, a is the process margin)
The semiconductor integrated circuit device according to claim 14, wherein: 16. The semiconductor integrated circuit device according to claim 8, wherein said memory cell array is a memory cell array of a ferroelectric memory. 17. The semiconductor integrated circuit device according to claim 8, wherein said capacitor is disposed above a bit line in said memory cell array section. 18. The semiconductor integrated circuit device according to claim 8, wherein in the memory cell array section, the capacitor is arranged above all wirings. 19. The capacitor according to claim 8, wherein the capacitance insulating film of the capacitor is a film selected from the group consisting of a tantalum oxide film, a PZT film, and a BST film.
19. The semiconductor integrated circuit device according to any one of 7 and 18. 20. The semiconductor integrated circuit device according to claim 16, wherein the insulating film of the ferroelectric capacitor included in the ferroelectric memory is selected from the group consisting of a PZT film and a BST film. 21. The semiconductor according to claim 1, wherein a second insulating film having a different etching rate from the interlayer insulating film is disposed under the wiring. Integrated circuit device. 22. The method according to claim 1, wherein a third insulating film having an etching rate different from that of the interlayer insulating film is arranged on a side portion of the wiring. Semiconductor integrated circuit device. 23. The semiconductor integrated circuit according to claim 1, wherein a fourth insulating film having a different etching rate from said interlayer insulating film is disposed on said wiring. apparatus. 24. The semiconductor device according to claim 21, wherein said second, third and fourth insulating films are silicon nitride films.
3. The semiconductor integrated circuit device according to any one of 3. 25. A step of forming a first interlayer insulating film on a base substrate, and a step of forming a first connection hole penetrating through the first interlayer insulating film and having an elliptical planar shape. Forming a first connection plug by filling the first connection hole with a conductive film; forming a first-layer wiring;
Forming an interlayer insulating film, forming a second connection hole penetrating the second interlayer insulating film and having an elliptical planar shape, and forming a conductive film in the second connection hole. Forming a second connection plug by filling the first connection hole with the long axis of the second connection hole and the long axis of the first connection hole. A semiconductor integrated circuit device formed in a direction orthogonal to a plane parallel to the semiconductor device. 26. The method according to claim 25, wherein the step of filling the contact hole with a conductive film is performed by using a selective CVD method. 27. The method according to claim 25, wherein the step of filling the contact hole with a conductive film is performed by using a blanket CVD method. 28. The method according to claim 28, wherein after the step of filling the connection hole with the conductive film, a step of polishing the conductive film to remove a portion formed outside the connection hole is performed. 28. The method of manufacturing a semiconductor integrated circuit device according to any one of 25 to 27. 29. The step of forming a second connection hole is performed after forming the second interlayer insulating film on a film having an etching rate lower than that of the second interlayer insulating film. 29. The method of manufacturing a semiconductor integrated circuit device according to claim 25, wherein: 30. The method according to claim 29, wherein the film having an etching rate lower than that of the second interlayer insulating film is a silicon nitride film.