JPH0369070A - Digital data recording and reproducing device - Google Patents

Abstract

PURPOSE:To promote the performance of correcting a code error by recording an odd number of times >=3 an optional upper-order bit data of a digital data from a data conversion circuit at the time of recording the data and performing a majority decision by a majority decision circuit at the time of reproducing. CONSTITUTION:The data conversion circuit 7 is provided prior to a coding circuit 3 while the majority decision circuit 8 is provided posterior to a decoding circuit 5. Then, at the time of recording the data, an optional upper-order bit data of the digital data is recorded an odd number of times >=3 by the data conversion circuit 7. And, at the time of reproducing the data, the majority decision is performed by the majority decision circuit 8, and its resultant value is outputted as the upper-order bit data of this digital data. By this method, while a plural bit constitutive digital data, e.g. a TV picture data of 30 picture/ sec is recorded in real time, the performance of correcting a bit error of the upper-order bit of this data is promoted.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a digital data recording and reproducing device, and in particular to a DFA (Digital Fluoroscope) device.
The present invention relates to a digital data recording and reproducing device suitable for a digital VTR for recording images used in an ic angio-grapy device.

The case where the present invention is applied to a digital VTR will be described below.

[Conventional technology]

In recent years, with the advancement of digital technology, some magnetic recording and reproducing devices that can digitally record television signals have begun to appear. An example of this is a digital VTR (
RL/Experiment of digital recording using 2-inch metal tape, Journal of the Television Society Vofi 1.39. &2,
(see 1985).

This type of equipment digitally records standard TV signals in real time, so the recording rate is extremely high, 80 to 100 Mbit/s, and high-density recording is required, so corrections for bit errors due to tape dropouts, etc. It has a function.

However, since the recording density is high, even if errors are corrected, the error rate is about 10-8 (errors cannot be corrected at a rate of 1 bit in 10' bits).

Also, as described in JP-A-63-152288.

There is a method of improving the error rate by recording a plurality of identical images and performing a majority decision between identical bits of each image during playback.

[Problem to be solved by the invention]

In the above conventional technology, the error rate for TV images (moving pictures) is 10-8, which is equivalent for each bit of image data. Therefore, when a bit error occurs in the upper bits of one image data, the image quality deteriorates significantly, whereas the lower bits are not affected much. In other words, errors in the upper bits of image data must be strongly corrected. However, in the prior art, no countermeasures were taken, and large errors often occurred in image data.

In addition, with the above method of recording multiple images of the same image and performing a majority vote between the same bits of each image during playback, when recording multiple images of TV images at 30 images/second, it is difficult to record multiple images in real time. requires a higher recording rate, and the current recording rate has problems such as not being able to record in real time, or requiring an extremely complex configuration, which significantly increases manufacturing costs.

An object of the present invention is to improve the bit error correction capability of the upper bits of the data while recording multi-bit digital data, for example, TV image data at about 30 images/second, in real time without increasing costs. An object of the present invention is to provide a digital data recording and reproducing device.

(Means for Solving the Problem) The above object is to provide a coding circuit that adds a correction code to multi-bit digital data to correct code errors during recording during reproduction, and a code circuit that adds the correction code to digital data having a plurality of bits. A digital device comprising: a recording and reproducing unit for recording the digital data on a recording medium and reproducing the recorded digital data; and a decoding circuit for correcting code errors in the digital data read from the recording and reproducing unit. In the data recording and reproducing device, a data conversion circuit is provided before the encoder circuit, and a majority circuit is provided after the decoding circuit, and when recording data, the data conversion circuit converts arbitrary high-order bit data of the digital data. This is achieved by recording an odd number of times, three or more times, and performing a majority decision using the majority decision circuit when reproducing the data, and outputting the resulting value as the upper bit data of the digital data.

[Effect]

As an example, Table 1 below shows an explanation of the operation when the error rate of digital data with a plurality of bits, here one digital TV image data, is 10'''8.For lower bit data, the error rate is 10- 6, there is no particular difference from the conventional technology, and here we will focus on any one bit in the upper bit data recorded three or more odd times.In this example, the majority decision in the case of three recordings will be considered. shows.

If the first time's data is correct, it is 0, if it is wrong, it is ``×'', and if the second and third times are entered, eight combinations of data can be considered. The result of the majority vote is the correctness of the output, and the correct case is shown as 0, and the incorrect case is shown as
x), (xxO).

(There are four possibilities: X X can.

Table 1 [Examples] The present invention will be described in detail below with reference to the drawings. FIG. 1 is a block diagram showing an embodiment of a digital data recording/reproducing apparatus according to the present invention, here a digital data VTR. This digital VTRI records and reproduces digital data obtained by digitizing a video signal or digital data from a digital system (not shown), and includes an A/D converter 2, a data conversion circuit 7, a code path 3, Recording/reproducing section 4, decoding circuit 5, and majority circuit 8
and a D/A converter 6.

The A/D converter 2 digitizes a video signal obtained from a television system (not shown). Further, the encoding circuit 3 adds a correction code to the digital data output from the A/D converter 2 or the digital data sent from a digital system (not shown) to correct code errors during reproduction. be.

The recording/reproducing section 4 records digital data to which a correction code has been added by the encoding circuit 3 onto a recording medium such as a magnetic tape, and reproduces the recorded digital data. The decoding circuit 5 corrects code errors (bit errors) in the digital data read from the recording/reproducing section 4 using the correction code added by the encoding circuit 3.

The D/A converter 6 converts the digital data whose code errors have been corrected by the decoding circuit 5 into a video signal and sends it to a television system (not shown).

Note that the digital data whose code errors have been corrected by the decoding circuit 5 can be directly sent to a digital system (not shown) without going through the D/A converter 6.

Here, in the present invention, a data conversion circuit 7 is provided before the encoding circuit 3, and a majority circuit 8 is provided after the decoding circuit 5.

The data conversion circuit 7 outputs upper bit data a plurality of times when recording digital data, and is configured as shown in FIG. 2, for example. In FIG. 2, memories 71 and 72 record and hold digital data output from the A/D converter 2 or digital data sent from a digital system (not shown); In this case, the other one performs reading. The data conversion unit 73 includes the memory 7
The upper bit data of the data read from 1.72 is output multiple times. The controller 74 controls the memories 71 and 72 and the data converter 73.

In this figure, the digital data output from the A/D converter 2 or the digital data transferred from a digital system (not shown) is transferred to a memory that is in write mode at that time, for example, the memory 71, for one image, and for the entire image. Bit memory, retained. When the next image data is written to the memory 72, the memory 72 simultaneously writes the next image data to the memory 72.
1 becomes the read mode, and the held data is transferred to the data conversion section 73. Similarly, the data stored and held in the memory 72 is also transferred to the data converter 73 at the same time as the memory 71 enters the write mode, and thereafter, by repeating this process alternately, image data is successively transferred to the data converter. Transfer to 73.

The data converter 73 converts the data structure of the data transferred from the memories 71 and 72 in order to record the upper bits a plurality of times.

FIG. 3 shows an example of data conversion when the most significant bit (1 bit) data is recorded three times for each pixel of 8-bit data. Here, among the image data transferred to the data conversion section 73, first four pixel data a, b, c are
, d (IN side), where ao is the 1st bit data (lowest bit data) of pixel a.Similarly, al is the 2nd bit data of pixel a, and a2 is the data of the 2nd bit of pixel a. The 3rd bit, a3, is the 4th bit of pixel a, a4 is the 5th bit of pixel a, and a5 is the 6th bit of pixel a, a.
6 indicates the data of the 7th bit of pixel a, and the data b, c, and d are also the same each time.

Then, the most significant bit data a7 . of each pixel data a, b, Q, d. b7. a7. Combine two d7s,
The data is structured as 8-bit data and output as pixel data of the fifth pixel (OUT side). At this time, there is a waiting time for one pixel on the IN side. Thereafter, the above operation is repeated to output the digital data to the code circuit 3 while adding the most significant bit data twice each time. All data conversion is completed while data for one image is written into the memories 71 and 72. These operations can be performed collectively under the control of the controller 74.

The majority decision circuit 8 makes a majority decision on the upper bit data recorded multiple times among the digital data whose code errors have been corrected in the decoding circuit 5, and an example of its configuration is shown in FIG. Now, regarding 1 pixel 8-bit data, the most significant bit data a7. b7,07. d7 to 3
This shows a majority circuit 8 for recording and reproducing data once at a time.
latch circuits 81 to 84 that capture and output the most significant bit data a7. b7. a7. The fifth pixel data composed of d7 is captured, and each of the four pixel data a.

Inverse conversion circuit 85 that returns the most significant bit data of b, c, and d
and a selector 86 that selects and outputs one of the outputs from the latch circuits 81 to 84, and the most significant bit data of the output data from the selector 86 and the most significant bit data from the inverse conversion circuit 85. A majority decision section 87 that makes a majority decision on bit data, and a controller 88 that controls the operations of the latch circuits 81 to 84, the inverse conversion circuit 85, and the selector 86.
It consists of

Here, the operation of the majority circuit 8 in FIG. 4 will be explained with reference to FIG. That is, among the digital data 90 whose code errors have been corrected in the decoding circuit 5 and transferred to the majority circuit 8, the 5 bits consisting of the most significant bit data are
Let the data of the pixel be e, and let the data of the four pixels that form the basis thereof be at be atd. The latch circuit 81 has four
Pixel data.

Capture the first pixel data a of b, c, d and output 9
The latch circuit 82 outputs 8-bit data ao''a7 of pixel a to pixel a.

Capture the second pixel data b of b, c, d, and output 9
The latch circuit 83 outputs 8-bit data of pixel BO"b7 to 2. The latch circuit 83 outputs 8-bit data of 4 pixels.

Capture the third pixel data C of b, c, d and output 9
3, 8-bit data CO to C7 of pixel C is output. The latch circuit 84 has four pixel data rows.

Capture the data d of the fourth pixel of b, c, d and output 9
The inverse conversion circuit 85 outputs 8-bit data do''dy of pixel d to pixels a, b, and c.

d most significant bit data a7. b7. a7. At the same time as capturing the fifth pixel data e composed of cly.

Inverse conversion is performed and the most significant bit data a7. b7. Return to 2 data each of a7°d7 and send a7. to the output 95. b7゜a
7. Each two data are output simultaneously in the order of d7. On the other hand, when the inverse conversion circuit output 95 is a7, the selector 86 selects the latch circuit output 91 and outputs the 8-bit data ao""'a7 of pixel a to the selector output 96. , c, and d.

When the most significant bit 2 data of pixel a is output from the inverse conversion circuit 85, the selector output 96 outputs the 8 most significant bit data of pixel a.
Bit data aO"a7 is output, of which the most significant bit data is transferred to the majority decision section 87,
A majority decision is made on the most significant bit data at 2 data of pixel a transferred from the inverse conversion circuit 85 and 3 data. The data resulting from the majority decision is output from the majority decision section 87, and together with the lower bit data of the selector output 96, the data is outputted from the majority decision section 87.
/A converter 6. Alternatively, the signal can be directly output to a digital system (not shown) without going through the D/A converter 6. Here, if the majority decision processing time in the majority decision unit 87 cannot be considered to be approximately O, a delay circuit (not shown) is provided in the selector 86 to delay the lower bit data so that it is not connected to the most significant bit data. It is possible to eliminate time lag.

The controller 88 controls each circuit to accurately perform the operations described above.

In this way, a majority vote is made on the upper bit data for each image and each pixel, but it is arbitrarily decided how many upper bits to perform the majority vote on. This is not limited to the case where majority voting is performed on 1-bit data.

Furthermore, the applicable data is not limited to image data; for example, for digital data attached to the image data, the upper bit data is recorded multiple times for each image,
It is also possible to improve code error correction ability by performing majority voting to obtain upper bit data.

According to the present invention, it is possible to improve the bit error correction ability of the upper bits of the data while recording multi-bit digital data, for example, TV image data at about 30 images/second, in real time without increasing costs. There is an effect.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing one embodiment of the device of the present invention, and FIG.
The figure is a block diagram showing a configuration example of the data exchange circuit in Figure 1, Figure 3 is an explanatory diagram of data conversion when the most significant bit data is recorded three times for each pixel of 8-bit data, and Figure 4 is A block diagram showing an example of the configuration of the majority circuit shown in FIG. I, and FIG. 5 are diagrams explaining the operation of the majority circuit shown in FIG. 1...Digital VTR12...A/D converter, 3
... code circuit, 4 ... recording/reproducing section, 5 ... decoding circuit, 6 ... D/A converter, 7 ... data conversion circuit,
71.72...Memory, 73...Data converter, 7
4.88...Controller, 8...Majority circuit, 8
1 to 84...Latch circuit, 85...Inverse conversion circuit, 8
6...Selector, 87...Majority decision unit, a (ao=a
7) ~d (do-d7) One pixel data (image data). Atsushi? Illustrated figure 1 UT

Claims (1)

[Claims] 1. A coding circuit that adds a correction code to digital data having a plurality of bits to correct code errors during recording during reproduction; and recording the digital data to which the correction code has been added onto a recording medium; A digital data recording/reproducing apparatus comprising: a recording/reproducing section for reproducing the recorded digital data; and a decoding circuit for correcting code errors in the digital data read from the recording/reproducing section; A data conversion circuit is provided in the , and a majority decision circuit is provided at the subsequent stage of the decoding circuit, and during data recording, the data conversion circuit records arbitrary high-order bit data of the digital data an odd number of times of three or more times, and when reproducing the data, . A digital data recording and reproducing apparatus, characterized in that the majority decision circuit performs a majority decision and outputs the resultant value as upper bit data of the digital data.