JPH03127248A - Composite computer system - Google Patents

Abstract

PURPOSE:To transmit and receive data at a high speed even in a loose-coupled composite computer system by providing the memory devices for each computer to which the corresponding computer can have a direct reference and securing the same contents among those memory devices. CONSTITUTION:The write information received from a transmission part 22 of a multi-linkage memory device MLM 20-i is transferred in broadcast to all MLM 20-1 to 20-n (incl. MLM 20-i) contained in a composite computer system via an optical star coupler 30-i and written into the same addresses of the MLMs of another computer. Thus the same contents are secured among the MLM 20-1 to 20-n of the computers 10-1 to 10-n respectively. Each computer can share the data on the MLMs of another computer via its own MLMs. In such a constitution, the data can be transmitted and received at a high speed among computers even in a loose-coupled composite computer system.

Description

DETAILED DESCRIPTION OF THE INVENTION [Object of the Invention] (Industrial Application Field) The present invention relates to a compound computer system in which a plurality of computers are loosely coupled to each other.

(Prior Art) A compound computer system configured by interconnecting multiple computers (computer system) is a so-called shared memory type tightly coupled compound computer system that shares one memory,
It is represented by a loosely coupled compound computer system using a LAN (Local Area Network). Tightly coupled compound computer systems have the advantage of being able to send and receive data at high speed, but because of their coupling method, it is difficult to geographically distribute or logically separate each computer, and it is difficult to add more computers. Furthermore, since the shared part is the core of the system, a failure in the shared part affects the entire system. On the other hand, a loosely coupled compound computer system using a LAN has the advantage of being able to easily distribute and separate each computer, and even add more computers. Because of this, there is a problem with high speed.

By the way, in a normal computer system equipped with a main memory device, a failure (
To prevent reading incorrect data from the device due to memory errors), an error detection and correction circuit (EDAC) is installed.
) is provided. When writing data to the main memory, this error detection/correction circuit generates redundant bits (check pits) for memory error detection/correction (ECC') for the write data, and writes the data along with the write data to the main memory. written to the device. When data is read from the main memory, the error detection/correction circuit checks whether the data read from the main memory is correct or not based on the check pit of the data. If it is a correctable bit error, correction is performed and correct read data is returned to the request source. On the other hand, in communication, in addition to the memory error detection/correction method of the main storage device, redundant bits such as a CRC code dedicated to transmission are generally used to detect errors in the transmission path (transmission system). For this reason, in a loosely coupled compound computer system, in addition to the circuit for detecting and correcting memory errors in the main memory, a dedicated circuit for detecting errors in data transmission between computers is installed inside each computer. Error detection was carried out for access by a memory error detection/correction circuit, and for data transmission between computers between the transmitter and the receiver by an error detection circuit dedicated to data transmission. However, in such a conventional loosely coupled compound computer system, error detection methods are different for memory access and data transmission, so there is a risk that error detection at the boundary may be missed.

(Question WJ to be solved by the invention) As mentioned above, in the case of a conventional compound computer system, which is a shared memory type tightly coupled compound computer system, it is difficult to decentralize and separate each computer, and to easily add more computers. Furthermore, there is a problem in the fault tolerance of the system against failures in the shared memory part, and in the case of loosely coupled compound computer systems using LAN, there is a problem in the high speed of data transmission and reception.

In addition, in a loosely coupled compound computer system, the error detection method is different between the memory access system and the data transmission system, so there is a risk that errors may be missed in the boundary between them.This invention was made in consideration of the above circumstances. The purpose of this is to provide a memory device for each computer that can be directly referenced from the corresponding computer, and by configuring the contents of each memory device to be the same, each computer can share data through its own memory device. , it is possible to decentralize and separate each computer while taking advantage of the high speed of tightly coupled data transmission and reception, and it is easy to add more computers, and failures in shared parts do not affect the entire system. The purpose of the present invention is to provide a loosely coupled composite computer system that is easy to use.

Another object of the present invention is to provide a loosely coupled complex computer system that can detect and correct errors without omission by using the same error detection and correction methods in the memory access system and data transmission system and using the same redundant bits. Our goal is to provide the following.

[Structure of the Invention] (Means for Solving the Problems) This invention provides that each of a plurality of computers constituting a compound computer system has its own writable area that can be written to by a daily computer, and other computers in the system can write to it. A storage means for sharing data with a computer, detects and corrects errors in data read from this storage means, and is a target when executing a write request from a computer to a writable area of this storage means. Write address error detection/
a first error detection/correction means that generates a first redundant bit for correction and a second redundant bit for error detection/correction of write data; A memory having a transmission means for transmitting write information including redundant bits, the write data, and a second redundant bit to the outside, and a second error detection/correction means for detecting and correcting errors in the information transmitted from the outside. In addition to adding a device (MLM), a coupling means corresponds one-to-one to the memory device of each of the above-mentioned computers, and is a coupling means for connecting the transmitting means of the corresponding memory device and the memory device of each other computer. When a write request is made from the computer, write information including write data to be written to the storage means of the own memory device is transmitted from the transmitting means of the own memory device to the other device via the coupling means. Commonly transferred to the memory device of each computer,
The second error detection/correction means of each memory device at the transfer destination detects an error in the write address and write data in the transferred write information based on the first and second redundant bits in the same information. The present invention is characterized in that a detection/correction process is performed, and the write address and write data after the error detection/correction process are used to write data into the storage means of the memory device of the transfer destination.

(Function) According to the above configuration, when a computer constituting a compound computer system writes to a memory device (own memory device) attached to the same computer, the same write data, its address, and the same data are written. Also, write information including redundant bits (check bits) for memory error detection and correction (ECC) generated by the first error detection and correction means corresponding to the address is transmitted from the transmission means of the own memory device via the coupling means. The data is commonly transferred to the memory devices of other computers in the system, that is, broadcast transfer is performed. In this way, when the above write information is transferred to the memory device of each computer, each memory device performs error detection/correction processing for each write data and its address in the transferred write information using the same information. The second error detection/correction means performs the error detection/correction based on the corresponding redundant bits in the error detection/correction means. And error detection/
According to the write information for which the correction process has been completed (write information without errors or error-corrected write information), the write data in the same information is written to the storage means in the own memory device specified by the address in the information. An action is taken to insert the image. The writing position of this storage means is the same as the writing position of the same data in the storage means in the memory device of the computer from which the write data is transferred, and thus the memory device of all computers in the system (storage means possessed by it) The memory contents of the two are made to match. That is, although the memory device of each computer is an independent memory device, it is equivalent to a shared memory shared by each computer, and each computer shares the same data using this memory device (its own memory device).

It also detects memory errors in the storage means of the memory device,
In the case of a correctable error, the redundant bits generated by the first error detection/correction means that perform error correction are used as redundant bits for error detection/correction in the transmission system. Since error detection and correction are performed when writing to the storage means, error detection without omission is possible.

(Embodiment) FIG. 1 shows a block configuration of a loosely coupled compound computer system according to an embodiment of the present invention. In the same figure, 10
-1. ...1G-1, ...10-n are main storage devices (
(hereinafter referred to as MEM) 11.

In addition to MEMII, the computers 10-1 to 10-n are arithmetic control units (arithmetic control processors) that form the core of the computer.
12, a distributed input/output II control processor (not shown) that operates in parallel with this arithmetic control unit 12 and specializes in input/output processing, and a system bus 13 to which these devices are connected.
have. 20-1. ...20-1. ...20
-n is computer 10-1. ...10-1. ...10-
The same computer 10-1. ...1
0-1. ...l This is a multi-linkage memory device (hereinafter referred to as MLM) added to O-n.

The MLM 20-1 includes a storage device 21 having the same capacity as, for example, MEMII, for sharing data with other computers in the system shown in FIG. At the time of execution, the storage device 21
A transmitter 22 for externally transmitting write information including write data (word data in this case) to be written to the computer 10-1-10-n, and an M
The corresponding M
It has receiving sections 23-1 to 23-n that receive information optically transmitted from M 20-1 to 20-ports (transmitting section 22 therein). The transmitter 22 has a parallel/serial conversion function that converts parallel transmission information into serial transmission information, and the reception units 23-1 to 23-n have a serial/parallel conversion function that converts serial reception information into parallel reception information. It has a conversion function.

The MLM 20-1 also includes a storage device 21, a transmitter 22, and a receiver 23-1 to 23-2 in the MLM 20-1.
It has a control unit 24 that controls 3-n by, for example, firmware. This control unit 24 controls the own M L M 20-1
Error detection of data read from the storage device 21 in the
In addition to making corrections, the date calculator 10 for the storage device 21
When executing a write request from -1, a check bit (ECC1) for ECC (error detection/correction) and write data (ECC1) for the target write address (A) are executed.
It includes an error detection/correction circuit (hereinafter referred to as EDAC) that generates an ECC check bit (ECC2) for D).

MLM 20-1 further includes receiving section 23-1.・2
3-1. EDA C2B-1, -28-, which detects and corrects errors in the received information received by -23-n.
1,-28-n. Excluding MLM 20-1 < MLM 20-1 to 20-n also MLM20-
It has the same basic configuration as 1.

30-1. -30-1. -30-n is MLM20-
1.・20-1°...This is an optical star coupler provided corresponding to 20-n. Hikari Star Kabra 30-j
(j is l,...i,...n) is the corresponding M L M
20-j and the MLM 20-j including the transmitter 22 and this MLM 20-j.
It is used for radially 1:n unidirectional coupling with each receiving section 23-j of L M 20-1 to 20-n. 4
1 is an optical fiber connecting the transmitter 22 of MLM 20-j and optical star coupler 30-j, 42-1 to 42-
, n is optical star coupler 30-j and M L M 20-1
This is an optical fiber that connects the receiving sections 23-j to 20-n.

Figure 2 shows the address space (this is called the system address space) applied to the computer 10-1 in Figure 1 and the MEMI
For explaining the correspondence between the address spaces allocated to I and MLM 20-1, and the address space writable by computer 10-1 (computer #i writable area) allocated to MLM 20-1. It is a diagram. In the figure, 51 is a system address space applied to the computer 10-1. In this embodiment, the system address space 51 is divided into two, an MEM address space 52-0 and an MLM address space 52-1.
The EM address space 52-0 and the MLM address space 52-1 are allocated to (the storage device 21 of) the MLM 20-1, respectively. Address space 52-Q.

52-1 is the memory address (here 32 bits) M
Identified by SB (Most Significant Bit). Here M
SB-0 indicates address space 52-0, MSB-1
The address space 52-1 is shown in FIG. Also M L M
A specific area (specific address space) of a predetermined size in the MLM address space 52-1 allocated to the computer 1
0-1 writable area (computer #i writable area)
It is set in advance as 53-1. The above is the same for the computers 1o-1 to 10-n other than the computer 10-1, and M L M 2 other than M L M 20-1
MLM address space allocated to 0-1 to 20-n (
The specific area 52-1) of a predetermined size is set in advance as a writable area (writable area) by the corresponding computers 1O-1 to 10-n. This calculator l0-1~10-
n (corresponding to M L M 20-1 to 20-++)
The unique writable area is for each M L M 20-1 to 20-2.
Each of 0 to n is independently written to prevent duplication. In this embodiment, computer #i writable area 53-1
A write access request from the computer 10-1 to any other area is treated as an access violation.

Next, the operation of one embodiment of the present invention will be explained.

First, M in response to an access request from the computer 10-1.
The operation of LM 20-1 will be explained with reference to the flowchart in FIG. When attempting to access MEMII or MLM 20-1, the arithmetic control unit 12 in the computer 10-1 sends a control signal indicating a memory address and a read access request onto the system bus 13 in the case of read access. However, in the case of write access, control signals indicating the memory address, write data, and write access request are sent onto the system bus 13. The memory address on this system bus 13 is
If it belongs to the MEM address space 52-O of the system address space 5i shown in the second mother, MEMII is accessed, and if it belongs to the MLM address space 52-1, MLM 20-1 is accessed. That is, the arithmetic control unit 12 converts M L M 20-1 into M
It can be accessed in the same way as EMII.

Now, when a memory access to the MLM address space 52-1 is requested from the arithmetic control unit 12 of the computer l0-1 via the system bus 13, the control unit 24 in the MLM 20-1 It is checked whether the request is a write access request (step Sl). If it is not a write access request, that is, if it is a read access request, the control unit 24 performs read access to the storage device 21 according to the memory address given from the arithmetic control unit 12 via the system bus 13, and data is sent from the storage device 21. and read the ECC check pit of the same data (
Step S2). The data and check bits read from the storage device 21 are supplied to the EDAC 25 in the control section 24. The EDAC 25 detects and corrects errors in the data read from the storage device 21 and check bits. As a result, if there is no error, the read data from the storage device 21 is output, and even if there is an error, if correction is possible, the error-corrected read data is output from the EDC 25, and the control unit 24 outputs the read data from the storage device 21 to the system bus. 13 to the arithmetic and control unit 12.

On the other hand, if the request from the arithmetic control unit 12 is a write access request, the control unit 24 selects the memory address from the arithmetic control unit 12 (preset as an area writable from the computer 10-1). It is checked whether the computer #i belongs to the writable area 58-1 (step 53). If the request is for access outside the computer #i writable area 53-I, the control unit 24 notifies the arithmetic control unit I2 of an access violation without executing write access to the storage device 21 (step S4). . On the other hand, if the request is for access to the computer #i writable area 53-1, the control unit 24 performs write access to the storage device 21 according to the memory address given from the arithmetic control unit L2 (step S5). Here, if it is not a fullword access from a fullword boundary, the control unit 2
4 performs zone control to read a full word from the storage device 21 and replace part of it with write data given from the arithmetic control unit 12, and writes the full word data after this zone control to the same address in the storage device 21. Lead to write
Perform a modify write. At this time, an ECC check pit (ECC2) for the write data (D) is generated in the EDAC 25 and written to the storage device 21 together with the write data (D). Further, in order to generate write information to be described later, an ECC check pit (ECCI) for address (A) is also generated in the EDC 25. Note that the read-modify-write operation accompanied by zone control is commonly performed in MEMII and is well known, so a detailed explanation will be omitted.

Now, when writing to the storage device 21 in step S5, the control unit 24 in the MLM 20-1 selects the address A1EDA indicating the write destination, as shown in FIG.
ECC check bit ECC1 of the same address A generated by C25, write data D, EDAC25
Write information consisting of the ECC check bit ECC2 of the same data D generated by the above and the header section H is generated. This header portion H includes a retransmission notification bit indicating whether or not the transmission of the corresponding write information is retransmission.

The fourth data generated by the control unit 24 in the MLM 20-1
The written information in the format shown in the figure is the same M L M 20-
The signal is output to the transmitter 22 within the transmitter 1.

Upon receiving the write information generated by the control unit 24, the transmitting unit 22 in the MLM 20-1 converts the information into parallel/serial, further converts it into an optical signal, and sends it to the optical fiber 41.
The optical star coupler 30-H is transmitted through the optical star coupler 30-H.

The optical signal (serial write information) sent to the optical star coupler 30-1 is sent to the optical star coupler 30-1 through the optical fiber 4.
2-1 to 42-n, each M L
It is simultaneously transferred to M 20-1 to 20-n. That is, M
The write information sent from the transmitter 22 of the L M 20-1 is sent to all the M L M 20-1 (including the transfer source M L M 20-1) in the multifunction computer system shown in FIG. 1 via the optical star coupler 30-1. Broadcast is transferred to MLM 20-1 to 20-n.

M L M 20-1 via optical star coupler 30-1
M L M broadcasted to ~20-n
The write information from 2O-i (transmitter 22 within) is M L
It is received by each receiving section 23-1 in M 20-1 to 20-n. Receiving section 23-1 in MLM20-1 to 20-n
converts the received write information into an electrical signal, and further performs serial/parallel conversion. This serial/parallel converted write information is passed to the EDC 26-1 provided corresponding to the receiving section 23-1. E D A C
When the 2B-1 receives the write information from the receiving unit 23-■,
Error detection and correction of address A is performed using address A and check bit ECCl in the same information, and write data D and check bit ECC in the same information are
2, errors in the write data D are detected and corrected. That is, each receiving section 23- in MLM 2G-1 to 20-n
The EDC2B-1 corresponding to (2) detects transmission errors in the received write information, and performs correction processing if the errors are correctable. And EDAC2G-i
sends the write information from the receiving unit 23-I when there is no error, and the write information after error correction when the error can be corrected, to the own M L M 20-1 to 20-n.
It is passed to the control unit 24 inside. On the other hand, in the case of an uncorrectable error, the transmission error is the own MLM 20-1 to 20-
The control unit 24 in n is notified.

Now, the control unit 24 in the MLM 20-1 to 20-n controls the EDA corresponding to the receiving unit 23-■ in its own MLM.
The following operations are performed depending on the presence or absence of a transmission error notification from C2G-1. This operation is performed by the transfer source M of the write information.
LM (here M L M 2O-1) and transfer source MLM
(Here, excluding MLM 20-1
M L M2O-1 to 2O-n).

First, M L M 2G, which is the write information transfer source (that is, executed the write access request from the computer 10-1)
The control unit 24 (the validity check unit, not shown) in the MLM 20-1 is not notified of a transmission error by the EDA C 213-i corresponding to the receiving unit 23-1 in the own MLM 20-1. If a transmission error is notified (that is, if the write information received by the receiving unit 23-1 contains an uncorrectable error), the write information is retransmitted. At this time, a predetermined bit (retransmission notification bit) in the header section H of the write information is set, indicating that the data is being retransmitted. In this embodiment, the number of retransmissions is limited to one, and any more than that will be treated as an error by the computer 10.
-1 is notified.

On the other hand, excluding the transfer source M L M20-1 (M L M2
The control unit 24 in O-1 to 20-n transmits a message to the receiving unit 23-ill in the own MLM: If a transmission error is not notified from the corresponding EDA C2G-1, the control unit 24 in the O-1 to 20-n
Based on the write information passed from C2B-1, write access is made to the storage device 21 in the own MLM according to address A in the same information, and write data D and CHI in the same information are accessed.
Writes Sokubi Soto ECC2. As a result, M.L.
Excluding M20-i < M L M 20-1 to 20-n
In response to a write access request from the arithmetic control unit 12 in the computer 10-1, M L M
The same data as the data written to the computer #i writable area 53-1 of 2O-1 (storage device 21 therein) is written to the same address.

On the other hand, the EDAC 26 corresponding to the receiving section 23-1
-1 is notified of a transmission error, the control unit 24
prohibits writing to the storage device 21 within the own MLM. This can prevent incorrect write data from being written to the storage device 21 or write data from being written to an incorrect address in the storage device 21.

By the above operation, excluding M L M 20-1 < ML
M20-1 to 20-n (storage devices 21) include M20-1 to M20-n.
A copy of the contents of the computer #i@include tilt area 53-1 of (the storage device 21 of) L M 2O-1 is placed in the same address space as the area 53-1. For this reason, calculator 1
0-1 to 10-n are the own M L M 20-1
~20-n share the contents of the computer #i write tilt area 53-1 of the MLM 20-1. This means that other M
The same applies to the write tilt range specific to LM. This situation can be seen by three M L M (M L M 20-1.
20-j, 2O-k) are shown in FIG. In addition,
In FIG. 5, 10-j is the computer 10-1-10-n
Among them, a computer different from the computer 10-1, 19- is a computer 10-1.10- among the computers 10-1 to 10-n.
It is a different computer from j. Also, 20-j is M L M
MLM different from MLM 20-1 among 20-1 to 20-n, MLM 20-1 to 20 to 20-
-n, MLM is a different MLM from 20-i and 20-j. Further, 53-j is an area of M L M 20-j that can be written by the computer 10-j (:1 Computer #j
Write tilt area) and 53- are areas of the MLM 20- that can be written by the computer 10-k (write tilt area for computer #).

As shown in the figure, calculators 10-1.10-j, 10-
MLM20-1.20-j, 20-k-specific mutually independent write tilt areas 53-1.53-j, 5
All the contents of 3- will be shared by Nichi Computer's MLM. As is clear, as shown in Figure 1, n computers 1
In a compound computer system configured using computers 0-1 to 10-n, computers 10-1-10-n are
The contents of mutually independent write tilt areas specific to MLM 10-n are all shared by the MLMs 20-1 to 20-n that the MLM 10-n has. Moreover, the computers 10-1 to 10-n are their own M L
Since M 20-1 to 20-n can be accessed via the system bus 13 in the same way as MEMII, data transmission and reception between computers can be performed at high speed similar to shared memory access in a tightly coupled complex computer system. For the same reason, even if any MLM of the computers 10-1-10-n constituting the composite computer system in FIG. 1 is removed (or even if a failure occurs in any MLM), the other It does not affect the system's MLM (computers of other systems).

This effect is significant in the system of FIG. 1, where each MLM (each computer) is electrically isolated by an optical star coupler.

Now, the error detection and
Check bits ECCl and ECC2 for the write address A and write data D used for correction are stored in the computer 1 in the MLM 20-1 that is the transfer source of the data D.
When executing a write access request from 0-1, the same M L
EDAC2 provided in the control unit 24 in M20-1
It was generated by 5. That is, in this example,
Detection and correction of memory errors during memory access (to the storage device 21) performed in response to an access request from the computer 10-1, and MLM 20-1 to MLM 20-1 to
The same check bit (redundant bit) is used to detect and correct errors in the transmission system of the write information broadcasted to 20-n.

Therefore, memory writing to MLM 20-1, data transmission of this write data to MLM 20-1 to 20-n, and transmission of this transmitted data to MLM 20-1
Memory write to ~20-n, M L M 20-1~
(Reading data written to 20-n (memory reading))
It becomes possible to perform thorough checks including the following.

In addition, in the above embodiment, the transmitter 2 in the MLM 20-1
2) through the optical star coupler 30-1 to all MLMs 20-1 to 20-n including itself.
Although the description has been made assuming that broadcast transfer is performed, the present invention is not limited to this. For example, in a system that does not require itself to receive the information it sends and check the validity of the transmission system, even if the information is broadcast and transferred to all other MLMs except itself. good. That is, regarding MLM 20-1, M L
Transmission unit 22 of M 20-1 and M L M 20-1 to 2
M L M 20-1 out of 0-n<n-1 M
The configuration may be such that the receiving section 23-1 of the LM is connected radially in a 1:n-1 manner by an optical star coupler 30-1.

Furthermore, in the above embodiment, the case where the write information is broadcast transferred using an optical transmission system including an optical star coupler is explained, but it is also possible to apply broadcast transfer using an electrical signal transmission system, although the transfer speed will be reduced. be.

[Effects of the Invention] As described in detail above, according to the present invention, the following effects can be achieved.

■When each computer writes to the writable area of its own memory device (MLM), the same write data is transferred to the memory devices of other computers in the system via a coupling means (an optical star coupler in the embodiment). Since the data is broadcasted and written to the same address in the memory devices of other computers, the memory devices of each computer can have the same content, and each computer can read data in the memory devices of other computers using its own memory device. can be shared. Therefore, each computer can send and receive data to and from other computers by accessing its own memory device, and even though it is a loosely coupled composite computer system, it is possible to achieve high-speed data sending and receiving between computers.

■The area of the own memory device that each computer can write to (@writable area) is an area unique to each computer, and the write area from each computer is unidirectionally divided without duplication for each computer. Therefore, even if a failure occurs in the memory device of any computer in the system, it will not affect the memory devices of other computers. This effect can be obtained when an optical star coupler is used as a coupling means provided for each computer to radially couple the corresponding computer (memory device) and other computers (memory device). , 6 systems are electrically separated, −
The layer becomes noticeable.

■Since it is a loosely coupled type, computers can be distributed and computers can be easily added.

■Although it is a loosely coupled type, the memory access system and data transmission system use the same error detection and correction methods, and the configuration uses the same redundant bits, allowing error detection and correction.
The correction circuit can be shared, the circuit can be made smaller, and errors can be detected and corrected without omission.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a loosely coupled compound computer system according to an embodiment of the present invention, and FIG. 2 shows an address space (system address space) and an MEM (main memory ), a diagram for explaining the correspondence between address spaces assigned to MLM (multi-linkage memory device), and computer-writable areas assigned to MLM, and FIG. 3 shows control within the MLM in response to access requests from computers. FIG. 4 is a diagram illustrating the format of written information broadcasted from the MLM, and FIG. 5 is a diagram illustrating the shared state of computer data in each MLM. 1G-1-1O-n=・Calculator, 11-M E M (
Main memory) 12... Arithmetic control unit, 13...
System bus, 20-1 to 20-n...MLM (Multi Linkage Memory Device) 21... Storage device,
22... Transmitter, 23-1 to 23-n-receiver, 2
4-...Control unit, 25.26-1~2B-n=・EDA
C (error detection/correction circuit), 30-1 to 30-n.
...Optical star coupler, 51...System address space, 52-O...MEM address space, 52-1...
MLM Address Space, 53-1.5a-j, 5a-k
...writable area (writable area for computer #i, writable area for computer #j; writable area for computer #).

Claims (1)

[Scope of Claims] In a compound computer system in which a plurality of computers each having a main storage device are interconnected, a memory device added to each of the above-mentioned computers, which has a unique memory that can be written to from the own computer. Storage means for sharing data with other computers in the above system, and error detection and detection of data read from this storage means.
In addition to performing the correction, when executing a write request from the own computer to the above-mentioned writable area of this storage means, the first redundant bit for error detection and correction of the target write address and error detection and correction of the write data are performed. second for
a first error detection/correction means that generates redundant bits, and when executing the write request, a first error detection/correction means that generates a write address that includes the write address, the first redundant bit, the write data, and the second redundant bit; A memory device having a transmission means for transmitting information to the outside and a second error detection/correction means for detecting and correcting errors in the information transmitted from the outside, and a memory device having a one-to-one correspondence with the memory devices of each of the above-mentioned computers. coupling means for connecting the transmitting means of the corresponding memory device and the memory devices of each of the other computers; The write information including the write data to be written in the storage means of the computer is commonly transferred from the transmitting means of the own memory device to the memory devices of the other computers via the coupling means, and the transferred write information is Based on the first and second redundant bits in the write address and write data, the second error detection and correction means of each memory device at the transfer destination detects and corrects errors.
A multifunction computer system characterized in that a correction process is performed, and data is written to a storage means of a memory device at a transfer destination using the write address and write data after the error detection and correction process.