JPH0287574A - Solid-state image sensing device - Google Patents

Abstract

PURPOSE:To reduce resistances of electrodes while deformation of work functions of the first and second polysilicon layers is prevented in a solid-state image sensing device having a structure in which transfer electrodes of each phase are shunted through a metallic electrode by shunting the metallic electrode through the third polysilicon layers. CONSTITUTION:The third polysilicon layers 1a and 1d are connected with aluminum wiring layers 7a and 7d through contact holes 6a and 6d opened in inter- layer insulating films 33 and 34. As a result, clock signals phia of the first phase is supplied to the first polysilicon layer 3a through the third polysilicon layer 1a and clock signals phid of the fourth phase are supplied to the second polysilicon layer through the third polysilicon layer 1d from the layer 7a. Thus the aluminum wiring layer is shunted to transfer electrodes through the third polysilicon layers 1a and 1d. Therefore, the resistance of the wiring can be reduced while the variation of work functions of the transfer electrodes is suppressed, since the metallic electrode is not connected to the transfer electrodes directly.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a solid-state imaging device having a structure in which a transfer electrode is shunted with a metal electrode.

[4 Summary of the Invention] The present invention provides a solid-state imaging device having a structure in which transfer electrodes for each phase are shunted with metal electrodes, by shunting the metal electrodes through a third polysilicon layer. 1st
This is to reduce the resistance of the electrode while preventing fluctuations in the work function of the polysilicon layer and the second polysilicon layer.

[Conventional technology]

The resolution of solid-state imaging devices such as CCDs is increasing, and for example, when trying to configure a 2 million pixel CCD, the chimp size is approximately 16++ u.
n angle, the clock frequency is approximately IMllz, and the resistance becomes high in polysilicon, which is the material of the transfer electrode,
Transfer efficiency deteriorates.

Therefore, there is a technique that connects a metal electrode such as an aluminum electrode film to the transfer electrode to lower the resistance compared to a wiring made of only a polysilicon layer.
The first . A solid-state imaging device is known in which an aluminum electrode film provided on a vertical transfer section is connected to a second polysilicon layer.

[Problem to be solved by the invention]

By shunting a metal electrode to a transfer electrode made of polysilicon in this way, the overall resistance can be lowered and wiring compatible with a high-resolution solid-state imaging device becomes possible.

However, when the metal electrode is shunted directly to the transfer electrode, the work function of the first polysilicon layer and the second polysilicon layer, which are the connected transfer electrodes, changes, resulting in Charge transfer becomes difficult.

Therefore, an object of the present invention is to provide a solid-state imaging device in which fluctuations in the work function of a transfer electrode are suppressed.

[Means for Solving the Problem] In order to achieve the above object, the solid-state imaging device of the present invention has the following features:
The method is characterized in that shunting is performed with a metal electrode via the third polysilicon layer for each phase transfer electrode. What is each phase?
It refers to a multi-phase clock with a two-phase lock or higher, and the transfer electrodes of each phase are, for example, the 1Nth polysilicon layer formed on the vertical transfer section.

It consists of a second polysilicon layer. Examples of the solid-state imaging device include an interline type and a frame interline type. The third polysilicon layer may have a pattern extending over the vertical transfer section. The pattern may cover the entire area of the vertical transfer section in the transfer direction, or may be a pattern for each pixel. In the case where the 3Nth polysilicon layer of the pattern extending over the vertical transfer section is formed, metal electrodes corresponding to the clock signals of each phase are formed in the same pattern extending over the vertical transfer section. You can also. The contact between the third polysilicon layer and the metal electrode may be made in any area above the third polysilicon layer, and may be formed on the contact area between the third polysilicon layer and the transfer electrode. You can also do this. The metal electrode is, for example, an aluminum film, but may be made of other metals.

It is also possible to provide a barrier metal below the metal electrode, and it is also possible to provide a barrier metal on the third polysilicon layer.

[Function] In the solid-state imaging device of the present invention, the metal electrode is shunted through the third polysilicon layer. Therefore, the interposition of the third polysilicon layer suppresses fluctuations in the work function of each transfer electrode.

〔Example] Preferred embodiments of the present invention will be described with reference to the drawings.

This embodiment is an example of a frame interline type CCD, in which electrodes and the like are composed of three polysilicon layers and a 2N aluminum layer. This CCD is driven in four phases, and the first polysilicon layer and the second polysilicon layer function as transfer electrodes. That is, the first polysilicon layer receives the first phase clock signal Φa or the third phase clock signal ΦC, and the second polysilicon layer receives the second phase clock signal Φb or the fourth phase clock signal ΦC. A phase clock signal Φd is applied through the aluminum wiring layer and the third polysilicon layer, respectively.

First, the layout will be described with reference to FIG. 1. In the figure, the (vertical) direction is the charge transfer direction, and the H (horizontal) direction in the figure is the transfer direction of the horizontal register (not shown). Note that the aluminum wiring layer is not shown.

In the direction (2), a number of third-layer polysilicon layers +a, lb, lc, and ld are provided in order in a substantially linear pattern, and the lower portions of these third-layer polysilicon layers 1a to 1d transfer charges. Becomes a department. A sensor section 2 divided for each pixel is formed between these charge transfer sections. The sensor part 2 consists of, for example, a photodiode';
At the top, windows 12 of a light-shielding aluminum layer (first aluminum layer) each having a rectangular opening whose length is in the V direction are provided. There is a chaff 7t on the right side of the figure of each sensor part 2.
/l/Stotsuba SJI area is formed, and each sensor section 2
A channel stopper region and a readout section are formed on the left side of the figure.

In this COD, the transfer electrodes are the first polysilicon layer 3a, 3ck and the second Nth polysilicon layer 4b, 4d.
It consists of First and second layer polysilicon N3
a, 3c, 4b, and 4d each extend with the H direction as the longitudinal direction, and are formed in a pattern that widens on the vertical charge transfer portion and narrows in the region between the sensor parts 2. In the direction ■ in the figure, the first polysilicon layer 3a, the second polysilicon layer 4b, the 1Mth polysilicon layer 3c, and the second polysilicon layer 4d are formed in a circular manner. The first polysilicon layers 3a and 3c and the second polysilicon layers 14b and 4d are located in the area between the sensor parts 2 and in the upper part of the vertical charge transfer part. The ends become flat molds. The first phase clock signal Φa is supplied to the 1Nth polysilicon layer 3a via the 3Nth polysilicon layer 1a, and the third polysilicon layer 4b is supplied with the first phase clock signal Φa. silicon layer 1
The second phase clock signal Φb is supplied via the second phase clock signal Φb. A third phase clock signal ΦC is supplied to the first polysilicon layer Ji3c via the third polysilicon layer IC, and a third phase clock signal ΦC is supplied to the second polysilicon layer 4d. The fourth phase clock signal Φd is transmitted through the polysilicon layer ld of
is supplied. In FIG. 1, the connection between the first or second polysilicon layer and the third polysilicon layer is made through contact holes 5a, 5b, 5c, and 5d, respectively. The polysilicon layer and the aluminum wiring layer (not shown) are connected through contact holes 6a and 6b.
, 6c, and 6d, respectively. The positions of contact holes 5a, 5b, 5c, and 5d seen on a plane are as follows:
They are arranged diagonally, and only one vertical charge transfer section is H.
If it deviates in the V direction, it deviates in the V direction by one transfer electrode.

In addition, the above contact holes 6a 6b 6c6d
are shifted by approximately two transfer electrodes from the corresponding contact holes 5a, 5b5c, and 5d, and are similarly arranged diagonally. Note that openings 13 in the light-shielding aluminum layer are formed around each of the contact holes 6a, 6b, and 6c6d.

Next, to explain in more detail with reference to FIGS. 2 to 4, two vertical charge transfer sections 2 are shown in FIGS. 2 and 3.
1.22, and these two vertical charge transfer parts 2 on the plane
1.22, a sensor part 2 is provided. As shown in FIGS. 3 and 4, the vertical charge transfer section 21.2
A transfer electrode is provided on 2 with an insulating film 31 interposed therebetween. These transfer electrodes include a first polysilicon layer 3a to which a first phase clock signal Φa is supplied, and a second polysilicon layer 4b to which a second phase clock signal Φb is supplied.
, the first layer of polysilicon fM3c! to which the third phase clock signal ΦC is supplied. 1f: and a second polysilicon layer 4d to which the fourth phase clock signal Φd is supplied. Note that the region between the first polysilicon layers 3a, 3c and the sensor part 20 becomes a readout section. The 1Nth polysilicon layers 3a and 3c and the second polysilicon layer 4b4d are alternately formed with an insulating film 32 in between along the charge transfer direction of the vertical charge transfer portions 21 and 22.
At the ends of the first polysilicon layers 3a and 3c in the charge transfer direction, the second polysilicon layers 4b and 4
d is provided overlappingly.

The third polysilicon layer 1a, ld has a substantially linear pattern extending only over each vertical charge transfer portion 22, 21, and the contact holes 5a, ld formed in the insulating film 32, The polysilicon layer 3a is connected to the first polysilicon layer 3a and the polysilicon layer [4d] is connected through the polysilicon layer 5d. That is, the first polysilicon layer 3a and the second polysilicon layer 4d, which are used as transfer electrodes, are not directly connected to the aluminum wiring layer. These third polysilicon layers 1a and ld are connected to aluminum wiring layers 7a and 7d (second layer aluminum N) through contact holes 6a and 6d opened in the interlayer insulating film 3334. As a result, the first phase clock signal Φ is output from the aluminum wiring Ji7a.
a is supplied to the first N-th polysilicon layer 3a through the third polysilicon layer 1a, and the aluminum layer 1a is supplied to the first Nth polysilicon layer 3a. A fourth phase clock signal Φd is supplied from the S layer 7d to the second polysilicon layer M4d via the third polysilicon layer ld. Note that the second phase and third phase clock signals Φb ΦC
The same applies to Further, in the portions of these contact holes 6a and 6d, the light-shielding aluminum N8 covered with the interlayer insulating film 34 is also opened to form an opening 13.

In this manner, in the solid-state imaging device of this embodiment, the aluminum wiring layer is shunted to the transfer electrode via the third polysilicon layers 1a to 1d. Therefore, since the metal electrodes are not directly connected to the transfer electrodes, fluctuations in the work functions of these transfer electrodes can be suppressed and the resistance of the wiring can be reduced.

In addition, in the above-mentioned embodiment, the transfer lock was explained as having four phases, but it is not particularly limited as long as it is a polyphase of two or more phases. Further, the solid-state imaging device is not limited to a frame interline type, but may be an interline type. Further, the third polysilicon layer may have a pattern for each pixel subdivided in the {circle around (2)} direction. Also, the third
The contact between the polysilicon layer and the metal electrode is the third layer.
It may be a region on the third polysilicon layer, or may be on a contact portion between the third polysilicon layer and the transfer electrode. Furthermore, a barrier metal may be provided below the gold Rf& electrode or on the third polysilicon layer, and in this case, it is possible to sufficiently suppress fluctuations in the work function.

〔Effect of the invention〕

In the solid-state imaging device of the present invention, as explained in the embodiments described above, the metal electrode to be shunted is connected to the transfer electrode through the third polysilicon layer, so that the work function of the transfer electrode is Fluctuations can be prevented, and at the same time, the resistance of the wiring can be reduced.

For this reason, it is especially advantageous when attempting to increase the resolution of a solid-state imaging device.

[BRIEF DESCRIPTION OF THE DRAWINGS] FIG. 1 is a plan view showing an example of the layout of a solid-state imaging device of the present invention, FIG. 2 is an enlarged plan view thereof, and FIG. 3 is a sectional view taken along the line l1l-III in FIG. , Figure 4 shows the IV-T in Figure 2.
It is a sectional view taken along the V line. a to 1d...Third layer polysilicon layer...Sensor part a, 3c...First layer polysilicon layer 4d...
・Second polysilicon layers a to 5d...Contact holes a to 6d...Contact hole patent applicant Akira Koike, patent attorney for Sony Corporation (and 2 others)

Claims (1)

[Scope of Claims] A solid-state imaging device in which a metal electrode is used to shunt each transfer electrode of each phase, and the metal electrode is shunted through a third polysilicon layer.