JPH02241061A - Cmos gate array - Google Patents

Abstract

PURPOSE:To obtain a bypass capacitor having a large capacity with a small region by connecting the source, drain of a PMOS of an unused basic cell to a power source potential wiring, a gate to a ground potential wiring, the source, drain of NMOS to a ground potential wiring, and a gate to a power source potential wiring. CONSTITUTION:In a CMOS gate array in which a plurality of basic cells each made of p-channel MOS transistor and N-channel MOS transistor are arranged, sources and drains 10a-10c of P-channel MOS transistors 11, 12 of P-channel MOS transistors 11, 12 and N-channel MOS transistors 21, 22 of unused basic cell are connected to power source potential wirings Vcc, gates 11G, 12G are connected to ground potential wiring GND, sources and drains 20a-20c of the transistors 21, 22 are connected to the wiring GND, and the gates 21C, 22G are connected to the wiring Vcc to constitute a bypass capacitor.

Description

Detailed Description of the Invention (Field of Industrial Application) The present invention relates to a CMOS gate array used in a master slice type semiconductor integrated circuit, and in particular to a CMOS gate array that is provided with a bypass capacitor for noise absorption between a power supply potential and a ground potential. The present invention relates to a CMOS gate array.

(Prior Art) In a CMOS gate array, for the purpose of absorbing noise on the internal power supply line of an integrated circuit (for example, LSI) caused by logic switching, the power supply potential vCC and the ground potential GN are
A technique for providing a bypass capacitor between
It is described in Publication No. 1-61437 (Document 2).

The technology in Document 1 provides a so-called parallel plate type capacitor that covers almost the entire area of the basic cell using a first layer of metal wiring and a second layer of metal wiring that sandwich an interlayer insulating film. be. Further, in the technology of Document 2, the sources and drains of all transistors in the basic cell are connected to each other,
A MOS capacitor is formed between them and the gate.

In both cases, by forming a bypass capacitor on an unused basic cell that is not used for the user's logic function, the bypass capacitor can be placed close to the noise source without incurring disadvantages such as an increase in chip area. could be provided, thereby making it possible to absorb noise.

(Problems to be Solved by the Invention) However, the bypass capacitor in the CMOS gate array having the above configuration has the following problems.

In general, the unused basic cell area is used for global wiring for logic circuits, etc., so two metal wiring layers are used in the basic cell area, as in the technology of Reference 1. In a configuration in which a bypass capacitor is formed using a bypass capacitor, there is a problem in that it obstructs global wiring and makes it extremely difficult to realize an LSI or the like.

On the other hand, the structure of Document 2 has the advantage that a bypass capacitor can be realized only with the first layer of metal wiring.
It can be said that this is superior to that in Document 1. However, in the configuration of Reference 2, since the gates of all MoS transistors in the basic cell are connected in common, P-channel type MOS
S transistor (hereinafter referred to as PMO3) or N-channel type MOS transistor (hereinafter referred to as NMo3)
A transistor of one of the conduction types (in reference 2, P
The gate on the MO3 side) and the substrate are at the same potential and are in an off state. In such an off-state transistor, the capacitance that contributes to the bypass capacitor is only the junction capacitance, and the MO3 capacitance does not contribute. Therefore, with the technique of Document 2, a bypass capacitor with a sufficiently large capacity could not be obtained. In other words, bypass capacitors are placed in unused basic cell areas, but considering the need for an area to be allocated to global wiring after the bypass capacitors are placed, it is possible to provide an unlimited number of bypass capacitors. Therefore, it was difficult to obtain large-capacity bypass capacitors.

The present invention provides a CMOS gate array that solves the problem of the prior art, which is that it is difficult to obtain a large capacitance bypass capacitor in a small area without interfering with global wiring.

(Means for Solving the Problems) In order to solve the above problems, the present invention provides 1MO8 and NM
In a CMOS gate array formed by arranging a plurality of basic cells consisting of O3, unused basic cells 1MO8 and N
Among Mo5, 1MO8 (7) whose source and drain are connected to the power supply potential wiring and whose gate is connected to the ground potential wiring, and whose source and drain of NMo3 are connected to the ground potential wiring and whose gate is connected to the power supply potential wiring. This constitutes a bypass capacitor.

(Function) According to the present invention, since the CMOS gate array is configured as described above, all the PMO3 and NMo3 that constitute the bypass capacitor are in the on state, and the MOS capacitors of all these PMO3 and NMo3 are bypassed.・It becomes the capacitance of the capacitor, and the capacitor capacity in the receiving area can be increased. Therefore, the above problem can be solved.

(Embodiment) Fig. 1 (a>, (b), and (c) shows a bypass capacitor according to an embodiment of the present invention, and Fig. 1 (a) shows a wiring diagram,
The same figure (b) is an equivalent circuit diagram of the same figure (b), and the same figure (C)
is an equivalent circuit diagram organized from the circuit diagram in FIG. Also, FIG. 2(a).

(b) shows an example of an unused basic cell of a CMOS gate array in an embodiment of the present invention, (a) is a pattern diagram, and (b) is an equivalent circuit of (a). It is a diagram. Note that the same elements in FIG. 1 and FIG. 2 are given the same reference numerals.

First, the configuration of the unused basic cell shown in FIGS. 2(a) and 2(b) will be explained. This basic cell consists of two PMOs 311 and 12 and two NMos 321 formed on the same substrate.
and 22.

The two PMOs 311, 12 are connected to the sources or drains 10a, 10b, 10c of the P diffusion region and the gates 11G1, 11G2, '12G1.
PM0S11 and PM0S12 are connected in series via a common source or drain 10b. , the two NMOs 321, 22 are the sources or drains 20a, 20b, 20c of the N diffusion region.
and gates 21G1 and 21G2 formed on them.
Composed of ゜22G1.22G2, its NMO821
and 22 are connected in series through a common source or drain 20b.

Note that although omitted in FIG.
For example, near the center of MO321, 22, etc., power supply potential (VCC) wiring and ground potential (GN
D) Wiring is provided respectively.

By wiring the unused basic cells shown in Figure 2, a bypass capacitor is constructed, which is then connected to Figure 1 (a).
), (b), and (C).

In FIG. 1, the gate 10G1 of PMO311, 12
．． 12G1 is connected to the ground potential (GND) through the contact 30.
) In the wiring 32, the source/drain 10a, 10b, 10
c is the power supply potential (VCC) wiring 3 via the conductor 30
1, and both PMOs 311 and 12 are in an on state. Furthermore, the gates 21G1 and 22G1 of the NMOs 821 and 22 are connected to the power supply potential wiring 31, and the sources/drains 20a, 20b, and 20c are connected to the ground potential wiring 3.
2, and each NMO 821 and 22 are in an on state.

FIG. 3 is a schematic cross-sectional view of the PMO 311 in FIG. 1.

This PMO 311 is formed in the N-well 40, the drain/source 10a and 10b are both connected to the power supply potential VCC, and the gates 11G1 and 11G2 are connected to the ground potential GND.
source/drain 10a, 10
An inversion layer 41 is formed between drain/source 10a, 1
Since conduction occurs between 0b and 0b, a large MO8 volume ff1cox due to the thin gate oxide film 42 connects the inversion layer 41 and gate 4.
Obtained within 2 hours.

As shown in FIG. 3, when the PMO 311 is on and the drains/sources 10a and 10b are at the same potential, the MO8 capacitance C8X is
>Specific dielectric constant ε of oxide film = 4 Gate length L = 1 μm Gate width −10 μm. Here, the gate oxide film thickness t. Assuming x=200 people, Cox=W0.018pF by equation (1)
becomes.

Next, in order to compare with the conventional one, PMO8 in the off state
Estimate the capacity of In this case, as described in Document 2, the drain and source of PMO3 are connected to ground potential GND, and the gate is connected to power supply potential VCC. Since the substrate (N-well) potential of PMO 8 is naturally equal to VCC, the only capacitance contributing to the bypass capacitor is the junction capacitance IICjx of the P+N- diode during reverse bias. Here, assuming that the junction is sufficiently shallow and the influence of the side surfaces of the junction can be ignored, the junction capacitance Cjx is expressed by the following equation.

AS 1 Pb However, AS: Area of each junction VB3: Substrate-source voltage Build-in voltage of substrate junction Pb# 0.89V Relative dielectric constant ε of silicon. =12 Electron charge q=1.6 x ID-19C substrate impurity concentration N sub , 4; i, 8 X1015 (cm
-3) In equation (2), the substrate-source voltage VBS is v8s=-5v since the voltage between Vcc and GND becomes a reverse bias as it is. Here, the area AS of each junction is, for example, AWxA L=10. czmx 3μm=30μm2
...(3) However, AW: drain/source 20a in FIG. 1(a)
Assuming that the vertical length AL is the horizontal length of the drain/source 20a in FIG. 1(a), c, x=o, oo 15 pF is obtained from equation (2). Note that in equation (3), AW=10 μm is a value selected to match the gate width W=10 μm, and AL=3 μm is a value selected to provide a common transistor shape as a basic cell of a gate array.

In the basic cell of the shape shown in Fig. 2, PMO811
, 2 sets of MO3 capacitance on the 12 side (number of gate electrodes)
, there are three sets of junction capacitance (the number of drains and sources), so
In the end, MO3O3 capacitance meter T1 > total junction capacitance T2...(4
) However, T 1 = CoxX 2 = 0.041) FT
2 = Cj months x 3 and 0.05pF. In other words,
An on-state MoS transistor can provide an order of magnitude larger capacitance than an off-state MoS transistor.

Therefore, in this embodiment, all the MOS transistors are turned on, so that a bypass capacitor with a larger capacitance than the conventional one can be obtained.

In addition, in this example, as shown in FIG. 1(a), PM
By using the power supply potential wiring 31 and the ground potential wiring 32 arranged in the center of each of O311, 12 and NMO321, 22 (7), regardless of whether the basic cell is used or not, the first layer metal wiring You can easily configure a bypass capacitor using only Therefore, there is no problem of significantly interfering with global wiring as in Document 1. In its tap water example, PMO 311,12 and NMO 821°2
2 gate 11G1.11G2.11G2.12G2.
The potential of 21G1.21G2.22G1.2202 and the potential of the power supply potential line 31 and the ground potential line 32 made of the first layer metal formed above are opposite potentials. For example, gate 11G1.11G2 of PMO311°12
... are connected to the ground potential wiring 32, and the power supply potential wiring 31 passes above them. Such power supply potential wiring 31 and ground potential wiring 32 are generally wider than the signal line, and therefore, the capacitance between the gate and the first layer metal wiring can also be taken into account as the capacitance of the bypass capacitor.

Furthermore, as shown in FIG. 4 showing an example of the wiring pattern of FIG. 1, portions 31a and 32a of the power supply potential wiring 31 and the ground potential wiring 32 made of the first layer metal are respectively extended in the gate direction. It is also possible to add a larger capacity.

Note that the present invention is not limited to the illustrated embodiment; for example, the first embodiment
Various modifications are possible, such as changing the basic cells shown in the figures and FIGS. 2 to other configurations, or changing the power supply potential wiring 31 and the ground potential wiring 32 to wiring patterns other than those shown in FIGS. 1 and 4 accordingly. .

(Effects of the Invention) As explained above in detail, according to the present invention, a bypass capacitor is configured to obtain MO3 capacity under the condition that PMO3 and NMO8 of unused basic cells are all turned on. , it is possible to obtain a capacitance approximately twice as large as that of a conventional configuration in which only the capacitance of a MOS transistor of one conduction type is used. Furthermore, since it can be reasonably constructed using only the first layer of metal wiring, for example, the problem of hindering global wiring caused by using two layers of metal wiring can be easily and accurately improved.

[Brief explanation of drawings]

FIGS. 1(a), (b), and (c) show bypass capacitors according to embodiments of the present invention, and FIG. 1(a) is a wiring diagram,
Figures (b) and (C) are equivalent circuit diagrams, Figures 2 (a) and (b)
) shows the basic cell of the embodiment of the present invention, and (a
) is a pattern diagram, FIG. 3(b) is an equivalent circuit diagram, FIG. 3 is a schematic sectional view of 1MO3 in FIG. 1, and FIG. 4 is a wiring pattern diagram of FIG. 1. 10a, 10b, 10c, 20a, 20b, 20C...
...Drain/source, 11, 12...1
MO3, 11G1.11G2.12G1.12G2゜2
1G1.21G2.22G1.22G2... Gate, 31... Power supply potential wiring, 32...
・Ground potential wiring.

Claims (1)

[Claims] P-channel type MOS transistor and N-channel type MO
C formed by arranging multiple basic cells consisting of S transistors
In the MOS gate array, among the P-channel MOS transistors and N-channel MOS transistors of unused basic cells, the source and drain of the P-channel MOS transistor are connected to the power supply potential wiring, and the gate is connected to the ground potential wiring. A CMOS gate array, characterized in that the source and drain of an N-channel MOS transistor are connected to a ground potential wiring, and the gate is connected to a power supply potential wiring to form a bypass capacitor.