JPH02136834A - Microcomputer for camera accessory - Google Patents

Abstract

PURPOSE:To control the area of a ROM to be made access by means of an external signal by adding a circuit which decides a specific number of high-order pitches of a program counter through hardware. CONSTITUTION:This microcomputer incorporates plural pieces of program codes (ROM) 2 in corresponding to an accessory mounted on a camera and high-order bits of a program counter 1 for deciding the address of the ROM 2 are unequivocally decided by means of an external input signal which makes directly access to the ROM 2. Namely, buffer gate 3 and 4 with chip enable terminals are inserted between terminals upon which IRAS1 and IRAS2 are respectively impressed and a CPU/memory separate signal EA is impressed upon the chip enable terminals. Then one of the executable areas of the ROM 2 is selectively decided. Therefore, the address space in the ROM can be controlled and freely used in a divided state by means of external signals.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a microcomputer for a camera accessory, and more particularly to a microcomputer that is used with an interchangeable lens barrel attached to a camera body and a built-in strobe unit.

[Prior art] In recent years, microcombustion in cameras - C by Yu
The use of PUs has expanded dramatically, and it is not uncommon for multiple CPUs to be used in one camera system. Especially-
In interchangeable lens cameras, such as eye reflex cameras, AF (autofocus) has become increasingly popular, and CPUs have come to be built not only in the camera body but also in camera accessories such as the lens barrel. ing. In addition, various actuators such as the AF drive motor, aperture drive motor, and the control unit for the built-in AF auxiliary light are mounted inside the lens barrel, and these are controlled by commands from the CPtJ of the camera body. , many systems have been proposed in which the C F' U on the side of the driver's m8 executes the system.

For example, the camera described in JP-A No. 60-26324 1f1l has a main CPU installed in the camera body, and also has seven film winding, winding, and rewinding functions.
'1λ dynamic drive unit, power source 1 (B,
Sub-CPUs each having a unique address code are provided, and the data input/output terminals of the main CPU and each sub-CPU are interconnected. When an address code is first sent from the data input/output terminal of the main CPU, each sub-CPU receives this address code and compares it with its own address code, and only the sub-CPU that matches the address code will be the next one. It waits for a control code sent from the main CPU. When the control code is sent, the above MU
The CPU performs camera operations corresponding to this control code, and sends the results to the main CPU from the input/output terminal to the above data.
It is designed to be sent back to the PU side.

By the way, there is a C inside the lens barrel as a camera accessory.
When using PU, conventionally developed CPUs, for example, 50mmFl, g, 35-70mmZ
For oomF 4, 70-210m+wZooLIF
5.6, etc., the CPU R for each lens.
I have to make an OM mask.

Moreover, in order to expand camera sales by enriching the lineup of camera accessories, it has traditionally been necessary to
There was frequent work to create ROM masks.

Therefore, one possible solution to this problem is to use an EPROM type (electrically programmable read-only memory) CPU, but the EPROM type increases the chip area when manufacturing the CPU and is inevitably expensive. turn into. Furthermore, in mass-produced products, it is necessary to write electrically each time, which increases the number of man-hours.

On the other hand, in recent years, the integration of ROM has progressed in CPUs with built-in ROM, and it has become possible to obtain a larger amount of memory with the same chip area. Even if a CPU is used, it has become possible to get away with a modest increase in cost. Therefore, by using this, for example, if the ROM size is 8 bits,
When applied to a CPU with a part-time job of 16 and
-70mmZoomF 4 and 70-210mnZ
oomF 5. 4 for B and 350n+mF2.8 etc.
Programs with different specifications can be stored in one CPU.

In this way, a CPU with a built-in ROM with a large memory capacity
If a CPU with a built-in control program for multiple lenses is developed using the U, and the ROM area of the CPU is selectively determined by an external switching signal, the CPU
By reducing the number of times the mask ROM is manufactured by a large number of times, the schedule required for manufacturing the ROM mask can be significantly shortened and the software of common parts can be used effectively.

In addition, this will reduce the cost of mask charge by 1/
4, and CPU manufacturers can also expect to reduce the number of ROM mask production times to 1/4, thereby shortening the schedule.

[Problem to be solved by the invention] However, the C
If a PU is used to load control programs for a plurality of lenses into one ROM, it is necessary to divide the ROM space into four in terms of software.

That is, in FIGS. 9 and 10, the processing routines P0°1, Po,
Figure 9 shows an example of dividing the ROM address space into four areas using 1.0 and 1.0. FIG. 10 is a diagram showing an "INTO" processing routine similar to other interrupt processing routines. In the "power on" routine shown in FIG.
When the power is turned on, the PC (program counter) gives instructions. After executing the "CPU initialization subroutine" stored at address ooo and thereby initializing each section of the CPU, "Po, 1. Proceed to ``Read Po, 2''.Then, read Po, 1 to the CPU.
According to the logical level of Po, 2, “Po, 2” means po,
If 2 is O, go to “first Po, 1”; if 1, go to “second PO”
ll" respectively. Then, "first PO,]
``Second Po, 1'' respectively determined Po.

According to the logic level 0.1 of 1, "Type 'A lens'
'Type B lens' 1 'Type C lens',
It branches to each subroutine of the Type D lens and continues processing in each subroutine until it is turned off or turned off.In the INTO processing routine shown in Figure 10, the terminal Then jump to P0.1, Po.

From the ``2 read'' routine, the same processing as explained in FIG. 9 is performed, and then the process ``returns'' to the routine following the ``-1:, record jump ■'' processing routine.

On the other hand, with the means of dividing the ROM space into four using software, troublesome processing is required when processing such as an interrupt occurs. That is, if the specifications of the target lenses are different, for example, an interrupt called "INTO" may be used as a power focus start signal for a certain lens.
In addition, with other lenses, a stop switch is used manually to forcefully stop the lens drive (7), so the program is programmed based on specific 2-bit information at the point where the interrupt processing occurs. It is necessary to branch out.

This places a heavy burden on the software side, and
The execution time of the interrupt processing is long (7), which goes against the original attempt to improve the execution speed of the interrupt processing (7).

SUMMARY OF THE INVENTION Therefore, an object of the present invention is to solve the above-mentioned problems and to provide a camera accessory that divides a ROM space in which a plurality of lens control programs are stored, instead of using software to divide the ROM space. The purpose is to provide microcomputer services.

[Means for Solving the Problem 1] The microcombiner for camera accessories of the present invention has the following features:
Compatible with accessories attached to the camera 1. τMultiple completed program codes (hereinafter abbreviated as ROM)
A micro combicoater with a built-in ROM, in which a specific high-order bit of the program counter for determining the ROM at L node is uniquely determined by an external input signal that is directly accessed, and thereby an area of the built-in ROM that can be executed. One of them is selectively determined.

[Sakukawa] The program counter for determining the CPU's ROM address is forced to set the 1-order bit of the RONi atto 1 nos space by an external input signal, and this set bit allows the program counter to specify a specific address. If the bit part is fixed from 1 to 8, the range of the output nfl range in the I NROM is forcibly determined. Can be used.

[Embodiment] The present invention will be specifically explained below with reference to the drawings. First, as shown in FIG. An overview of the camera system developed will be explained below. .

As shown in FIG.
2 via a rack mechanism 43, and movement of the zoom lens 48 is detected by a zoom encoder 45. Further, the diaphragm mechanism 46 is driven by a step motor 44, and the subject light transmitted through the photographing optical system is arranged behind the planned focal plane 28, and is arranged behind the pupil projection lens 24a. The A-group sensor 25a is divided by a pupil-splitting optical system 24 consisting of pupil-splitting lenses 24b and 24c.

The line sensor 25 consisting of the Bil sensor 25b is irradiated with the light.

This line sensor 25 is formed by arranging a plurality of 5IPTs (electrostatic induction photoI transistors) in a straight line, and the signal photoelectrically converted by the 5NPTs is sent to the microcontroller of the camera body via an interface circuit 26. computer (hereinafter abbreviated as B-ltCOM)]1.

The voltage of the power supply battery 12 is supplied to each circuit by turning on the main switch 13, and the voltage of the power supply battery 12 is supplied to each circuit by turning on the main switch 13.
The /DC converter 14 stabilizes the battery 1u pressure (supplied after 7 seconds.) The BμCOM II performs sequence control of the entire system and performs various calculations. Two computers (hereinafter referred to as L-μCOM) perform control.

The display control circuit 15 displays various modes, the number of film frames, and exposure information (AF status) in the finder according to commands from the B-μC0M11.

The mode setting switch 16 is used to set exposure mode, AF operation mode, and in manual exposure mode, T
v value r Avlii! Used for setting.

The release switch 17 is a two-step press switch, and the first step signal generated when the release switch 17 is pressed halfway is B-μCOMII, AF,! 1. Execute Oki 1 light,
Exposure operation is performed by the second stage signal generated when the switch 17 is fully pressed.

The shutter control circuit 18 forms the shutter shutter time Tv based on the shutter shutter time signal of the B-μC0M11. In addition to up/down control of a quick return mirror (not shown), the leading and trailing curtains of a focal brain shutter (not shown) are also controlled based on the TV value.

The winding and rewinding control circuit 19 controls the winding and rewinding of the film based on commands from the B-μC0M11.

The photometry processing circuit 20 detects the subject brightness from the photocurrent of a /1$1 optical element such as a 5PD (silicon photodiode) 21, and sends a signal of the subject brightness By to the B-μC0M11.

The film sensitivity reading circuit 22 reads the DX code of the film and sends the film sensitivity information Sv signal to B-μCOMI.
Send to I.

The light flux from the exit pupil of the photographic lens is divided by a pupil splitting optical system 24, and a group A sensor of a line sensor 25 is formed of 5ITs (static induction transistors) in which 5IPTs (static induction phototransistors) are arranged in a line. 25a and 8 group sensor 25b, respectively.

The interface circuit 26 consists of a line sensor control circuit and an A/D converter, and when a control signal is supplied from the B-μC0M11, the line sensor control circuit operates and integrates the signal output from the line sensor 25. . When the appropriate level is reached, the integrated output is changed to A/
Convert to digital value with D converter and convert to B-μCO
This value is supplied to MII, and B-μC0M11 calculates the amount of focus shift from this value.

The mount contact 30 is a contact for connecting the circuit on the camera body side and the circuit on the lens side, and supplies power to the lens side and L-μC0M29 and B-μC0 through the contact 30.
M1.1 communication is executed.

Next, explaining the lens barrel side, L-μC0M29
drives the lens based on the command of B-μCOMII,
Performs aperture drive, various calculations, etc.

The lens status switch 32 includes an Avo switch.

There is a 5TOP switch and an AM switch. A v.

The switch detects when the aperture is open, and is always on when the aperture is stopped down, and turns off when the lens is wide open. 5TOP switch is user A
This switch is used when it is desired to perform an exposure operation regardless of the F state. When the 5TOP switch is turned on, lens drive is interrupted, and when the release switch is pushed to the second step, the exposure operation is immediately executed. The AM switch is
When set to AF side with the switch to change between AF and MF, "A"
When F single "or" AF servo 1 mode is executed and it is set to MF side, power focus is executed in which L-μC0M29 controls the amount of lens drive corresponding to the rotation amount of rotation 1 Eisakubu shrine. It has become.

An auxiliary light circuit including resistors 33 and 35, a transistor 34, an LED 36, and a condensing lens 31 is used to increase the brightness of the subject by turning on the high-intensity LED 36 and projecting light onto the subject when the subject brightness is low. The lens driver circuit 37 forms signals for operating the first and second motor drive circuits 38 and 39 based on the two L-μC0M commands.

In addition, the L-μC0M29
Send to.

The rotation operation member 40 corresponds to a distance ring, and outputs two-phase clock pulses in accordance with the rotation of the lens barrel. This output becomes a rotation direction signal and a pulse indicating the rotation speed in the lens driver circuit 37, and is converted into a pulse indicating the rotation direction signal and rotation speed.
29.

The pulse generator 41 generates pulses proportional to the amount of rotation of the DC motor 42 that drives the focus adjustment lens 47.

The output is waveform-shaped by the lens driver circuit 37 and then sent out L-μC0M29-\. The first motor drive circuit 38 is composed of a bridge circuit of transistors, and drives the DC motor 42 . The zoom encoder 45 outputs a code corresponding to the position of the zoom lens 48, that is, a value corresponding to the current focal length of the zoom lens 1 as L-μC0.
Output to M29. The second motor drive circuit 39 is a circuit that drives the step motor 44 that drives the aperture mechanism 46 .

Next, the signal line of the mount contact will be explained.

The mount contact 30 includes power supply lines PWR and PWR2 for supplying power from the camera body to the lens circuit.
, B-μC0M11 and ■,=μC0M29 are connected to communication signal lines for communication, respectively. The signal line LR5T is from B-μC0Mll- to L-μC0M29
The heliset signal is connected to the signal lines MC0NT and LCONT.
is a handshake line used to synchronize when communicating between B-μC0M1.1 and L-μC0M29, and signal line CLK is a line that carries a synchronization clock used to synchronize data in serial communication. . Serial data flows through the signal lines RXD and TXD, which are connected in series, in synchronization with the output of the clock signal CLK. For example, from B-μCOMII to L-1, noC0
When data is sent to M29, B-μCOMII
Data is output from TXD of L-μC0M29 RX
Data is now input to D. The signal line LMSW is used to determine whether an accessory lens is attached to the camera body, and is connected to the power supply line through a pull-up resistor 27, and is Therefore, when the lens VL is attached to the camera body, the logic 1 level of the signal line LMSW is "L" level, and when it is not attached, it is "H" level. Therefore, by reading the logic level of this signal line LMSW as B-μCOMII, it is possible to know whether the lens t?

B used for the camera system constructed in this way.
An overview of CPLIs such as -μC0M111 and L-μCOM29 will be explained using FIGS. 3 to 5.

Figure 3 (A) is a layout diagram showing the main components of such a CPU, and Figure 3 (B) is a simple configuration diagram of the program counter (hereinafter referred to as PC). be. In the figure, the CPU 60 has a ROM section 2 within itself.
．． It has RAM sections 56 and 110, a timer section, and a peripheral circuit 52 that performs communication functions.

The code to be executed by the CPU is programmed into the ROM 2, and when the read address is set by the PCI, the code is transferred to the ROM via the address buffer 51.
2 is supplied with a read command.

Then, the memory contents of ROM2 are transferred to the CPU internal BUS5.
The ALU (Central Processing Unit) 55
Cooperation with C (accumulator) 53 and Temp (temporary register) 54 1. and execute the command. Also, 1
Each time an instruction is executed, the PCI is incremented to store the contents to be executed next.

Next, the general architecture of the CPU 60 will be explained in more detail using FIG. 4.

"lNROM" 2 contains 1.6 bytes worth of programs.
A memory is built in as a mask ROM 5 on the chip. Since the memory capacity is 16 bytes, the address AO-
A13 causes the ROM address to be designated and read. Codes DO to D7 are codes stored in R and OM, and are led to the CPU internal BUS.

'r'cH' 1 a/'PCL' lb is the Hl byte and LO byte of the program counter 1 with a length of 16 bits, and if all the pins are used, ix bytes can be selected in the at1nos space 64.

"PCHL"71a/'PCLL' 71b latches the value of the program counter 1 and stores it in the internal ROM 2.
or the address of an external ROM (not shown) via PORT 72a or PORT 272c.

'DPH'73a/'DPL' 73b are the H1 byte and LO byte of a 16-bit data pointer.

As a base address for register indirect addressing, it is used for transferring constant data in program memory, transferring variable data in external data memory, and for branching instructions on the 64 byte program memory space.

'SP' 74 indicates the address of the stack set in the 256-byte memory area of the internal data RAM 56.

IR'76 is an instruction register, P
L A (Programmable Logic A
lay) 77 and is converted into a control signal.

'PLA' 77 is Programmable Logl
c Alay, which generates necessary control signals according to the IR.

“AIR” 78 indicates the address of a register, ROM, etc. where the instruction indicated by the IR register 76 is to be executed.

'5PECIAL FUNCTION REGIS
TERADDRESS DECORDER'79 is
Indicates the address of SFR that controls various registers of the CPU. Note that SFR refers to various registers including the ACC53.

“TRI” 80. "TR2" 81 is ALU55
This is an 8-bit temporary register guided by

ALU"55 is an arithmetic logic operation unit, and stores one or two 8-bit data in a temporary register TRI,
The receiver is received from TR2 and processed. Processing contents include addition/subtraction, increment, decrement, bit inversion, rotated decimal correction 1 multiplication, division, bit detection, and logical OR.

Can process logical AND, exclusive OR, etc.

"PSW" 82 is a program status word, and indicates switching of various operation registers and general-purpose register banks of the ALU 55, and the like.

"ACC" 53 is an accumulator, and is a central register for executing arithmetic and logical operations of the CPU.

'RAMDP' 83 is a data pointer for the built-in RAM 56.

“5BUF(T)”84. 5BUF(R)'85.
5CON' 86 is a buffer and control register for serial I10. It also controls interrupt requests, etc.

'TH1'87. 'TL1'88. 'THO'
8, "TLO" 90 are each 16 bit long timer event counters.

'TMOD' 91. “TCON” 92 is 16
This register controls bit timers 0 and 1. Controls timer mode and event mode selection, start, stop, interrupt requests, etc.

IE"93. "IP"94 is an interrupt enable register and an interrupt priority register, respectively, and controls interrupts.

“TR2”95. "TL2" 96 is a multi-mode 16
This is a BIT timer/event counter with additional functions such as capture mode and baud rate mode.

“72CON” 97 is a control register for timer 2.

RCAP2L"99 RCAP2H'98 is a register used when timer 2 operates in capture mode.

"FORT O" 72a is an 8-bit Ilo, and in external ROM use mode, "FORT O" and "
Expand the memory space using ``PORT 2''.

"PORT 1" 72b has an 8-bit I10 port and a timer 2 manual function.

'PORT 2' 72c is an 8-bit I10 port and is also used when expanding memory.

“PORT 3” 72d is an 8-bit I10 port with secondary functions and [7] Serial port interrupt.

Evening/Ima 01 Manually Outputs the timing signal for external memory use.

lNC0N" 100 "PCON" 101 is
"PCON" is a register that controls the power saving mode, etc.

IRAS1'' The "IRASO" signal is a human signal that forcibly controls pins 1-12.13 of the PCI from the outside, and is controlled by the DW signal.

"n-" (d is whether to use external ROM or internal ROM.
This signal determines whether to use 2 or 4.

The XTAL1" and XTAL2" terminals are input/output terminals for a lock signal necessary for the operation of the microcomputer.

The “)~LE” signal is sent to the external memory use 114J by the CI
) To capture the Atonenos signal output from the IJ boat during lunch in the evening (No. 3).

The "r3-■° signal is a signal that is output when an external program signal is sent, and is output when an instruction and data are taken in.

The "RESET" terminal is a reset signal input terminal to the CPU, and when the reset is released, the program is executed.

First, the input/output terminal r of the CPU 60 shown in FIG. 4 will be explained with reference to FIG.

The XTALl, XTAI, and 2 terminals are terminals for externally connecting a crystal resonator used for the crystal controlled oscillator for the internal clock signal of the CP TJ. The capacitor 6263 is connected to each other.

When the reset signal supplied to the RESET terminal changes from active to non-active, reset/reset is released and P
C starts executing the program from oooo.

XTT1 ■) 1 ball. Wπ and R-5 are external ROMs.

This is a terminal for timing with the FORTO BUS, which will be described later, when using external RAM t7.

Vcc and Vss are power supply terminals, and normally +5V is supplied to Vcc and OV is supplied to VSS.

PORTO, PORTI, PORT2. PORT3 is
Its primary function is as an input/output terminal, and PORT
is designed to perform an extended BUS function as a secondary function. Mat-1 PORTI.

PORT3 has a secondary function and 15, a timer, and a serial communication 1 interrupt-9 function.

- [W is CPU MEMORY 5EPARAT
E, when Ei or HI level, internal ROM or TI
When is at the HO level, the external ROM is selected.

IRASO and IRASI are the characteristics of the present invention,
The address space of INROM is divided into four by this 2-bit signal 5 at the signal input terminal r of IN ROM AREA 5ELECT.

This terminal is enabled only when n is an H1l novel.

Next, the present invention is applied to the CPU 60 configured as in 1. Another embodiment will be described with reference to FIGS. 1, 6, and 7. FIG. 1 is a block system diagram showing the main parts of a microcomputer for a camera accessory according to an embodiment of the present invention. In the figure, the PCI consisting of a 1-6 bit counter is the bit pc constituting the L-order byte]a.
= pc15 and bit P that constitutes lower byte 1b
Co to pc7, and the G4 number is exchanged between the input/output terminal of each byte and the DATA BUS6 inside the CPU. On the other hand, 1
6 bytes of memory, internal storage with capacity R, OM 2
is divided into four blocks, that is, divided into four blocks of 4 bytes, and the stored information is read out to the CPU internal BUS5. In order to specify the address of the content storage ROM2 in item 1-1, the 12-bit address line from PC to PC11 of the PC1 is connected to the ROM2.
1.

And PCI2 of PCI. The 2 bits of PCl3 are
IRASI on the line that selects two consecutive 4 blocks.
and the end J' to which the IRASO signal is applied,
A buffer gate 3.4 with a chip enable terminal is inserted, and a CPU MEMORY 5EPARATE signal TT is applied to the chip enable terminal of the buffer gate 3.4. J: The sea urchin is turning. Therefore, since the buffer gate 3.4 is enabled when the signal rτ is at Hl level, it becomes an internal ROM mode, and the ROM 2 receives the IRASI and IRASO signals regardless of the PCI bits PC, 2, and pc. An address space divided into four parts will be selected. on the other hand,
When the signal TI is at the LO level, the buffer gates 3 and 4 enter an external ROM mode called disabled. Also, bit PCl5. of the PCI mentioned above. PCl4 is external R
Since it is used for addressing when using the OM, up to 64 bytes can be accessed in external ROM mode.

In this embodiment configured as described above, when Rs c is released, the PCI counts up from 0OOOH in hexadecimal notation, and increments by +1 every time a - instruction is executed.

When the T''K signal is at the Hl level, the CPU enters the INROM mode, fetches the R Otv1 data stored at the address designated by the PCI, and sends it to the CPU internal BUS.

When the n signal is at the LO level, the mode is set to external ROM, and the address specified by Pct is transferred to the CPU internal BUS.
5 to "FORTO" 72a (see FIG. 4), thereby indicating the access address of the external ROM.

IRAS (IN ROM AREA 5ELE
CT) 0. 1 signal q is n-Hl (IN ROM
bit 12 of Pct becomes active according to settings from outside the CPU. Forcibly determined by wired ORing bit 13.

FIG. 6(A) shows the '[W signal, rRAsl, IRAS
The relationship between the O signal and the logic level of each bit of PCI is shown. In the figure, the X mark indicates that its logic level may be either 1 or 0.

FIG. 6(B) shows the address space of the internal ROM 2 at this time in comparison with the IRAS1 and IRASO signals. As can be seen from the figure, INROMAREAO has Ty
ARE for peA lenses, AREAI for T'ypQ B lenses, AREA2 for TypeC lenses.
A3 describes each application for the Type D lens. And the above AREAO~3
is in the internally stored ROM area, AREA4 is in this C
Each corresponds to an area of a ROM provided outside the PU.

FIG. 7(^) shows the address space for interrupt processing. In the figure, IRASl, ARE where O is OO
When an interrupt occurs in the AO, the PCI response is the same as in a conventional CPU.

Figure 7 (13) shows IRASI, AREA where 0 is 0, 1.
This figure shows the response of the PCI when an interrupt occurs in I. AREAI's ROIV1 space is 100O
Since there are 4 bytes from H to IFFFH, the interrupt processing must also respond to this, but since bit 12 of PCI is always set to 1 by the IRASI signal,
No problem.

However, in the CPU shown in the conventional example, an interrupt will occur in AREAO in this case as well, and the countermeasures will be taken up by software, making the processing complicated and time-consuming.

In other words, when dividing multiple lens control programs stored in one ROM space, the problem of complicated processing and time required on conventional CPU-derived software can be solved as follows. There is. That is, by controlling (setting to HI/LO) the input of two specific bits determined on the lens-side substrate on which this CPU is mounted, the program area can be arbitrarily selected and used.

FIGS. 8(A) and 8(B) show a software development environment for the CPU of the present invention. The present invention is to control Pct externally by hardware only when the CPU is mounted on the U plate of the application lens.
The software development steps up to ordering the mask for the CPU's ROM section are completely unchanged from before. All conventional development environments can be used, and hardware and software depacking is possible using conventional escalators. This imposes no burden on the software developer or the software developer, and is extremely convenient.

[Effects of the Invention] As described below, according to the present invention, the internal ROM can be
The address space of the ROM stored inside the CPU can be divided by adding a circuit that determines a specific number of high-order bits of the program counter (PC) in hardware using an external code. Therefore, it became possible to control the area to be accessed in the ROM using an external signal.

This makes it possible to incorporate software with different specifications into the same CPU, making it possible to improve the development efficiency of CPUs.

According to this method, the software development method can be
The method for developing U can be used in common, and in software development, a remarkable effect is achieved in that several separate applications can be realized on the same CPU without any increase in burden.

[Brief explanation of the drawing]

Fig. 1 is a block system diagram showing the main parts of a microcomputer for a camera accessory according to an embodiment of the present invention. Fig. 2 shows a microcomputer equipped with a microcombi coater at each interface between the camera body and the accessory interchangeable lens. A block system diagram of the camera system, FIG. 3 (^) is a layout diagram showing the main components of the microcomputer used in the present invention, and FIG. 3 (B) is a block diagram of the camera system in FIG. 3 (A). 4 is a block system diagram showing the general architecture of the microcomputer shown in FIG. 3(A) above; FIG. 5 is a block diagram showing the general architecture of the microcomputer shown in FIG. The terminal arrangement diagram, Figure 6 (^), shows the Tff signal and IRAS in the program counter of the microcomputer shown in Figure 1 above.
FIG. 6<13) is a diagram showing the logic states for each signal of I and IRASO.
Figures 7(A) and 7(B) show the address space during interrupt processing. Figure (B) is a diagram showing the case where the IRASI and 0 signals are 0.1, Figure 8 (Δ) and (+3) are diagrams showing the CPU software development environment of the present invention, Figures 9 and 10 The figure is a flowchart for dividing the ROM address space in a conventional microcomputer for camera accessories into four parts. Fig. 9 shows the case of power-on reset, and Figs. 1 and 0 show the case of IN'r O processing. FIG. 1...Program counter 2...
・・・・・・・・・・・・ROM60・・・・・・・・・
・・CPU Patent n4 Applicant Olympus Optical Industry Co., Ltd.'f1゜Representative Mr. Fujikawa Seven Part muscle diagram 6 (A) Horse a (A) Horse diagram 6 (B) r-----"-"'-- -”--1-ko PC=65,
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Claims (1)

[Claims] (1) In a microcomputer that contains multiple complete program codes (ROM) corresponding to accessories attached to the camera, a specific high-order bit of the program counter for determining the ROM address is an external input signal that is directly accessed. Built-in RO that is uniquely determined by and executable by
A microcomputer for a camera accessory, characterized in that one of M regions is selectively determined.