JPH02119314A - Zero cross voltage detector - Google Patents

Abstract

PURPOSE:To attain the reduction of the number of out-fitted components and the detection of high sensitivity by comparing an input signal after passing a signal level conversion circuit with a comparative output from a comparative voltage generator by using a comparator, and detecting the transition of a comparison result by using a transition detector. CONSTITUTION:The output 63 of the AC voltage source 61 of electrical equipment 60 is inputted to the signal level conversion circuit 42, and is converted to the one of range that can be handled by a microcontroller. The output 64 of the signal level conversion circuit is inputted to the comparator 43, and is compared with the comparative voltage 69 outputted by the comparative voltage generator 44, The output of the comparator 43 is inputted to the transition detector 45. The detection of the zero cross of the input 63 is always performed by the comparative voltage(Vref) detection of the output 64 of the signal level conversion circuit in the inside of the microcontroller. When the output 63 of the AC voltage source of the electrical equipment 60 crosses with a zero voltage, a leading or trailing transition detecting signal WF or VR is outputted from the transition detector 45, thereby, the detection of the zero cross can be performed.

Description

[Detailed description of the invention] [Industrial application field]

The present invention relates to an apparatus for inputting alternating voltage and current waveforms and detecting that the input waveforms cross a zero voltage, that is, a so-called zero cross.

[Prior art]

In a device (zero cross voltage detection device) that detects signal changes from a positive signal to a negative signal and from a negative signal to a positive signal in an input signal, conventionally, as shown in Fig. 1, a C cut circuit 1 and a bias FIG. 2 shows a specific embodiment of the prior art zero-crossing voltage detection device constructed from a stage 3 and an amplification stage 4 inside an integrated circuit. There is an AC voltage source 61 that generates an AC voltage inside the electrical equipment 60, and the electrical equipment 6 detects the zero cross of the AC voltage.
This is an embodiment in which control is performed by sending a signal to the control unit 62 of No. 0. A microcontroller 6, which is an integrated circuit, is used to detect zero crossings. A prior art DC cut circuit 1 is placed between the electrical device 60 and the microcontroller 6, and a prior art bias stage 3 and amplification stage 4 are integrated and contained within the microcontroller 6. The output 63 of the AC voltage tA61 of the electrical equipment 60 is the DC
The C component force is input to the human circuit and converted into a voltage range that can be handled by the microcontroller 6. The DC cut circuit I
The output of is input to the bias stage 3 inside the microcontroller 6. The output of the bias stage 3 is supplied to the amplification stage 4.
is set at the position (operating point) where the gain is greatest. - the deviation of the output signal of the bias stage 3 from the operating point is amplified by the amplification stage 4; The output 5 of the amplification stage 4 is sent to a control section 7 located inside the microcontroller 6. A control signal 67 of the control unit 7 is output from the microcontroller 6 and input to the control unit 62 of the electrical device 60. The control section 62 issues appropriate control signals to control the electrical equipment. A specific example of 1.3 and 4 in FIG. 2 is shown in FIG. 63 is the output of the AC voltage source. Reference numeral 11 denotes a voltage converter that converts the peak voltage of the output 63 of the AC voltage source into a voltage range that can be handled by the microcontroller 6 (usually 0 to 5y). 13 is a capacitor for removing the DC component of the voltage converter output. 30 is a P-channel MO3 for increasing the input impedance of the bias stage 3 without adding an integrated circuit manufacturing process. 31 is an inverter whose input and output are short-circuited for setting the operating point of the amplification stage 4 described in FIG. 40.41 is a high gain inverter for amplifying the deviated voltage when the output of the DC cant circuit 1 deviates from the operating point of the amplification stage 4. 5 is the output of the amplification stage 4. In addition, as a document related to the prior art, rNEC microcomputer synchronized 7'' (ll-nt) 19
There are 85JP and B-423.

[Problem to be solved by the invention]

When zero-cross detection is performed with such a conventional configuration, the following drawbacks occur. (1) External components of an integrated circuit such as a microcontroller, for example, 13 capacitors are required as external components. (2) Due to the input terminal dependence of the resistance value of 30, when the input changes, the resistance value of the P-MOS also changes. In order to obtain high resistance with a diffused resistor, a large area is required. (3) Due to variations in the manufacturing process of integrated circuits, the operating point of the inverter 40 set by the bias stage 3 is not necessarily the point where the inverter 40 has the largest gain. Therefore, the sensitivity of the amplification stage 4 varies depending on the manufacturing process of the integrated circuit. (4) Sensitivity is low, on the order of several hundred 11 Iv. In order to eliminate and improve the drawbacks of the prior art described above, the present invention uses a highly sensitive comparator and transition detector that do not require external components and are not affected by manufacturing process variations. be.

[Means to solve the problem]

In order to solve the problems described above, the zero-crossing voltage detection device of the present invention includes a signal level conversion circuit that converts the amplitude and DC level of an AC signal whose zero point is to be detected into a desired voltage, and a signal level conversion circuit that converts the amplitude and DC level of an AC signal whose zero point is to be detected, and a zero-cross detection control circuit to which an AC signal that is the output of the negative circuit is input, and the zero-cross detection control circuit is a comparison circuit that generates a comparison voltage that is a voltage equal to the DC level voltage of the output of the signal level conversion circuit. a voltage generator; a first switch element that samples the comparison voltage with a first clock pulse; and a second clock pulse that is alternately issued with the first clock pulse and does not overlap with the first clock pulse; a second switch element for sampling the output; a capacitor having one terminal connected to the first and second switch elements and the other terminal connected to the input of the amplifier section; and a capacitor operated by the first clock pulse. a comparator having an amplification section whose operating point is set at a highly sensitive position by an operating point setting section that operates by the second clock pulse and an operating point compensation section that operates by the second clock pulse; and a transition detector for detecting.

[For use]

The present invention provides a signal level conversion circuit 42 as shown in FIG.
After passing through the input signal, the input signal is compared with a comparison voltage from a comparison voltage generator 44 using a comparator 43 and a transition detector 45
This is an input zero-cross detection method that can reduce the number of external components and achieve high-sensitivity detection by detecting the transition of the comparison result. Furthermore, although external components such as large-capacity capacitors have conventionally been required, this method allows for miniaturization, making it possible to construct a high-precision zero-cross detection that can be built into a microcontroller.

【Example】

A specific example in which the present invention is implemented inside an integrated circuit is described in Section 5 U! ! ! Shown in I. In this embodiment, there is an AC voltage source 6I that generates an AC voltage inside the electric device 60, and the zero cross of the AC voltage is detected and a signal is sent to the control unit 62 of the electric device 60 for control. A microcontroller 65, which is an integrated circuit, is used to detect zero crossings.
is used. Comparator 43 and comparison voltage generator 4 of the present invention
4 and a transition detector 45 are integrated and contained in a microcontroller 65. A signal level conversion circuit 42 of the present invention is placed between the electrical equipment 60 and the microcontroller 65. A reference voltage 49 used in the zero-crossing voltage detection device of the present invention is input to the signal level conversion circuit 42 and the comparison voltage generator 44. The output 63 of the AC voltage #61 of the electric device 60 is at the signal level f? The signal is input to the A circuit 42 and converted into a range that can be handled by the microcontroller. The output 64 of the signal level conversion circuit is input to the comparator 43 of the microcontroller 65 and compared with the comparison voltage 69 output by the comparison voltage generator 44. The output of the comparator 43 is input to the transition detector 45. That i! The output of the two-shift ratio detector is sent to the control section 66 of the microcontroller, and the control section 66 is controlled by the control section 66 of the microcontroller. An IO signal 67 is output from the microcontroller and input to the control section 62 of the electrical device 60. The control section 62 issues appropriate control signals to control the electrical equipment. The configuration of the signal level conversion circuit 42 of the present invention is shown in FIG. The signal level conversion circuit 42 is composed of a voltage converter 46 and a shift circuit 50. The voltage converter 46 converts the peak voltage at the input 63 into a voltage range that can be handled by the microcontroller in which the comparator 43, comparison voltage generator 44, and transition detector 45 of the present invention are incorporated. A reference voltage 49 twice the comparison voltage Vref is applied to the shift circuit 5.
It is input to 0. The shift circuit 50 shifts the output 47 of the voltage converter 46 so that it oscillates around the set comparison voltage Vref. The output of the shift circuit 50 becomes the output 64 of the signal level conversion circuit. The operation of the signal level conversion circuit 42 of the present invention is as follows. Input 63 and output 64 of the signal level conversion circuit 42
is shown in FIG. 7, the amplitude of the input waveform 63 is positive and negative 100V,
It is assumed that the voltage range that the microcontroller 65 can handle is from Ov to 5V. The output 63 of the AC voltage source of the electrical equipment 60 is converted by the voltage converter 46 into an AC voltage 47 with an amplitude of positive and negative 5V. When the input 63 crosses zero voltage, the output 47 of the voltage converter also crosses zero voltage. Vref is a comparison voltage serving as a reference for comparison. The reference voltage 49 is a voltage 2Vre4 which is twice Vref. This Vref can be set by the user. In this embodiment, Vref is assumed to be 3V. The shift circuit 50 is composed of resistors R, 11° having the same abrasive value. Resistors are connected in series, and an output 47 (Vin) of a voltage converter and a reference voltage 49 (2Vref) are applied to both ends of the resistors, respectively. Assuming that the output 64 (Vi) of the shift circuit is taken from the midpoint of the series resistor, Vi can be calculated as follows. 2Vref-Vin Vin In this example, since Vref is 3v, Vi is expressed by the following equation. 1n Vi =3ν+-・・・・・・・・・・・・・・・・・・
...(2) According to equation (2), when Vin reaches a positive peak voltage of 5v, Vi becomes 5.5v and Vin
When becomes a negative peak voltage of 5v, Vi becomes 0.5v. The waveform of Vi, that is, the output 64 waveform of the signal level conversion circuit is shown in FIG. When Vin crosses zero voltage OV, Vi becomes 3ν and Vre
It will intersect with 4. Therefore, when the input 63 crosses zero voltage, the output 64 (Vi) of the signal level conversion circuit becomes V
It will intersect with ref. In other words, if ', N' n and ρ' can be detected at the point where the output 64 (Vi) of the signal level conversion circuit 42 intersects with vref, the AC voltage S6 of the electrical equipment 60 can be detected.
At the zero cross point of the output 63 of t, 1. Plow, n and ρ can now be detected. The configuration of the comparison voltage generator 44 of the present invention will be explained. The reference voltage 49 (2Vref) is applied to the comparison voltage generator 44.
A voltage divider is placed between the reference voltage 49 (2Vref) and the ground voltage Ov of the microcontroller 65. The voltage divider consists of resistors R, t, R, with the same resistance value. The comparison voltage Vref is connected in series with R,,I? , and output to the comparator 43 of the present invention. In this example,
) fE'$ Voltage 49 is 6V, so is it a resistor? :
If the ratio of the resistance values of 'ath and R4 is 1:1, Vref will be 3V. The configuration of the comparator 43 of the present invention is shown in FIG. It consists of an AC amplification type titanium comparator. 72 is a switch 1173 is a switch 2.75 is a capacitor, 7
7 is an amplification section, 78 is an operating point setting section, and 79 is a compensation section. The switch 1 and the operating point setting section 78 are driven by the clock 1, which is the internal clock of the microcontroller 65, and the switch 2 and the compensation section 79 are driven by the clock 2, which is the internal clock of the microcontroller. As the capacitor 75, a small capacitance that can be made inside an integrated circuit such as a microcontroller is sufficient. Of course, a capacitor using a depressed tandem MOS transistor may also be used. The operation of this configuration is as follows. The comparison voltage generator 44
The output 69 (Vref) of the signal level conversion circuit 42 and the output 64 (Vi) of the signal level conversion circuit 42 are clock 1 and clock 2, respectively.
and is input to the comparator 43. The operating point of the amplifying section 77 is set by the operating point setting section 78. The compensating section 79 has a mirror capacitance l of the amplifying section (the capacitance f between the source, train, and gate of the MOS transistor).
This is a circuit for removing the influence caused by f1), etc. A capacitor 75 between the input switch and the amplifier section is charged during clock l by the output 69 (Vref) of the comparison voltage generator and during clock 2 by the output 64 (Vi) of the signal level conversion circuit. be done. The charge difference due to the voltage difference between the two voltages (Vref and Vi) is amplified by the amplifier section, and a comparator output 68 (Vc) is output. A timing chart of clock 1 and clock 2 used in the comparator 43 is shown in FIG. 80 and 81 are times when clock 1 and clock 2 become active, respectively. Clock 1 and clock 2 do not overlap each other. 82 is the non-overlap time. A timing chart of the potential of the capacitor 75 of the comparator 43 is shown in FIG. 10.11. During the time 80 that clock 1 is active, switch 1 is turned on and switch 2 is turned off so that the output of the comparison voltage generator V r
ef is sampled and the input 74 of the capacitor 75
(point f) is the 76th axis point) and is charged and discharged to a potential corresponding to Vref. During the time 81 when clock 2 is active, switch l is turned off, switch 2 is turned on, and the output 64 (Vi) of the signal level conversion circuit is
is sampled, and point f is charged and discharged to a potential corresponding to 'ζv1 with respect to point g. FIG. 10 shows potential changes at point f when Vi is larger than Vref. Vi is V
FIG. 11 shows the change in potential at point f when the voltage is smaller than rer. The amplification section of the comparator amplifies and outputs a change in potential at point g on the output side due to a change in potential at point f on the input side of the capacitor. The operating point V- of the amplifier section is set by the operating point setting section while the clock l is active (80). By setting the operating point at the point where the gain is the highest in the amplifying section, the amplifying section can respond sensitively to the minute potential difference at point g on the output side of the capacitor, and a highly sensitive amplifying section can be obtained. Since the operating point setting section is driven by the clock 1, when the input potential of the amplifying section is switched from OFF to ON of the clock 1 due to the influence of the Miller capacitance, etc., it increases by an amount corresponding to the Miller capacitance, and the potential of the input of the amplifier section increases by an amount corresponding to the Miller capacitance. When switching from on to off, it decreases by an amount corresponding to the mirror capacitance. In order to eliminate the influence of the mirror capacitance and increase accuracy, a compensator driven by clock 2 was provided. clock 2 is clock l
This means that for every off-to-on or on-to-off switching of clock l, there is always a corresponding on-to-off switching or off-to-on switching of clock 2. Therefore, the potential fluctuation error at the input end of the amplification section due to the switching of the clock 1 is canceled out and compensated for by the switching of the clock 2. The relationship between the potential change of the capacitor and the comparator output 68 (Vc) with respect to clocks 1 and 2 is shown in FIG. 10.11. If Vi is greater than V ref, then while switch 2 is active (81), as shown in FIG.
, the comparator output Vc changes from the operating point Vw of the amplifier section to a low voltage corresponding to a logical value of 0. When vl is smaller than Vref, as shown in FIG. 11, Vc changes from the operating point of the amplifier section to a high voltage corresponding to a logical value of one. The configuration of the transition detector 45 of the present invention is shown in FIG. Comparator output 68 (VC) is clock 1 and clock 2
is sampled by and stored in the storage section 89 of the transition detector 45. The comparator output 6B (Vc
) is decoded by the decoder 90. The output of the decoder 90 becomes the output of the zero-cross voltage detection device of the present invention. The operation of the transition detector 45 is shown in FIGS. 13 and 14. FIG. 13 shows an example in which the output 64 (V i ) of the signal level conversion circuit transitions from a voltage smaller than V ref to a voltage larger than V ref. Comparator output 68 (Vc) is the 13th
Changes as shown in the figure. The value of Vc sampled at clock 2 is the logical value 1 at the -th time, and is the logical value 0 at the second time. The sampled Vc value is decoded by a decoder and a rising transition detection signal 8
8(V, ) becomes active. Vi'h (Vrer
An example of transition from a larger voltage to a voltage smaller than Vref is shown in FIG. Comparator output 68 (Vc) is the 14th
Changes as shown in the figure. The value of VC sampled at clock 2 is the logical value O at the -th time, and is the logical value l at the second time. The sampled Vc value is decoded by a decoder and a falling transition detection signal 8
7 (VF) becomes active. A specific configuration of the transition detector 45 of the present invention is shown in FIG. Note i, the α section 89 consists of a latch element 91 (latch l) and a latch element 92 (lunch 2), and the decoder 90
consists of a NAND logic element 94, a NOR logic element 95, and an inverter 93 (inν2). Comparator output 68 (V
c) is sampled by clock 2 and latch l
remembered by. The negative output q, of latch l is sampled by clock 1 and stored by latch 2. The negative output σ1 of the launch 1 and. The negative output ζ2 of launch 2 is decoded by a decoder,
A falling transition detection signal a7 (vr) or a rising transition detection signal 88 (VR) is output. When the output 64 (Vi) of the signal level conversion circuit transitions from a voltage lower than Vref to a voltage higher than Vref,
Comparator outputs VC, V, , and ■ are output as shown in FIG. The output 64 (Vi) of the signal level conversion circuit changes from a voltage higher than Vref to a voltage lower than Vref X!
When transferring, the comparator output ■. , ■4. and V, l is the first
The output will be as shown in Figure 4. As described above, the zero cross detection of input 63 is as follows:
Inside the microcontroller, it is always V ref cross detection of the output 64 (Vi) of the signal level conversion circuit. When the output 63 of the AC voltage source of the electrical equipment 60 crosses zero voltage, the a-thread detector 45 of the present invention detects ■ or ■.
. is output and zero crossing can be detected. In this embodiment, Vref is set to 3V, but of course Vref is set to Vc.
Even if the voltage is 2.5V, which is half of c (5V), the zero cross of the input 63 can be detected without any problem. The output V or ■ of the transition detector 45 is sent to the control section of the microcontroller, and the control signal 67 is sent to the control section 6.
6 and is input from the microcontroller to the control section 62 of the electrical equipment. A control signal is output from the control section 62, and appropriate control is performed on the zero cross. FIG. 16 shows a modification of the present invention, which differs from the comparator in FIG. 8 in that the output 64 (Vt
) and the switch 2, an amplifier 96 is inserted between the switch 2 and the switch 2. Vi is amplified by the amplifier 96 and sampled by clock 2 and switch 2. In the present invention, the sensitivity of input zero-cross detection is as follows:
It varies depending on the slope when intersecting ref. The larger the slope, the higher the sensitivity, and the smaller the slope, the worse the sensitivity. This is due to the offset of the AC amplification type Chomba comparator. Vi is Vre
If the voltage difference with f is too small, even if it is amplified by the amplification section of the comparator, the logic value will not be 1 or 0 from the perspective of the storage section of the transition detector 45, so it will not be recognized as a transition. That's because there isn't. In this modification, each time the amplifier 9G is used, vl
Even if the gradient is small, it is amplified by the amplifier 96 and high sensitivity is always achieved.

【Effect of the invention】

The signal level conversion circuit 42 of the present invention does not require a large-capacity capacitor as an external component, and the comparator 43, comparison voltage generator 44, and transition detector 45 of the present invention are easily incorporated into an integrated circuit, and a 5V single Since zero cross detection can be performed using the power supply, it is very effective in reducing the number of system components, improving reliability, and reducing costs.

[Brief explanation of the drawing]

Figure 1 is a block diagram of a conventional zero-cross voltage detection device.
FIG. 2 is a block diagram of an embodiment of a conventional zero-cross voltage detection device, FIG. 3 is a circuit diagram of a specific example of a conventional zero-cross voltage detection device, and FIG. 4 is a block diagram of a zero-cross voltage detection device of the present invention. , FIG. 5 is a block diagram of an embodiment of the zero-cross voltage detection device of the present invention, FIG. 6 is a block diagram of the signal level conversion circuit of the present invention, and FIG. 7 is a diagram of the input and output of the signal level conversion circuit of the present invention. Timing chart,
FIG. 8 is a block diagram of the comparator of the present invention, FIG. 9 is a timing chart of clock 1 and clock 2 used in the comparator and transition detector of the present invention, and FIG. 10 is a signal level conversion circuit of the present invention. FIG. 11 is a timing chart of the comparator output Vc when the output voltage i is higher than the comparison voltage Vref, and FIG. Chart, FIG. 12 is a block diagram of the transition detector of the present invention, and FIG. 13 is the output V of the signal level conversion circuit of the present invention.
FIG. 14 is a timing chart of the comparator output 'Jc and the transition detection signals V, , V, when i transitions from a voltage lower than the comparison voltage Vref to a voltage higher than Vref, and FIG. 14 shows the timing chart of the signal level conversion circuit of the present invention. The output Vi is the comparison voltage ■r
Comparator output Vc and transition detection signal ■ when transitioning from a voltage higher than ef to a voltage lower than Vref. FIG. 15 is a circuit diagram of the transition detector of the present invention, and FIG. 16 is a block diagram of a modified example of the comparator of the zero-cross voltage detection device of the present invention.

Claims (1)

[Claims] It consists of a signal level conversion circuit that converts the amplitude and DC level of an AC signal whose zero point is to be detected into a desired voltage, and a zero cross detection control circuit to which the AC signal that is the output of the signal level conversion circuit is input. The zero cross detection control circuit includes a comparison voltage generator that generates a comparison voltage having a value equal to the DC level voltage output from the signal level conversion circuit, and a first switch that samples the comparison voltage using a first clock pulse. a second switching element that samples the output of the signal level conversion circuit with second clock pulses that are alternately issued with the first clock pulses and do not overlap; a capacitor connected to the second switch element and having the other terminal connected to the input of the amplifier section; an operating point setting section operated by the first clock pulse; and an operating point compensating section operated by the second clock pulse. 1. A zero-crossing voltage detection device comprising: a comparator having an amplifying section whose operating point is set at a highly sensitive position; and a transition detector detecting a zero point based on the output of the comparator.