JPH01168115A - Waveform generator - Google Patents

Abstract

PURPOSE:To generate various kinds of and diversified waveform patterns through the mere access of a memory by providing a memory deciding the leading edge and trailing edge shapes of a waveform and a timing pulse generating circuit selecting the leading edge and trailing edge pulses from the clock pulse whose phase differs depends on the data in the memory. CONSTITUTION:A memory storing a timing data to decide the leading edge and trailing edge shapes of the waveform corresponding to the waveform to be generated in advance in the inside and a timing pulse generating circuit 22 selecting the leading/trailing edges pulse from the clock pulse whose phase differs based on the data in the memory are provided in the waveform generator. As a result, the waveform control circuit is constituted by a simple memory controlling the leading/trailing edges of the waveform and the memory is accessed by the pattern data from the pattern generator 12. Thus, various kinds of and diversified waveforms corresponding to the various waveform generating mode can be generated.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a waveform generator, and more specifically,
The present invention relates to a waveform generator that generates a test waveform pattern for IC testing corresponding to each C test pin.

[Prior Art] In an IC testing system, a multi-bit test waveform pattern necessary for performing a performance one-function test of an IC is automatically generated according to a test pattern program or the like.

Conventionally, in such a test waveform pattern generator, necessary data for each pin of an IC is extracted from pattern data created by a pattern generator and clock pulses created by a timing clock generator. A method is adopted in which a predetermined waveform is generated by selecting one, which is sent to a drive circuit, and its output is level-converted and supplied to a predetermined IC pin.

As an example, a specific circuit as shown in FIG. 3 can be cited.

1 is a pattern generator, which usually includes ROM and RAM.
It consists of an instruction memory, a program counter, a controller, etc., and generates addresses for the device under test (hereinafter referred to as CUT), generates data such as pattern data and expected value data, and also sends read/write control signals to the CUT. Occur.

For example, if a predetermined address in the instruction memory of the pattern generator 1 is accessed,
Pattern data is generated, and the data selector 2 selects pattern data as shown in FIG. 4(a) at a predetermined timing and sends it to the waveform formatter 3.

On the other hand, the timing clock generator 4 is configured as shown in FIG. 4(b).
, the clock pulses having different phases as shown in timing waveforms (1) and (2) in (C) are generated sequentially, and one of them is selected by the timing selector 5 in the evening and sent to the waveform formatter 3. Ru.

For example, if timing waveforms (1) and (2) are selected, then according to these, (
A test waveform pattern of a pulse waveform rising and falling at the timing shown in d) is generated as the output of the waveform formatter 3.

The output signal of this waveform formatter 3 is sent to the driver 7 of the next stage drive circuit 6 as a test waveform pattern. Then, through the drive circuit 6, a waveform pattern corresponding to the output signal of a predetermined voltage is transmitted to the IC to be tested inserted into the socket on the 11 driver side, for example.
to a specific pin.

Note that %7a + 7b is a basic voltage source module that supplies the driver 7, and a stable voltage VIH (high level set voltage value) is provided by these modules.

VIL (low level set voltage value) is supplied to the driver 7.

Here, in the conventional waveform formatter 3, RZ,
A waveform control circuit that generates fixed waveforms such as NRZ and EXOR, and waveforms such as RTWC (real-time waveform control) is provided, and generates waveforms such as RZ, NRZ, EXOR, RTWC, etc. from given pattern data. Waveform generation modes corresponding to these are provided and can be selected.

[Problems to be solved] By the way, as semiconductor integrated circuits become more sophisticated, chips with various functions are integrated inside them, or many functional blocks are integrated into one chip. It's becoming. Therefore, when performing a functional test, etc., the number of test items increases and the types of waveforms generated also increase, and the generated waveform patterns are becoming more complex and diverse.

Accordingly, the number of waveform control circuits provided in the waveform formatter 3 has increased, become more diverse, and become more complex.

The present invention solves the problems of the prior art, and provides a waveform generator capable of generating a wide variety of waveforms corresponding to various waveform generation modes with a simple circuit configuration. With the goal.

[Means for Solving the Problems] The configuration of the waveform generator of the present invention for achieving such an object includes a pattern generator, and a plurality of clock pulses having different phases at a predetermined period. a timing clock generator that generates signals corresponding to the respective timing clocks;
A memory for storing data having a plurality of bits corresponding to the rising edge of the generated waveform and a plurality of bits corresponding to the falling edge of the generated waveform respectively assigned to each of the plurality of phases; A gate signal is obtained, and a specific clock pulse is obtained from the clock pulses of each phase corresponding to the rising and falling edges of the generated waveform, and the first pulse signal and the second pulse signal are generated correspondingly to the rising and falling edges of the generated waveform.
a timing pulse generation circuit that generates pulse signals respectively, and a waveform that causes the generated waveform to rise or fall in response to the first pulse signal, and causes the generated waveform to fall or raise \γ in response to the second pulse signal. The memory is accessed by a signal from the pattern generator and the data is sent to the timing pulse generation circuit.

[Operations] In this way, there is a memory that stores timing data that determines the rising and falling forms of a waveform that corresponds to the waveform that should be generated in advance inside the waveform generator, and a clock pulse that has a different phase depending on the data in this memory. By providing a timing pulse generation circuit that selects rising and falling pulses from 0 to 1, a wide variety of waveform patterns can be generated simply by accessing the memory.

As a result, the waveform control circuit controls the waveform's rise and \γ-
can be configured by the rlt-memory that controls the edge,
There is no need to provide many control circuits corresponding to the types of waveform generation modes as in the conventional case, resulting in a simple circuit. Moreover, it is possible to generate waveforms in any waveform form that rises or falls in response to a clock pulse, and can be set using data stored in memory, thus realizing a waveform generator with a high degree of freedom. This eliminates timing skew deviations for each generated waveform.

Furthermore, since the memory is accessed using pattern data from the pattern generator, if you store waveform data in different formats in different address areas of the memory, you can change the waveform format in real time by simply changing the access area. It is easy to sequentially generate waveforms.

[Example 1] Hereinafter, an example of the present invention will be described in detail with reference to the drawings.

FIG. 1 is a block diagram of an embodiment in which the waveform generator of the present invention is applied to a waveform generator for a conductor tester, and FIG. 2 is a timing chart for explaining the waveform generation operation. It is.

In FIG. 1, 10 is a CPU, which sets a program necessary for pattern generation in a pattern generator 12 via an interface 11, and generates a timing clock 7.
Set the necessary timing generation data in 9113. The data from the pattern generator 12 and timing clock generator 13 are sent to each waveform formatter of the waveform generator 17, and the output of the waveform formatter is input to the driver circuit of the pin electronics 18, and then passed through the drive circuit. Test waveforms and the like are output to corresponding pins of the CUT 19.

17a, 17b, 17c, see are respective waveform formatters, and 6a, 8b + 6c +
... are drive circuits that receive the waveform patterns output from each of these waveform formatters. Here, since each waveform formatter has a similar configuration, the waveform formatter 17a is representative.
The specific internal configuration will be shown below, and the configuration and operation will be explained using the waveform formatter 17a as a representative, and other components will be omitted.

In addition, 20 is a test voltage setting circuit, and
1) Generates data for setting the bias voltage of the UT 19, the level of the test pattern, etc. using the data from the DUT 19. These are supplied to the pin electronics 18, etc., respectively.

The pattern data generated from the pattern generator 12 and the clock pulses of each phase of the timing clock generator 13 are generated by the respective waveform formatters 17a, 17b, 17.
c and ohm, respectively. Then, some of the pattern data is input to the waveform formatter 17a, and the signal is applied as an address signal to the address input terminal of the timing data memory 21 of the waveform formatter 17a.

This address signal is, for example, 2 or 3 bits of the pattern data, and a specific address of the timing data memory 21 is accessed by these 2 or 3 bits, and the data read from that address is used to generate a timing pulse. The signal is sent to circuit 22.

The timing pulse generation circuit 22 receives data from the timing data memory 21 and the timing clock generation circuit 11.
3, and generates a rising pulse signal and a falling pulse signal under the AND condition of these data and the clock pulses, and outputs the set terminals S and 3 of the flip-flop 23. Each signal is sent to the reset terminal R.

This timing pulse generation circuit 22 is an AND circuit 22a for generating repulses at the rising edge of the clock pulses of each phase obtained from the timing clock generator 13, each of which is received by one human input.

22 by 22 C* . . . and an AND circuit 22 by 22 C* 22m for generating a falling pulse, which receives clock pulses of each phase at one input.

22J! , φ...

Each bit signal of the data from the timing data memory 21 is assigned to the other input of each AND circuit, corresponding to each phase, and the bits of each digit correspond to each other. It is powered by the other side of the phase. As a result, the clock pulse of a certain phase and each bit of the digit corresponding to that phase of the timing data memory 21 are both set to "1" (negative logic) in response to the rising edge and the rising edge of the generated waveform, respectively. Sometimes, when both become "0"), the clock pulse of that phase is selected and the rising pulse signal (TR) or the falling pulse signal (TR) of the corresponding AND circuit is selected.
TF) respectively.

These rising pulse signals (TR) and falling pulse signals (TF) are generated in response to the clock pulses selected by each data bit, and are sent to the set terminal and reset terminal r of the flip-flop 23, respectively. Then, the Q output of the flip-flop 23 is caused to rise or fall depending on the pulse signal on the input side. Then, this Q output is outputted as a test waveform pattern to the drive circuit 6a, and sent to 0UT19 via this drive circuit 6a.

Here, the data stored in the timing data memory 21 is data that determines the rising edge or falling timing of the waveform to be generated.

The structure of one data consists of a group of bit data assigned to each phase of timing clock generation 'a13 in response to the rising edge of the generated waveform, and a group of bit data assigned to each phase in response to the falling edge of the generated waveform. Consists of a group of allocated bit data. Such data is set in advance from the CPU 10 via the interface 11 before or at the start of the test, and depending on the contents of the set data, the rise and/or rise of the generated waveform is determined. The gap can be set freely.

Therefore, data corresponding to the waveform mode required for testing is
The timing data memory 21 is set in advance from PU10, and the timing data memory 2 is set in advance in accordance with the generation timing of pattern data of the pattern generator 12.
1 and flip-flop 2 to access a wide variety of waveforms.
It can be generated from 3.

Assume now that the number of clock pulses with different phases generated from the timing clock generator 13 is three, and the unit of data read out from the timing data memory 21 is six pits (according to the clock pulse of each phase, the number of clock pulses on the rising side bit, 3 bits on the falling side). The relationship between the generated pattern waveform and the generated waveform mode in the flip-flop 23 under these conditions is shown in FIG. 2(a).
.

This will be explained according to (b).

FIG. 2(a) shows a case where a generated waveform pattern is converted into RZ, and the original data pattern to be generated is shown in FIG. 2(a). And three clock pulse forces generated from the timing clock generator 13 (b)
1 (c), (d) ACLK, BCL,
There are three clock pulses of CCLK, and (e) shows the RZ waveform for the data pattern (a).

Then, the timing data memory 21 is transferred to (to).
This is 6-bit data stored in .

As is clear from this timing chart, when the pattern data is "°1", in order to generate the corresponding RZ pulse signal, the waveform must be generated using BCLK as the rising timing and CCLK as the falling timing. I know it's good.

Further, when the pattern data is "0", it is not necessary to select three clock pulses.

Incidentally, of the 8-bit data stored in the timing data memory 21, the bits in the 20th, 21st, and 22nd digit positions are designated as ACLK and BCLK, respectively.

If it is assigned to the rising timing bit of CCLK, when the corresponding bit is set to "L", a rising pulse signal (TR) is generated from the timing pulse generation circuit 22, and the corresponding bit is set to "L". “O
”), the γ1] edge pulse signal will not be generated.Similarly, of the 6-bit data, the bits at each digit position of 23, 29, and 25 are ACLed respectively.
K, BCLK.

If it is assigned to the falling timing bit of CCLK, when the corresponding bit is set to "1", a falling pulse signal (TF) is generated from the timing pulse generation circuit 22, and the corresponding bit is set to "1". 0
”, no rising pulse signal is generated.

When each bit position of data is assigned in correspondence with a clock pulse in this way, the data (100010) shown in (f) of FIG. 2(a) is stored at a specific address in the timing data memory 21. If so, by accessing that address, it is possible to generate the RZ waveform shown in FIG. Furthermore, if the data (000000) is stored in another specific address of the timing data memory 21,
By accessing that address, pattern data “0” is created.
It is possible to generate the RZ waveform shown in FIG.

What is shown in FIG. 2(b) is a case where an RTWC waveform is generated, and similarly to the above, the data pattern is as shown in (a), and three clock pulses generated from the timing clock generator 13 are used. ga(b),(c),(d)
ACLK, BCLK.

CCLK, and (e) shows the RTWC waveform for the data pattern (a). 6-bit data of the timing data memory 21 is shown in (v). In addition, "N" in (a) means a "0" data pattern in a specific measurement state, "up" means a "1" data pattern in a specific measurement state, and R
As TWC mode, such data pattern “0”
, '1'', different types of waveforms can be successively generated in real time.

Here, in response to the generation of pattern data, as shown in FIG.
) The first two data shown in (to) (010000)
, (000010) are sequentially read from the timing data memory 21, the waveform up to the first rising state shown in (e) is set, and (000010) is set as the next data.
10100) is read, the next falling edge and Xr
”-gari is set. Furthermore, (101010) is read and the next falling, rising, and falling edges are set.

Therefore, if each of these data is sequentially stored in each address of the timing data memory 21, each address of the timing data memory 21 is sequentially accessed as pattern data is generated, and the waveform pattern (e) is generated.

Here, the first two data (which may be two or more) and the last two data (which may also be two or more) are stored in different address areas of the memory. If you memorize it, by switching the address information of the upper digit that specifies the storage area to “1” or “0”,
RTWC mode (access a specific storage area with the 1st digit “1”) or normal fixed waveform mode (access the specific storage area with the 11th digit “0”)
You can easily select whether to access the normal storage area as ``ordinary storage area''.

The above example is just an example, and if you use access addresses, you can generate various waveforms with many combinations.
If there is an address access at a timing when there is no need to generate a waveform, the stored data is set to (0) as a condolence.
00000).

As explained above, in the embodiment, the signal is handled as a positive logic, but this may also be a negative logic, and the timing pulse generation circuit handles the signal under the AND condition that the data and clock pulse are valid. It may be either positive or negative, or a mixture of these may be used. Therefore, the logic circuit can take various forms.

In addition, in the embodiment, the rising pulse signal of the timing pulse generation circuit is inputted to the set terminal of the flip-flop, and the falling pulse signal is inputted to the reset terminal of the 7 flip-flop, but this can be done manually instead. It is also possible to generate an inverted waveform. Note that the flip-flop is not limited to this, and any general waveform generating circuit can be used. Further, it goes without saying that the timing data memory includes one composed of registers.

In the embodiment, the application pattern to OUT is mainly explained, but it goes without saying that this can be similarly applied to the case of generating an expected value.

Furthermore, although the description focuses on a waveform generator for a semiconductor tester, the present invention is not limited to semiconductor testers.

[Effect of the invention] As can be understood from the above explanation, this invention has the following effects:
Inside the waveform generator, there is a memory that stores timing data that determines the rising and falling forms of a waveform that corresponds to the waveform that should be generated in advance, and the data in this memory allows the rising and falling pulses to be generated from clock pulses with different phases. By providing a timing pulse generation circuit that selects a timing pulse generation circuit, a wide variety of waveform patterns can be generated simply by accessing the memory.

As a result, the waveform control circuit can be configured with a single memory that controls the rise and rise of the waveform, and there is no need to provide many control circuits corresponding to the types of waveform generation modes as in the past, resulting in a simple circuit. . In addition, it is possible to generate waveforms in any waveform form that rises or falls in response to a clock pulse, and since it can be set using data stored in memory, a waveform generator with a high degree of freedom can be realized. Timing skew deviation during wave cutting is also eliminated.

Furthermore, since the memory is accessed using pattern data from the pattern generator, if you store waveform data in different formats in different address areas of the memory, you can change the waveform format in real time by simply changing the access area. It is easy to sequentially generate waveforms.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of an embodiment in which the waveform generator of the present invention is applied to a waveform generator of a semiconductor tester.
The figure is a timing chart for explaining the waveform generation operation, and FIG. 3 is a block diagram of a conventional waveform generator.
FIG. 4 is a timing chart for explaining the waveform generation operation. 1.12...Pattern generator, 3+ 17 a-17b-17c ”・Waveform formatter, 6.6 a * 8 b + 6 c ”・
Drive circuit, 10...CPU% tt...Interface, 13...Timing clock generator, 14
...Instruction memory section, 15...Program counter, 16...Controller, 17...Waveform generator, 18
...Pin electronics, 19.. Device under test (DUT), 20.. Test voltage generation circuit, 21.. Timing data memory, 22.. Timing pulse generation circuit. Patent Applicant [Representative of 1 Ritsu Denshi Engineering Co., Ltd. Patent Attorney Kaji Yama Tsuyoshi This patent attorney is Yamaki Fujio Figure 2 (a) (b) (to) 'E5 up ° fr buri +010000), (0
000101, [0101001, (+010103r
9/Mori Figure 4 (d) Nigepay-fY-11

Claims (2)

[Claims] (1) a pattern generator; a timing clock generator that generates clock pulses having different phases at a predetermined period in correspondence with the plurality of different phases; a memory that stores data having a plurality of bits corresponding to the rising edge of the generated waveform and a plurality of bits corresponding to the falling edge of the generated waveform, each of the plurality of bits being a gate signal, and a clock pulse of each phase; a timing pulse generation circuit that obtains specific clock pulses from among the clock pulses corresponding to rising and falling edges of a generated waveform, respectively, and generates a first pulse signal and a second pulse signal in response to the clock pulses; a waveform generation circuit that raises or lowers a generated waveform in response to a first pulse signal and lowers or raises a generated waveform in response to a second pulse signal, and the memory includes a waveform generation circuit that raises or lowers a generated waveform in response to a second pulse signal; A waveform generation device, characterized in that the data is accessed by a signal and sent to the timing pulse generation circuit. (2) The waveform generator according to claim 1, wherein the data stored in the memory is set in advance from an arithmetic processing unit of a semiconductor tester according to a generated waveform mode.