JPH01155663A - Amorphous silicon thin-film transistor - Google Patents
Amorphous silicon thin-film transistorInfo
- Publication number
- JPH01155663A JPH01155663A JP31402287A JP31402287A JPH01155663A JP H01155663 A JPH01155663 A JP H01155663A JP 31402287 A JP31402287 A JP 31402287A JP 31402287 A JP31402287 A JP 31402287A JP H01155663 A JPH01155663 A JP H01155663A
- Authority
- JP
- Japan
- Prior art keywords
- layer
- film
- amorphous silicon
- silicon thin
- photocurrent
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 229910021417 amorphous silicon Inorganic materials 0.000 title claims abstract description 21
- 239000010409 thin film Substances 0.000 title claims abstract description 10
- 239000010408 film Substances 0.000 claims abstract description 33
- 239000000758 substrate Substances 0.000 claims abstract description 11
- 239000012535 impurity Substances 0.000 claims 2
- 238000000034 method Methods 0.000 abstract description 10
- 239000011521 glass Substances 0.000 abstract description 3
- 238000001259 photo etching Methods 0.000 abstract description 2
- 238000005268 plasma chemical vapour deposition Methods 0.000 abstract description 2
- 230000015572 biosynthetic process Effects 0.000 abstract 1
- 238000005530 etching Methods 0.000 description 9
- 238000009826 distribution Methods 0.000 description 8
- 229910052581 Si3N4 Inorganic materials 0.000 description 6
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 6
- 238000001312 dry etching Methods 0.000 description 5
- 239000004973 liquid crystal related substance Substances 0.000 description 3
- 230000000694 effects Effects 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- 238000004544 sputter deposition Methods 0.000 description 2
- 238000010586 diagram Methods 0.000 description 1
- 230000008034 disappearance Effects 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 238000002161 passivation Methods 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 235000015067 sauces Nutrition 0.000 description 1
- 238000007740 vapor deposition Methods 0.000 description 1
Landscapes
- Thin Film Transistor (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は、液晶表示パネル等に用いる非晶質シリコン薄
膜トランジスタ(以下a 5iTFTと略称する)に
係り、特にバックライトなどの照明により発生する光電
流の低減に好適なa −S i TFTに関する。Detailed Description of the Invention [Field of Industrial Application] The present invention relates to an amorphous silicon thin film transistor (hereinafter abbreviated as a5iTFT) used in liquid crystal display panels, etc. The present invention relates to an a-S i TFT suitable for reducing current.
従来の液晶表示パネル用a −S i T F Tは、
特開昭58−148458号に記載のように、a−8i
(iM)の膜厚が2000人程度ある。このa −5i
TFTが構成されている基板の裏面から光を照射した場
合、ゲート電極近くのa−8iに光があたりホールが発
生し光電流が流れる@a−siの膜厚が500Å以上に
厚くなると光電流は1O−10A程度以上となり、a
−S i T F Tの○N/○FF比が小さくなりス
イッチング素子として充分な機能をはたせなくなる。The conventional a-S i T F T for liquid crystal display panels is
As described in JP-A-58-148458, a-8i
(iM) has a film thickness of about 2,000 people. This a-5i
When light is irradiated from the back side of the substrate on which the TFT is constructed, the light hits the a-8i near the gate electrode, holes are generated, and a photocurrent flows. When the film thickness of @a-si becomes 500 Å or more, the photocurrent increases. is about 1O-10A or more, and a
-The ○N/○FF ratio of S i T F T becomes small, and it becomes impossible to perform a sufficient function as a switching element.
上記従来技術は、上部光に対しては遮光膜を設けて遮光
対策を行なっていたが、下部光に対する配慮がなされて
いなかった。そのためにバックライトなどによりa −
S i T F Tに大きな光電流が発生する。In the above-mentioned conventional technology, a light shielding film is provided to block light from the upper side, but no consideration is given to the lower light. Therefore, a −
A large photocurrent is generated in S i T F T .
第2図に従来のa 5iTFT断面図を示す。FIG. 2 shows a cross-sectional view of a conventional a5i TFT.
TPT素子が構成されている基板上部からの光に対して
は金属膜による遮光膜8が設けられている。A light shielding film 8 made of a metal film is provided against light from the upper part of the substrate on which the TPT element is formed.
しかし基板裏面からの光(液晶表示用としてケイ光灯な
どのバックライトを使用する)に対してはなんら有効な
対策がなされていない。そのためにゲート電極6付近を
通過した光9がa −S i 4に照射され、それが原
因で光電流が発生するaa−8i(i層)膜厚が200
0人では〜×1O−9A程度の光電流が発生する。この
発生する光電流を小さくする方法としては、a −S
i膜を薄く(500Å以下)する事も考えられる。However, no effective measures have been taken against light from the back surface of the substrate (a backlight such as a fluorescent lamp is used for liquid crystal display). For this reason, the light 9 that has passed near the gate electrode 6 is irradiated onto the a-S i 4, which causes the aa-8i (i layer) film thickness, which generates a photocurrent, to be 200 mm.
For 0 people, a photocurrent of about 10-9 A is generated. As a method to reduce this generated photocurrent, a -S
It is also conceivable to make the i-film thin (500 Å or less).
第3図にa −S i膜厚と発生する光電流IOの関係
を示す。a−8iの膜厚が200人程度になると光電流
は約1O−11A になることがわかる。FIG. 3 shows the relationship between the a-Si film thickness and the generated photocurrent IO. It can be seen that when the film thickness of a-8i becomes about 200, the photocurrent becomes about 1O-11A.
このようにa −S iの膜厚を500Å以下にするこ
とにより光電流の発生を小さくする事はできるが、チャ
ネル上部のn層を除去する工程においてはn / i層
の選択性が小さく(ドライエツチングで3倍以下)、大
面積の基板においてはエツチング分布、膜厚分布などが
相互に関係しn層除去と同時にi層もオーバエッチされ
事実上は非常に困難である。これをさけるためn層とi
層の間にストッパー層を入れてエツチングを行なう方法
などが実用化されている。これはi層を形成した後でチ
ャネル上部に窒化シリコン膜でストッパー層を形成し、
その上にn層を形成する。n層と窒化シリコンの選択性
は大きいので、n層を除去する時に窒化シリコン膜が下
部のi層をエツチングからまもる働きをする。そのため
大面積においても1層膜厚を薄くすることができる。し
かしこの方法は、a −S i上の窒化シリコンをパタ
ーン化する時にa −S iがエツチングされることや
、プラズマCVDの工程が増加しプロセスが複雑化する
などの問題点があった。Although it is possible to reduce the generation of photocurrent by reducing the a-Si film thickness to 500 Å or less, the selectivity of the n/i layer is low in the process of removing the n layer above the channel ( In dry etching, the etching distribution, film thickness distribution, etc. are interrelated, and the i-layer is over-etched at the same time as the n-layer is removed, making it extremely difficult to remove the n-layer. To avoid this, the n layer and i
A method of etching by inserting a stopper layer between the layers has been put into practical use. After forming the i-layer, a stopper layer is formed using a silicon nitride film on the top of the channel.
An n layer is formed thereon. Since the selectivity between the n-layer and silicon nitride is high, the silicon nitride film serves to protect the underlying i-layer from etching when the n-layer is removed. Therefore, even in a large area, the thickness of one layer can be reduced. However, this method has problems such as etching of the a-Si when patterning the silicon nitride on the a-Si and an increase in the number of plasma CVD steps, which complicates the process.
本発明の目的は、この光電流を低減するのに有効であり
、かつ容易に形成できるa −S i T F Tを提
供することにある。An object of the present invention is to provide an a-S i T F T that is effective in reducing this photocurrent and can be easily formed.
上記目的は、a−8i膜を凸型に形成することにより、
すなわちa −S i T F Tのソース、ドレイン
電極部分に相当する下層のa−8iを薄くし、チャネル
上部部分にあたるa−8i膜厚を厚く形成することによ
り解決される。The above purpose is achieved by forming the a-8i film in a convex shape.
That is, this problem can be solved by making the lower layer a-8i, which corresponds to the source and drain electrode portions of the a-S i T F T, thinner, and by forming the a-8i film, which corresponds to the upper part of the channel, thicker.
上記の如(a −S i膜を凸型に形成すると、基板裏
面からの光照射に対してはその光のあたる部分のa −
S i膜の膜厚が薄いので光電流を小さくおさえること
ができ、一方ゲート金属に遮ぎられて裏面からの光があ
たらないチャネル上部はa −8i膜の膜厚が厚いので
エツチング分布の片寄り等の影響によって部分的になく
なってしまうことがない。As described above (if the a-Si film is formed in a convex shape, when light is irradiated from the back side of the substrate, the a-
Since the Si film is thin, the photocurrent can be suppressed to a small level. On the other hand, the thick a-8i film prevents the etching distribution from being uneven in the upper part of the channel, which is blocked by the gate metal and is not exposed to light from the back side. It will not be partially lost due to the influence of shifting or the like.
以下、本発明の一実施例を第1図により説明する。 An embodiment of the present invention will be described below with reference to FIG.
ガラス基板1の上にスパッタリングによりCr膜を堆積
し、ゲート電極2を形成する。次にプラズマCVDによ
り窒化シリコン膜(SiN)3゜ノンドープa−8i(
i層)4の順に連結堆積する(第1図(a) ) 、こ
のa−8i(i層)4をホトエツチングなどによりチャ
ネル上部に相当する部分を厚く、ソース、ドレイン電極
に相当する部分を薄く加工形成する(第1図(b))。A Cr film is deposited on a glass substrate 1 by sputtering to form a gate electrode 2. Next, a silicon nitride film (SiN) 3° non-doped a-8i (
The a-8i (i-layer) 4 is connected and deposited in this order (Fig. 1(a)), and the a-8i (i-layer) 4 is made thicker in the part corresponding to the upper part of the channel and thinner in the part corresponding to the source and drain electrodes by photoetching. Process and form (Fig. 1(b)).
ソース。sauce.
ドレイン電極に相当する部分のa−8i(i層)膜厚は
充電流特性の関係から200人前後あれば充分である。It is sufficient that the thickness of the a-8i (i-layer) in the portion corresponding to the drain electrode is around 200 in view of charging current characteristics.
チャネル上部に相当するa −S i(i層)膜厚は、
a−8i(i、n)の膜厚分布。The a-S i (i layer) film thickness corresponding to the upper part of the channel is:
Film thickness distribution of a-8i (i, n).
ドライエツチング分布CnM除去時の)などを考慮して
500人程度あれば良い、ただし、チャネル上部に関し
ては、遮光膜の存在によりa−8iのpA厚は若干厚く
なっても良い。次にこのa−3i (i層)4の上にリ
ンドープa−Si(n層)5約200人をプラズマCV
Dにより堆積し、a−3i4.5をドツト状に形成する
。スパッタリングまたは蒸着によりCr−AQの二層膜
を堆積し、ソース、ドレインの上部電極6を形成する(
第1図(C))。この状態でドライエツチングによりチ
ャネル上部のn層を除去する(第1図(d))。Approximately 500 people are sufficient considering the dry etching distribution (when removing CnM), etc. However, regarding the upper part of the channel, the pA thickness of a-8i may be slightly thicker due to the presence of a light shielding film. Next, approximately 200 layers of phosphorus-doped a-Si (n layer) 5 are deposited on top of this a-3i (i layer) 4 using plasma CV.
D is deposited to form a-3i4.5 in a dot shape. A two-layer film of Cr-AQ is deposited by sputtering or vapor deposition to form the upper electrodes 6 of the source and drain (
Figure 1 (C)). In this state, the n layer above the channel is removed by dry etching (FIG. 1(d)).
このエツチングにおいて大面積(例えば220×180
m程度)になると中央部と端部では一般に±20%前後
のエツチング分布が発生する。またa−8iこの堆積膜
厚分布も一般に±10%前後ある。この両者を考慮して
1層200人を完全に除去するドライエツチング工程で
多少のオーバーエッチでも充分に中央部と端部のa−8
i(i層)が残る。この時、エツチングで残るa−8i
(i層)は、MAX500Å以下が望ましい、これは光
電流特性から考慮したものである。n層除去後、パッシ
ベーション膜として窒化シリコン膜を形成して完了する
(第1図(e))。In this etching, a large area (e.g. 220 x 180
m), an etching distribution of about ±20% generally occurs at the center and edges. Further, the a-8i deposited film thickness distribution is generally around ±10%. Taking both of these into consideration, the dry etching process completely removes 200 layers per layer.
i (i layer) remains. At this time, the a-8i remaining after etching
The (i-layer) preferably has a maximum thickness of 500 Å or less, which is taken into consideration from the photocurrent characteristics. After removing the n layer, a silicon nitride film is formed as a passivation film to complete the process (FIG. 1(e)).
本発明のa−8iTFTは、基板裏面からの光照射に対
しては、a−8i(i層)の膜厚が薄いので光電流は小
さく (10−11A程度)おさえられる、チャネル上
部のa−8i(i層)膜はドライエツチングの特性を考
慮して厚く形成されているのでエツチング分布などの影
響により部分的になくなるような事故の発生もない。ま
た、n層とi層の間にストッパ層をもうけたりする必要
がないので工程が短縮できるなどの利点がある。In the a-8i TFT of the present invention, when light is irradiated from the back side of the substrate, the a-8i (i layer) is thin, so the photocurrent is suppressed to a small level (about 10-11 A). Since the 8i (i-layer) film is formed thickly in consideration of dry etching characteristics, accidents such as partial disappearance due to the influence of etching distribution etc. do not occur. Further, since there is no need to provide a stopper layer between the n-layer and the i-layer, there is an advantage that the process can be shortened.
第1図は本発明の一実施例のa −S i T F T
の製造工程図を示す図、第2図は従来のa −5iTF
Tの断面図、第3図はa −S i T F Tの1層
膜厚と光照射により発生する光電流特性を示す図である
。
1・・・ガラス基板、2・・・ゲート電極、3・・・S
iN膜、4−=a−8i(i層)、5−a−8i(n層
)、6′$l呂
(b)
(dl
第2呂FIG. 1 shows a -S i T F T of one embodiment of the present invention.
Figure 2 shows the manufacturing process diagram of the conventional a-5iTF.
FIG. 3 is a cross-sectional view of T, which shows the thickness of one layer of a-S i T F T and the photocurrent characteristics generated by light irradiation. 1...Glass substrate, 2...Gate electrode, 3...S
iN film, 4-=a-8i (i layer), 5-a-8i (n layer), 6'$l layer (b) (dl 2nd layer)
Claims (1)
リコン薄膜およびソース・ドレイン電極を形成して成る
非晶質シリコン薄膜トランジスタにおいて、 上記非晶質シリコン薄膜が、実質的に不純物を含有しな
い第1の非晶質シリコン薄膜と、不純物を含有する第2
の非晶質シリコン薄膜とから成り、上記第1の非晶質シ
リコン薄膜の膜厚が上記ソース・ドレイン電極下部は薄
く、チャンネル部分は厚く形成されていることを特徴と
する非晶質シリコン薄膜トランジスタ。[Claims] 1. An amorphous silicon thin film transistor comprising a gate electrode, a gate insulating film, an amorphous silicon thin film, and a source/drain electrode formed on a transparent substrate, wherein the amorphous silicon thin film substantially A first amorphous silicon thin film containing no impurities and a second amorphous silicon thin film containing impurities.
an amorphous silicon thin film, wherein the first amorphous silicon thin film is thin at a lower portion of the source/drain electrode and thick at a channel portion. .
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP31402287A JPH01155663A (en) | 1987-12-14 | 1987-12-14 | Amorphous silicon thin-film transistor |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP31402287A JPH01155663A (en) | 1987-12-14 | 1987-12-14 | Amorphous silicon thin-film transistor |
Publications (1)
Publication Number | Publication Date |
---|---|
JPH01155663A true JPH01155663A (en) | 1989-06-19 |
Family
ID=18048263
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP31402287A Pending JPH01155663A (en) | 1987-12-14 | 1987-12-14 | Amorphous silicon thin-film transistor |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH01155663A (en) |
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH04196490A (en) * | 1990-11-28 | 1992-07-16 | Nec Corp | Thin-film transistor |
JP2009278037A (en) * | 2008-05-19 | 2009-11-26 | Oki Semiconductor Co Ltd | Photocurrent estimation method and screening method of semiconductor uv sensor using same |
JPWO2011141954A1 (en) * | 2010-05-11 | 2013-07-22 | パナソニック株式会社 | Thin film semiconductor device for display device and manufacturing method thereof |
Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS59163868A (en) * | 1983-03-08 | 1984-09-14 | Fujitsu Ltd | Manufacture of self-alignment type thin-film transistor |
JPS6439065A (en) * | 1987-08-04 | 1989-02-09 | Nec Corp | Thin film field-effect transistor |
-
1987
- 1987-12-14 JP JP31402287A patent/JPH01155663A/en active Pending
Patent Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS59163868A (en) * | 1983-03-08 | 1984-09-14 | Fujitsu Ltd | Manufacture of self-alignment type thin-film transistor |
JPS6439065A (en) * | 1987-08-04 | 1989-02-09 | Nec Corp | Thin film field-effect transistor |
Cited By (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH04196490A (en) * | 1990-11-28 | 1992-07-16 | Nec Corp | Thin-film transistor |
US5396099A (en) * | 1990-11-28 | 1995-03-07 | Nec Corporation | MOS type semiconductor device having a high ON current/OFF current ratio |
JP2009278037A (en) * | 2008-05-19 | 2009-11-26 | Oki Semiconductor Co Ltd | Photocurrent estimation method and screening method of semiconductor uv sensor using same |
JPWO2011141954A1 (en) * | 2010-05-11 | 2013-07-22 | パナソニック株式会社 | Thin film semiconductor device for display device and manufacturing method thereof |
JP5421357B2 (en) * | 2010-05-11 | 2014-02-19 | パナソニック株式会社 | Thin film semiconductor device for display device and manufacturing method thereof |
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