JPH09266361A - Voltage variation accommodating structure of circuit board - Google Patents
Voltage variation accommodating structure of circuit boardInfo
- Publication number
- JPH09266361A JPH09266361A JP7398796A JP7398796A JPH09266361A JP H09266361 A JPH09266361 A JP H09266361A JP 7398796 A JP7398796 A JP 7398796A JP 7398796 A JP7398796 A JP 7398796A JP H09266361 A JPH09266361 A JP H09266361A
- Authority
- JP
- Japan
- Prior art keywords
- circuit board
- terminal layer
- power supply
- supply terminal
- ground terminal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/0213—Electrical arrangements not otherwise provided for
- H05K1/0216—Reduction of cross-talk, noise or electromagnetic interference
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/18—Printed circuits structurally associated with non-printed electric components
- H05K1/182—Printed circuits structurally associated with non-printed electric components associated with components mounted in the printed circuit board, e.g. insert mounted components [IMC]
Landscapes
- Structure Of Printed Boards (AREA)
Abstract
Description
【0001】[0001]
【発明の属する技術分野】本発明は、ICやLSI等の
電子部品を搭載すると共に、この電子部品に電源を供給
する電源端子層と、アースを行うアース端子層とを備え
た回路基板の電圧変動吸収構造に関するものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a voltage of a circuit board on which an electronic component such as an IC or an LSI is mounted and which has a power supply terminal layer for supplying power to the electronic component and a ground terminal layer for grounding. It relates to a variable absorption structure.
【0002】[0002]
【従来の技術】ICやLSI等の電子部品を搭載して所
定の電子回路を構成する回路基板においては、前記電子
部品への電源供給及びアースのための電源端子層及びア
ース端子層が設けられるが、前記電子回路の電子部品の
動作時に電源端子層とアース端子層間で電源電圧の変動
を生じることから、この種の回路基板では電源端子層と
アース端子層間の電源電圧の変動を吸収する目的でバイ
パスコンデンサまたはデカップリングコンデンサと呼ば
れる電圧変動吸収用のコンデンサが実装されており、こ
のコンデンサは一般的にIC等の電子部品数個に対して
1個の割合で設けられている。2. Description of the Related Art In a circuit board on which electronic components such as IC and LSI are mounted to form a predetermined electronic circuit, a power supply terminal layer and a ground terminal layer are provided for supplying power to the electronic components and grounding. However, since the power supply voltage fluctuates between the power supply terminal layer and the ground terminal layer during the operation of the electronic component of the electronic circuit, the purpose of absorbing the fluctuation of the power supply voltage between the power supply terminal layer and the ground terminal layer in this type of circuit board. A capacitor for absorbing voltage fluctuations called a bypass capacitor or a decoupling capacitor is mounted, and this capacitor is generally provided at a ratio of one to several electronic components such as ICs.
【0003】図13は従来の回路基板の電圧変動吸収構
造を示す平面図である。この図に見られるように従来
は、回路基板101上に搭載される例えば4個の電子部
品102に対して電圧変動吸収用のコンデンサ103を
1個実装し、このコンデンサ103を図示していない電
源端子層とアース端子層に接続している。このようにす
ることで電子部品102の動作時に発生する電源端子層
とアース端子層間の電源電圧の変動をコンデンサ103
で吸収し、これによりコンデンサ103近傍の電源電圧
の変動を小さく抑えるようにしている。FIG. 13 is a plan view showing a conventional voltage fluctuation absorbing structure of a circuit board. As shown in this figure, conventionally, one capacitor 103 for absorbing voltage fluctuation is mounted on, for example, four electronic components 102 mounted on a circuit board 101, and this capacitor 103 is not shown in the power source. It is connected to the terminal layer and the ground terminal layer. By doing so, fluctuations in the power supply voltage between the power supply terminal layer and the ground terminal layer, which occur during the operation of the electronic component 102, can be suppressed by the capacitor 103
To suppress the fluctuation of the power supply voltage in the vicinity of the capacitor 103 to be small.
【0004】尚、図中104は回路基板101の端部に
設けられたコネクタである。Reference numeral 104 in the figure denotes a connector provided at the end of the circuit board 101.
【0005】[0005]
【発明が解決しようとする課題】しかしながら上述した
従来の技術によると、以下の問題がある。すなわち、図
14は従来技術における電源端子層とアース端子層間の
電源電圧の変動の抑制効果を示す図で、この図から判る
ように電圧変動吸収用のコンデンサ103の近傍では、
同図 (a) に示したように電源電圧の変動を小さく抑え
ることができるものの、電圧変動吸収用のコンデンサ1
03から離れた部分、例えばコネクタ4が取り付けられ
ている基板端部においてはコンデンサ103の電圧変動
吸収機能が及ばないため、図14 (b) に示したように
電源電圧の大きな変動が出るという問題があり、更には
電源端子層とアース端子層間の電圧変動が原因で発生す
る放射ノイズに対しても、その抑制効果が得られないと
いう問題もあった。However, the above-mentioned conventional techniques have the following problems. That is, FIG. 14 is a diagram showing the effect of suppressing the fluctuation of the power supply voltage between the power supply terminal layer and the ground terminal layer in the prior art. As can be seen from this figure, in the vicinity of the voltage fluctuation absorbing capacitor 103,
Although it is possible to suppress fluctuations in the power supply voltage as shown in FIG.
The voltage fluctuation absorbing function of the capacitor 103 does not work at the part away from 03, for example, the end part of the board to which the connector 4 is attached, so that a large fluctuation of the power supply voltage occurs as shown in FIG. 14 (b). In addition, there is also a problem that the effect of suppressing radiation noise generated due to voltage fluctuation between the power supply terminal layer and the ground terminal layer cannot be obtained.
【0006】[0006]
【課題を解決するための手段】このような問題を解決す
るため、本発明は、電子部品を搭載すると共に、この電
子部品に電源を供給する電源端子層と、アースを行うア
ース端子層とを備えた回路基板の電圧変動吸収構造にお
いて、電圧変動吸収用のコンデンサを前記回路基板の外
周部の各辺に沿って配置すると共に、各コンデンサを前
記電源端子層とアース端子層に接続したことを特徴とす
る。SUMMARY OF THE INVENTION In order to solve such a problem, the present invention mounts an electronic component and includes a power supply terminal layer for supplying power to the electronic component and a ground terminal layer for grounding. In the circuit board voltage fluctuation absorbing structure provided, capacitors for voltage fluctuation absorption are arranged along each side of the outer peripheral portion of the circuit board, and each capacitor is connected to the power supply terminal layer and the ground terminal layer. Characterize.
【0007】[0007]
【発明の実施の形態】以下に図面を参照して本発明の実
施の形態の一例を説明する。図1は本発明による回路基
板の電圧変動吸収構造の第1の実施の形態を示す平面
図、図2は図1の要部断面図、図3は図1で用いる電圧
変動吸収用のコンデンサの正面図である。BEST MODE FOR CARRYING OUT THE INVENTION An example of an embodiment of the present invention will be described below with reference to the drawings. FIG. 1 is a plan view showing a first embodiment of a voltage fluctuation absorbing structure for a circuit board according to the present invention, FIG. 2 is a cross-sectional view of an essential part of FIG. 1, and FIG. 3 shows a voltage fluctuation absorbing capacitor used in FIG. It is a front view.
【0008】図において1は回路基板で、この回路基板
1は、電源端子層2とアース端子層3とを絶縁体4で覆
うと共に、絶縁体4の上下の面及び電源端子層2とアー
ス端子層3との間の絶縁体4内に信号線パターン5を設
け、更に外周部4辺にから板面と平行な方向に向かって
窪むように凹部6を設けて、この凹部6内の対向面に前
記電源端子層2とアース端子層3の一部を露出させた構
造となっている。In the figure, reference numeral 1 denotes a circuit board. The circuit board 1 covers the power supply terminal layer 2 and the ground terminal layer 3 with an insulator 4, and the upper and lower surfaces of the insulator 4 and the power supply terminal layer 2 and the ground terminal. The signal line pattern 5 is provided in the insulator 4 between the layer 3 and the concave portion 6 so as to be recessed in the direction parallel to the plate surface from the four sides of the outer peripheral portion. The power supply terminal layer 2 and the ground terminal layer 3 are partially exposed.
【0009】7は電圧変動吸収用のチップ状のコンデン
サで、両端に電極8a,8bを有している。このコンデ
ンサ7は図3 (a) に示したように、直線状に複数個並
べて樹脂等により一体に固定するか、または図3 (
(b) に示したように一定の長さを有するように棒状に
形成されており、このようにしたコンデンサ7を前記回
路基板1の外周部の各辺に設けた凹部6内に装着して、
それぞれの電極8a,8bを電源端子層2とアース端子
層3に接触させることにより、各コンデンサ7を電源端
子層3とアース端子層4間に設けた構造としている。Reference numeral 7 is a chip-shaped capacitor for absorbing voltage fluctuations, which has electrodes 8a and 8b at both ends. As shown in FIG. 3A, a plurality of the capacitors 7 are arranged linearly and fixed integrally with resin or the like, or as shown in FIG.
As shown in (b), it is formed in a rod shape so as to have a constant length, and the capacitors 7 thus constructed are mounted in the recesses 6 provided on each side of the outer peripheral portion of the circuit board 1. ,
The capacitors 7 are provided between the power supply terminal layer 3 and the ground terminal layer 4 by bringing the respective electrodes 8a and 8b into contact with the power supply terminal layer 2 and the ground terminal layer 3.
【0010】従って、これによれば図示しない電子部品
の動作時に電源電圧の変動が発生しても、回路基板1の
外周部全体に実装されているコンデンサ7によりその電
圧変動が吸収されるため、回路基板1全体の電源電圧の
変動を低く抑えることができるという効果が得られ、電
源端子層とアース端子層間の電圧変動が原因で発生する
放射ノイズに対しても抑制効果が得られる。Therefore, according to this, even if the power supply voltage fluctuates during the operation of an electronic component (not shown), the voltage fluctuation is absorbed by the capacitor 7 mounted on the entire outer peripheral portion of the circuit board 1. The effect that the fluctuation of the power supply voltage of the entire circuit board 1 can be suppressed to a low level is obtained, and the effect of suppressing the radiation noise generated due to the voltage fluctuation between the power supply terminal layer and the ground terminal layer is also obtained.
【0011】また、この実施の形態では比較的高い周波
数領域まで電圧変動を低く抑えることもできる。すなわ
ち、図4は回路基板1の外周部における電圧変動吸収用
のコンデンサの実装数と電圧変動の関係を示す図であ
る。ここで同図 (a) は電圧変動吸収用の単一のコンデ
ンサ7を3個、同図 (b)はコンデンサ7を5個、同図
(c) はコンデンサ7を7個実装した例を示しており、
また同図 (d) は同図 (a) 〜 (c) の各例において、
左上隅を振動源、右下隅を観測点として電圧変動を観測
したときの観測結果を表したもので、この図(d) から
判るようにコンデンサ7の実装数を増加させると、それ
に応じて広い周波数領域で電圧変動を低く抑えることが
できる。Further, in this embodiment, the voltage fluctuation can be suppressed to a relatively high frequency range. That is, FIG. 4 is a diagram showing the relationship between the number of capacitors mounted on the outer peripheral portion of the circuit board 1 for absorbing voltage fluctuations and the voltage fluctuations. Here, (a) in the figure shows three single capacitors 7 for absorbing voltage fluctuations, (b) in the figure shows 5 capacitors 7,
(c) shows an example in which seven capacitors 7 are mounted.
Further, FIG. 7D is the same as in each of FIGS.
It shows the observation result when the voltage fluctuation is observed with the upper left corner as the vibration source and the lower right corner as the observation point. As can be seen from this figure (d), if the number of capacitors 7 is increased, it becomes wider accordingly. The voltage fluctuation can be suppressed low in the frequency domain.
【0012】従って、回路基板1の外周部全体にコンデ
ンサ7を実装した上述の構造によれば、比較的高い周波
数領域まで電圧変動を低く抑えることができるという効
果が得られる。また、上述した構造ではコンデンサ7を
回路基板1の外周4辺に設けた凹部6内に装着している
ので、他のIC等の電子部品の実装面積を圧迫しないと
いう効果も得られる。Therefore, according to the above-mentioned structure in which the capacitor 7 is mounted on the entire outer peripheral portion of the circuit board 1, the effect that the voltage fluctuation can be suppressed to a relatively high frequency range can be obtained. Further, in the above-described structure, since the capacitors 7 are mounted in the recesses 6 provided on the outer peripheral four sides of the circuit board 1, there is an effect that the mounting area of electronic components such as other ICs is not pressed.
【0013】図5は本発明における第2の実施の形態を
示す要部断面図で、この実施の形態は、回路基板1に外
周4辺に凸部9を形成して、この凸部9の上下面に電源
端子層2とアース端子層3の一部を露出させると共に、
コンデンサ7をコの字形に形成してその内面に電極8
a,8bを設け、このコンデンサ7を前記凸部9に装着
して電極8a,8bを電源端子層2とアース端子層3に
接触させることにより、コンデンサ7を電源端子層3と
アース端子層4間に設けた構造としている。FIG. 5 is a cross-sectional view of an essential part showing a second embodiment of the present invention. In this embodiment, a convex portion 9 is formed on the outer peripheral four sides of the circuit board 1 and the convex portion 9 is formed. While exposing a part of the power supply terminal layer 2 and the ground terminal layer 3 on the upper and lower surfaces,
The capacitor 7 is formed in a U shape and the electrode 8 is formed on the inner surface
a and 8b are provided, the capacitor 7 is mounted on the convex portion 9 and the electrodes 8a and 8b are brought into contact with the power supply terminal layer 2 and the ground terminal layer 3, thereby the capacitor 7 is connected to the power supply terminal layer 3 and the ground terminal layer 4 The structure is provided between them.
【0014】尚、この実施の形態におけるコンデンサ7
も、上述した第1の実施の形態のように直線状に複数個
並べて樹脂等により一体に固定するか、または一定の長
さを有するように棒状に形成するもので、回路基板1の
外周部全体にコンデンサ7を実装することは、第1の実
施の形態と同様である。このようにした第2の実施の形
態によれば、回路基板1の外周部全体にコンデンサ7を
実装した構造としているので、第1の実施の形態と同様
に回路基板1全体の電源電圧の変動を低く抑えることが
できるという効果が得られ、電源端子層とアース端子層
間の電圧変動が原因で発生する放射ノイズに対しても抑
制効果が得られる。Incidentally, the capacitor 7 in this embodiment
Also, as in the first embodiment described above, a plurality of pieces are arranged linearly and fixed integrally with a resin or the like, or formed into a rod shape having a certain length. Mounting the capacitor 7 on the whole is the same as in the first embodiment. According to the second embodiment thus configured, since the capacitor 7 is mounted on the entire outer peripheral portion of the circuit board 1, the fluctuation of the power supply voltage of the entire circuit board 1 is the same as in the first embodiment. Can be suppressed to a low level, and an effect of suppressing radiation noise generated due to voltage fluctuation between the power supply terminal layer and the ground terminal layer can also be obtained.
【0015】また、この実施の形態でも比較的高い周波
数領域まで電圧変動を低く抑えることもできる。また、
コンデンサ7を回路基板1の凸部9に装着したとき、コ
ンデンサ7の上下の面が回路基板1の上下の面と同一面
となるようにしておけば、この第2の実施の形態におい
ても、他のIC等の電子部品の実装面積を圧迫しないと
いう効果も得られる。Also in this embodiment, voltage fluctuation can be suppressed to a relatively high frequency range. Also,
If the upper and lower surfaces of the capacitor 7 are flush with the upper and lower surfaces of the circuit board 1 when the capacitor 7 is mounted on the convex portion 9 of the circuit board 1, in the second embodiment as well, It is also possible to obtain the effect of not pressing the mounting area of other electronic components such as ICs.
【0016】図6は本発明における第3の実施の形態を
示す平面図、図7は図6の要部断面図で、この実施の形
態は回路基板1の外周部に沿って絶縁体4の部分に一定
の間隔でチップ状のコンデンサ7を埋設すると共に、回
路基板1の外周部に電源端子層3とアース端子層4を設
けて、この電源端子層3とアース端子層4に各コンデン
サ7の上下に設けられている電極8a,8bを接続した
もので、このようにしても第1の実施の形態と同様に回
路基板1全体の電源電圧の変動を低く抑えることができ
ると共に、比較的高い周波数領域まで電圧変動を低く抑
えることができるという効果が得られ、電源端子層とア
ース端子層間の電圧変動が原因で発生する放射ノイズに
対しても抑制効果も得られる。FIG. 6 is a plan view showing a third embodiment of the present invention, and FIG. 7 is a cross-sectional view of the principal part of FIG. 6, in which the insulator 4 is provided along the outer peripheral portion of the circuit board 1. The chip-shaped capacitors 7 are embedded in the portions at regular intervals, and the power supply terminal layer 3 and the ground terminal layer 4 are provided on the outer peripheral portion of the circuit board 1. The power supply terminal layer 3 and the ground terminal layer 4 are provided with the capacitors 7 respectively. By connecting the electrodes 8a and 8b provided above and below, the variation of the power supply voltage of the entire circuit board 1 can be suppressed to a low level as in the case of the first embodiment, and it can be comparatively achieved. The effect that the voltage fluctuation can be suppressed to a low level even in the high frequency region is obtained, and the effect of suppressing the radiation noise generated due to the voltage fluctuation between the power supply terminal layer and the ground terminal layer is also obtained.
【0017】図8は本発明における第4の実施の形態を
示す斜視図、図9はその要部断面図である。この実施の
形態における回路基板1は、電源端子層2の上下にアー
ス端子層3a,3bを配して、これらを絶縁体4で覆
い、この絶縁体4の上下の面を信号層として信号線パタ
ーン5を形成すると共に、電源端子層2に電気的に導通
したスルーホール10aと、アース端子層3a,3bに
電気的に導通したスルーホール10bを設けた構造とな
っている。FIG. 8 is a perspective view showing a fourth embodiment of the present invention, and FIG. 9 is a sectional view showing the main part thereof. In the circuit board 1 in this embodiment, the ground terminal layers 3a and 3b are arranged above and below the power supply terminal layer 2, and these are covered with an insulator 4, and the upper and lower surfaces of the insulator 4 serve as signal layers to serve as signal lines. The structure is such that the pattern 5 is formed, and the through hole 10a electrically connected to the power supply terminal layer 2 and the through hole 10b electrically connected to the ground terminal layers 3a and 3b are provided.
【0018】ここでスルーホール10aと10bは対を
成すもので、回路基板1の外周に沿って一定の間隔で設
けられており、そしてこれら各スルーホール10a,1
0bに電極8a,8bが接続されるようにコンデンサ7
が回路基板1の上下の面においてその外周に沿って一定
の間隔で実装されている。つまり、コンデンサ7はスル
ーホール10a,10bの対数と同数だけ回路基板1の
上下の面に外周縁に沿って実装されている。Here, the through holes 10a and 10b form a pair and are provided at regular intervals along the outer periphery of the circuit board 1, and the through holes 10a, 1 are provided.
0b to connect the electrodes 8a, 8b to the capacitor 7
Are mounted on the upper and lower surfaces of the circuit board 1 along the outer periphery thereof at regular intervals. That is, the capacitors 7 are mounted on the upper and lower surfaces of the circuit board 1 along the outer peripheral edge in the same number as the number of pairs of the through holes 10a and 10b.
【0019】図10は上述した構造における電源端子層
2とアース端子層3a,3bとの間に電圧変動が発生し
た場合の動作説明図で、この図3において、11は回路
基板1内のある点で発生した変動電圧、12は電圧変動
の観測点である。本実施の形態では、電源端子層2がア
ース端子層3a,3bにより上下から挟み込まれ、かつ
この両アース端子層3a,3bはスルーホール10bに
よって周辺部が電気的に短絡されているため、図示した
ように電源端子層2はアース端子層3a,3bとスルー
ホール10bによって包み込まれた構造となる。FIG. 10 is an operation explanatory view when a voltage fluctuation occurs between the power supply terminal layer 2 and the ground terminal layers 3a and 3b in the above-mentioned structure. In FIG. 3, 11 is in the circuit board 1. A fluctuating voltage generated at a point, and 12 is an observation point of the voltage fluctuation. In the present embodiment, the power supply terminal layer 2 is sandwiched between the ground terminal layers 3a and 3b from above and below, and the peripheral portions of the ground terminal layers 3a and 3b are electrically short-circuited by the through holes 10b. As described above, the power supply terminal layer 2 has a structure surrounded by the ground terminal layers 3a and 3b and the through hole 10b.
【0020】そして、電源端子層2とアース端子層3
a,3bの間には回路基板1の外周に沿って一定の間隔
で設けられたスルーホール10a,10bを介して電圧
変動吸収用のコンデンサ7が設けられており、そのため
変動電圧8の低周波成分はコンデンサ7によって、また
高周波成分は電源端子層2の包み込み構造によってそれ
ぞれ減衰され、従って観測点12で電圧変動は観測され
ないものとなる。The power supply terminal layer 2 and the ground terminal layer 3
A capacitor 7 for absorbing voltage fluctuations is provided between a and 3b via through holes 10a and 10b provided at regular intervals along the outer periphery of the circuit board 1, and therefore a low frequency of the fluctuation voltage 8 is provided. The component is attenuated by the capacitor 7 and the high frequency component is attenuated by the wrapping structure of the power supply terminal layer 2, so that the voltage fluctuation is not observed at the observation point 12.
【0021】図11は電源端子層2とアース端子層3
a,3b間の電圧変動の実測結果を示す図で、同図
(a) は上述した電源端子層2の包み込み構造を有して
いない従来技術で、図中の13は測定された電圧であ
り、同図 (b) は上述した電源端子層2の包み込み構造
を有する本発明の実施の形態のもので、図中の14は測
定された電圧である。FIG. 11 shows the power supply terminal layer 2 and the ground terminal layer 3
The figure which shows the measurement result of the voltage fluctuation between a and 3b.
(a) is a conventional technique which does not have the above-mentioned wrapping structure of the power supply terminal layer 2, 13 in the figure is a measured voltage, and (b) of the same figure shows the wrapping structure of the power supply terminal layer 2 described above. In the embodiment of the present invention that has, 14 in the figure is a measured voltage.
【0022】この図11 (a) , (b) により従来技術
の場合と本実施の形態の場合を比較すると、従来技術の
場合は図11 (a) に示したように、電源端子層とアー
ス端子層間の電圧変動に対して500MHZ 程度の周波
数では効果があるが、それ以上の周波数では電圧変動を
充分吸収できず、そのため電源端子層とアース端子層間
の電圧変動が原因で発生する放射ノイズに対しても、そ
の抑制効果が得られないものであった。Comparing the case of the prior art with the case of the present embodiment with reference to FIGS. 11 (a) and 11 (b), as shown in FIG. 11 (a), the power supply terminal layer and the ground are shown in the case of the prior art. is effective at a frequency of about 500 mH Z relative to the voltage variation of the terminal layers, can not be sufficiently absorbed voltage fluctuations at higher frequencies, the voltage fluctuation of the order power terminal layer and the ground terminal layers caused by radiation noise However, the suppressing effect was not obtained.
【0023】これに対して本実施の形態の場合は、図1
1 (b) に示したように低周波から高周波までの広い範
囲の周波数領域において電源端子層2とアース端子層3
a,3bとの間の電圧変動が低減されているのが判る。
従って、この第4の実施の形態によれば、電源端子層2
を上下からアース端子層3a,3bにより挟んた構造の
回路基板1の外周縁に沿って電圧変動吸収用のコンデン
サ7を一定の間隔で配置し、各コンデンサ7を前記スル
ーホール6aと電源端子層2に接続したスルーホール6
bを介して電源端子層2及びアース端子層3a,3bに
接続した構成としているため、回路基板1全体で電源端
子層2とアース端子層3a,3b間の電圧変動を低減す
ることができ、電源端子層とアース端子層間の電圧変動
が原因で発生する放射ノイズに対しても抑制効果が得ら
れる。On the other hand, in the case of the present embodiment, FIG.
As shown in 1 (b), the power supply terminal layer 2 and the ground terminal layer 3 in a wide frequency range from low frequency to high frequency.
It can be seen that the voltage fluctuation between a and 3b is reduced.
Therefore, according to the fourth embodiment, the power supply terminal layer 2
Capacitors 7 for absorbing voltage fluctuations are arranged at constant intervals along the outer peripheral edge of the circuit board 1 having a structure in which is grounded from above and below by the ground terminal layers 3a and 3b, and each capacitor 7 is connected to the through hole 6a and the power supply terminal layer. Through hole 6 connected to 2
Since it is configured to be connected to the power supply terminal layer 2 and the ground terminal layers 3a and 3b via b, it is possible to reduce the voltage fluctuation between the power supply terminal layer 2 and the ground terminal layers 3a and 3b in the entire circuit board 1. The effect of suppressing the radiation noise generated due to the voltage fluctuation between the power supply terminal layer and the ground terminal layer is also obtained.
【0024】また、アース端子層3a,3bをスルーホ
ール6aによって電気的に短絡していることから、電源
端子層2はアース端子層3a,3bとスルーホール10
aによって包み込まれた構造となり、この構造により電
圧変動の高周波成分を減衰できるので、電圧変動の低減
が低周波から高周波の領域にまで及ぶという効果も得ら
れる。Since the ground terminal layers 3a and 3b are electrically short-circuited by the through holes 6a, the power supply terminal layer 2 is connected to the ground terminal layers 3a and 3b and the through holes 10.
Since the structure is surrounded by a and the high frequency component of the voltage fluctuation can be attenuated by this structure, the effect of reducing the voltage fluctuation from the low frequency to the high frequency region is also obtained.
【0025】図12は本発明における第5の実施の形態
を示す要部断面図で、この第5の実施の形態は、回路基
板1の上下の面をアース端子層3a,3bとして形成す
ると共に、コの字形に形成された金属製のショート用部
品15によりアース端子層3a,3bを短絡させるよう
にしたものである。すなわち、この実施の形態における
回路基板1は、電源端子層2の上下に信号線パターン5
を有する信号層を配してこれらを絶縁体4で覆い、この
絶縁体4の上下の面をアース端子層3a,3bとして、
電源端子層2に電気的に導通したスルーホール6bを設
けた構造としており、この回路基板1の外周にコの字形
に形成された金属製のショート用部品15を嵌合装着す
ることにより、アース端子層3a,3bを短絡させ、そ
して電圧変動吸収用のコンデンサ7をその電極8a,8
bがスルーホール6b及びアース端子層3a,3bに接
続されるように回路基板1上下の面において回路基板1
の外周に沿って一定の間隔で実装したものとなってい
る。FIG. 12 is a cross-sectional view of an essential part showing a fifth embodiment of the present invention. In the fifth embodiment, the upper and lower surfaces of the circuit board 1 are formed as ground terminal layers 3a and 3b. The grounding terminal layers 3a and 3b are short-circuited by a metal short-circuiting component 15 formed in a U shape. That is, the circuit board 1 in this embodiment has the signal line patterns 5 above and below the power supply terminal layer 2.
And disposing the signal layers having the above, and covering them with the insulator 4, and the upper and lower surfaces of this insulator 4 as the ground terminal layers 3a and 3b,
The power supply terminal layer 2 is provided with a through hole 6b that is electrically connected, and a metal shorting component 15 formed in a U-shape is fitted and mounted on the outer periphery of the circuit board 1 to provide grounding. The terminal layers 3a and 3b are short-circuited, and the capacitor 7 for absorbing the voltage fluctuation is connected to its electrodes 8a and 8b.
circuit board 1 on the upper and lower surfaces so that b is connected to through hole 6b and ground terminal layers 3a and 3b.
It is mounted at regular intervals along the outer circumference of.
【0026】尚、ショート用部品12は回路基板1の一
辺に対して複数個装着するものでもよいが、長さを長く
して回路基板1の一辺に対して1個設ける構造とすれば
便利である。このようにした第5の実施の形態において
も、上述した第1の実施の形態と同様の作用,効果が得
られる。A plurality of short-circuit components 12 may be mounted on one side of the circuit board 1, but it is convenient if the length is increased and one component is provided on one side of the circuit board 1. is there. Also in the fifth embodiment thus configured, the same operation and effect as those of the above-described first embodiment can be obtained.
【0027】図15は本発明における第6の実施の形態
を示す平面図、図16は図15の要部断面図で、この実
施の形態は電源端子層2とアース端子層3とを絶縁体4
で覆った回路基板1の外周部に沿って一定の間隔でチッ
プ状のコンデンサ7を埋設し、そして電源端子層2に電
気的に導通したスルーホール10aと、アース端子層3
に電気的に導通したスルーホール10bを各コンデンサ
7と対応するように設けると共に、回路基板1の上面外
周に沿って各スルーホール10aに接続した導体16a
を、また回路基板1の上面外周に沿って各スルーホール
10bに接続した導体16bを設けて、この両導体16
a,16bに各コンデンサ7の電極8a,8bをそれぞ
れ接続するとにより、各コンデンサ7を電源端子層2と
アース端子層3にそれぞれ接続した構造となっている。FIG. 15 is a plan view showing a sixth embodiment of the present invention, and FIG. 16 is a cross-sectional view of the principal part of FIG. 15. In this embodiment, the power supply terminal layer 2 and the ground terminal layer 3 are made of an insulating material. Four
The chip-shaped capacitors 7 are embedded at regular intervals along the outer periphery of the circuit board 1 covered with the through holes 10a electrically connected to the power supply terminal layer 2, and the ground terminal layer 3
Conductors 16a connected to the through holes 10a along the outer periphery of the upper surface of the circuit board 1 while the through holes 10b electrically connected to the capacitors 7 are provided so as to correspond to the capacitors 7.
And a conductor 16b connected to each through hole 10b along the outer periphery of the upper surface of the circuit board 1.
By connecting the electrodes 8a and 8b of the capacitors 7 to a and 16b, respectively, the capacitors 7 are connected to the power supply terminal layer 2 and the ground terminal layer 3, respectively.
【0028】このようにしても第1の実施の形態と同様
に回路基板1全体の電源電圧の変動を低く抑えることが
できると共に、比較的高い周波数領域まで電圧変動を低
く抑えることができるという効果が得られ、電源端子層
とアース端子層間の電圧変動が原因で発生する放射ノイ
ズに対しても抑制効果も得られる。Even in this case, the fluctuation of the power supply voltage of the entire circuit board 1 can be suppressed to a low level as in the first embodiment, and the voltage fluctuation can be suppressed to a relatively high frequency range. Therefore, the effect of suppressing the radiation noise generated due to the voltage fluctuation between the power supply terminal layer and the ground terminal layer is also obtained.
【0029】[0029]
【発明の効果】以上説明したように本発明は、電圧変動
吸収用のコンデンサを回路基板の外周部の各辺に沿って
配置すると共に、各コンデンサを前記電源端子層とアー
ス端子層に接続した構成として、回路基板の外周部全体
に電圧変動吸収用のコンデンサを実装している。As described above, according to the present invention, capacitors for absorbing voltage fluctuations are arranged along each side of the outer peripheral portion of the circuit board, and each capacitor is connected to the power supply terminal layer and the ground terminal layer. As a configuration, a capacitor for absorbing voltage fluctuation is mounted on the entire outer peripheral portion of the circuit board.
【0030】従って、これによれば電子部品の動作時に
電源電圧の変動が発生しても、回路基板の外周部全体に
実装されているコンデンサによりその電圧変動が吸収さ
れるため、回路基板全体の電源電圧の変動を低く抑える
ことができるという効果が得られ、電源端子層とアース
端子層間の電圧変動が原因で発生する放射ノイズに対し
ても抑制効果が得られる。Therefore, according to this, even if the power supply voltage fluctuates during the operation of the electronic component, the voltage fluctuation is absorbed by the capacitors mounted on the entire outer peripheral portion of the circuit board. The effect that the fluctuation of the power supply voltage can be suppressed to a low level is obtained, and the effect of suppressing the radiation noise generated due to the voltage fluctuation between the power supply terminal layer and the ground terminal layer is also obtained.
【図1】本発明による回路基板の電圧変動吸収構造の第
1の実施の形態を示す平面図である。FIG. 1 is a plan view showing a first embodiment of a voltage fluctuation absorbing structure for a circuit board according to the present invention.
【図2】図1の要部断面図である。FIG. 2 is a sectional view of a main part of FIG.
【図3】図1で用いる電圧変動吸収用のコンデンサの正
面図である。FIG. 3 is a front view of a capacitor for absorbing voltage fluctuations used in FIG.
【図4】電圧変動吸収用のコンデンサの実装数と電圧変
動の関係を示す図である。FIG. 4 is a diagram showing a relationship between the number of mounted capacitors for absorbing voltage fluctuations and voltage fluctuations.
【図5】本発明における第2の実施の形態を示す要部断
面図である。FIG. 5 is a cross-sectional view of an essential part showing a second embodiment of the present invention.
【図6】本発明における第3の実施の形態を示す平面図
である。FIG. 6 is a plan view showing a third embodiment of the present invention.
【図7】図6の要部断面図である。FIG. 7 is a sectional view of a main part of FIG. 6;
【図8】本発明における第4の実施の形態を示す斜視図
である。FIG. 8 is a perspective view showing a fourth embodiment of the present invention.
【図9】図8の要部断面図である。9 is a cross-sectional view of the main parts of FIG.
【図10】第4の実施の形態の動作説明図である。FIG. 10 is an operation explanatory diagram of the fourth embodiment.
【図11】電源端子層とアース端子層間の電圧変動の実
測結果を示す図である。FIG. 11 is a diagram showing an actual measurement result of voltage fluctuation between a power supply terminal layer and a ground terminal layer.
【図12】本発明における第5の実施の形態を示す要部
断面図である。FIG. 12 is a cross-sectional view of essential parts showing a fifth embodiment of the present invention.
【図13】従来技術を示す平面図である。FIG. 13 is a plan view showing a conventional technique.
【図14】従来技術における電圧変動の抑制効果を示す
図である。FIG. 14 is a diagram showing the effect of suppressing voltage fluctuations in the prior art.
【図15】本発明における第6の実施の形態を示す平面
図である。FIG. 15 is a plan view showing a sixth embodiment of the present invention.
【図16】図15の要部断面図である。16 is a cross-sectional view of the main parts of FIG.
1 回路基板 2 電源端子層 3,3a,3b アース端子層 4 絶縁体 5 信号線パターン 6 凹部 7 コンデンサ 8a,8b 電極 9 凸部 10a,10b スルーホール 15 ショート用部品 1 Circuit Board 2 Power Supply Terminal Layers 3, 3a, 3b Ground Terminal Layer 4 Insulator 5 Signal Line Pattern 6 Recess 7 Capacitor 8a, 8b Electrode 9 Convex 10a, 10b Through Hole 15 Shorting Parts
Claims (7)
品に電源を供給する電源端子層と、アースを行うアース
端子層とを備えた回路基板の電圧変動吸収構造におい
て、 電圧変動吸収用のコンデンサを前記回路基板の外周部の
各辺に沿って配置すると共に、各コンデンサを前記電源
端子層とアース端子層に接続したことを特徴とする回路
基板の電圧変動吸収構造。1. A capacitor for absorbing voltage fluctuations in a voltage fluctuation absorbing structure for a circuit board, comprising a power supply terminal layer for mounting electronic parts and supplying power to the electronic parts, and a ground terminal layer for grounding. Is arranged along each side of the outer peripheral portion of the circuit board, and each capacitor is connected to the power supply terminal layer and the ground terminal layer.
構造において、 回路基板の外周部の各辺に凹部を設け、直線状に並べて
一体化した複数のコンデンサまたは棒状に形成したコン
デンサを前記各凹部に収納するように装着し、各々のコ
ンデンサを前記電源端子層とアース端子層に直接接続し
たことを特徴とする回路基板の電圧変動吸収構造。2. The voltage fluctuation absorbing structure for a circuit board according to claim 1, wherein a concave portion is provided on each side of an outer peripheral portion of the circuit board, and a plurality of capacitors arranged in a line and integrated or a rod-shaped capacitor are formed. A voltage fluctuation absorbing structure for a circuit board, which is mounted so as to be housed in each recess, and each capacitor is directly connected to the power supply terminal layer and the ground terminal layer.
構造において、 回路基板の外周部の各辺に凸部を設け、この凸部のコの
字形に形成したコンデンサを挟み付けるように装着し、
各々のコンデンサを前記電源端子層とアース端子層に直
接接続したことを特徴とする回路基板の電圧変動吸収構
造。3. The voltage fluctuation absorbing structure for a circuit board according to claim 1, wherein a convex portion is provided on each side of the outer peripheral portion of the circuit board, and the capacitor formed in a U-shape of the convex portion is mounted so as to be sandwiched. Then
A voltage fluctuation absorbing structure for a circuit board, wherein each capacitor is directly connected to the power supply terminal layer and the ground terminal layer.
構造において、 回路基板の外周部の各辺に沿って複数のコンデンサを埋
設し、前記回路基板の上下の面に電源端子層とアース端
子層を設けて、この電源端子層とアース端子層に前記各
コンデンサを直接接続したことを特徴とする回路基板の
電圧変動吸収構造。4. The voltage fluctuation absorbing structure for a circuit board according to claim 1, wherein a plurality of capacitors are embedded along each side of an outer peripheral portion of the circuit board, and a power supply terminal layer and a ground are provided on upper and lower surfaces of the circuit board. A voltage fluctuation absorbing structure for a circuit board, wherein a terminal layer is provided, and the capacitors are directly connected to the power supply terminal layer and the ground terminal layer.
構造において、 回路基板は、電源端子層の上下に配置したアース端子層
を備えると共に、前記電源端子層に接続したスルーホー
ルとその上下の両アース端子層に接続したスルーホール
を外周部の各辺に沿って複数設けた構造とし、 前記回路基板の外周部の各辺に沿って複数のコンデンサ
を配置すると共に、各コンデンサを前記両スルーホール
を介して前記電源端子層とアース端子層に接続したこと
を特徴とする回路基板の電圧変動吸収構造。5. The voltage fluctuation absorbing structure for a circuit board according to claim 1, wherein the circuit board includes ground terminal layers disposed above and below the power supply terminal layer, and through holes connected to the power supply terminal layer and the upper and lower sides thereof. A plurality of through-holes connected to both ground terminal layers are provided along each side of the outer peripheral portion, a plurality of capacitors are arranged along each side of the outer peripheral portion of the circuit board, and each capacitor is A voltage fluctuation absorbing structure for a circuit board, characterized in that the power supply terminal layer and the ground terminal layer are connected through a through hole.
構造において、 回路基板は、電源端子層の上下で外部に露出するように
配置したアース端子層を備えると共に、前記電源端子層
に接続したスルーホールを外周部の各辺に沿って複数設
けた構造とし、 前記回路基板の外周部の各辺にコの字形のショート用部
品を挟み付けるように装着して、このショート用部品に
より両アース端子層を短絡させると共に、 前記回路基板の外周部の各辺に沿って複数のコンデンサ
を配置し、各コンデンサを前記スルーホールを介して前
記電源端子層に接続しすると共にアース端子層には直接
接続したことを特徴とする回路基板の電圧変動吸収構
造。6. The voltage fluctuation absorbing structure for a circuit board according to claim 1, wherein the circuit board includes a ground terminal layer disposed above and below the power supply terminal layer so as to be exposed to the outside, and connected to the power supply terminal layer. A plurality of through holes are provided along each side of the outer peripheral portion, and a U-shaped shorting component is mounted on each side of the outer peripheral portion of the circuit board so as to be sandwiched by the shorting component. While short-circuiting the ground terminal layer, a plurality of capacitors are arranged along each side of the outer peripheral portion of the circuit board, each capacitor is connected to the power supply terminal layer through the through hole, and the ground terminal layer is A circuit board voltage fluctuation absorbing structure characterized by being directly connected.
構造において、 内部に電源端子層とアース端子層を備えた回路基板の外
周部の各辺に沿って複数のコンデンサを埋設し、 更に回路基板に前記電源端子層とアース端子層に接続し
たスルーホールを前記各コンデンサに対応するように設
けて、 このスルーホールを介して前記電源端子層とアース端子
層に前記各コンデンサを接続したことを特徴とする回路
基板の電圧変動吸収構造。7. The circuit board voltage fluctuation absorbing structure according to claim 1, wherein a plurality of capacitors are embedded along each side of an outer peripheral portion of the circuit board having a power supply terminal layer and a ground terminal layer therein. Through holes connected to the power supply terminal layer and the ground terminal layer are provided on the circuit board so as to correspond to the capacitors, and the capacitors are connected to the power supply terminal layer and the ground terminal layer through the through holes. A circuit board voltage fluctuation absorbing structure characterized by:
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP7398796A JPH09266361A (en) | 1996-03-28 | 1996-03-28 | Voltage variation accommodating structure of circuit board |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP7398796A JPH09266361A (en) | 1996-03-28 | 1996-03-28 | Voltage variation accommodating structure of circuit board |
Publications (1)
Publication Number | Publication Date |
---|---|
JPH09266361A true JPH09266361A (en) | 1997-10-07 |
Family
ID=13533981
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP7398796A Pending JPH09266361A (en) | 1996-03-28 | 1996-03-28 | Voltage variation accommodating structure of circuit board |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH09266361A (en) |
Cited By (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
DE19911731A1 (en) * | 1998-03-16 | 1999-10-07 | Nec Corp | Multilayer printed circuit board for electronic device, such as information processing or communications device |
EP1130950A2 (en) * | 2000-02-29 | 2001-09-05 | Kyocera Corporation | Wiring board |
US6580931B1 (en) * | 1998-04-10 | 2003-06-17 | Fujitsu Limited | Printed circuit board including EMI reducing circuits, an information processing apparatus having the board and a method to select the circuits |
JP2008205457A (en) * | 2007-02-16 | 2008-09-04 | Samsung Electronics Co Ltd | Multilayer printed circuit board |
JP2016075636A (en) * | 2014-10-08 | 2016-05-12 | 株式会社日本マイクロニクス | Probe card |
-
1996
- 1996-03-28 JP JP7398796A patent/JPH09266361A/en active Pending
Cited By (11)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
DE19911731A1 (en) * | 1998-03-16 | 1999-10-07 | Nec Corp | Multilayer printed circuit board for electronic device, such as information processing or communications device |
US6198362B1 (en) | 1998-03-16 | 2001-03-06 | Nec Corporation | Printed circuit board with capacitors connected between ground layer and power layer patterns |
DE19911731C2 (en) * | 1998-03-16 | 2002-08-29 | Nec Corp | Printed circuit board |
US6580931B1 (en) * | 1998-04-10 | 2003-06-17 | Fujitsu Limited | Printed circuit board including EMI reducing circuits, an information processing apparatus having the board and a method to select the circuits |
US6782243B2 (en) | 1998-04-10 | 2004-08-24 | Fujitsu Limited | Printed circuit board including EMI reducing circuits, an information processing apparatus having the board and a method to select the circuits |
EP1130950A2 (en) * | 2000-02-29 | 2001-09-05 | Kyocera Corporation | Wiring board |
US6469259B2 (en) | 2000-02-29 | 2002-10-22 | Kyocera Corporation | Wiring board |
EP1130950A3 (en) * | 2000-02-29 | 2003-12-17 | Kyocera Corporation | Wiring board |
JP2008205457A (en) * | 2007-02-16 | 2008-09-04 | Samsung Electronics Co Ltd | Multilayer printed circuit board |
JP4675387B2 (en) * | 2007-02-16 | 2011-04-20 | 三星電子株式会社 | Multilayer printed circuit board |
JP2016075636A (en) * | 2014-10-08 | 2016-05-12 | 株式会社日本マイクロニクス | Probe card |
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