JPH088426A - Semiconductor device - Google Patents

Abstract

(57) [Abstract] [Problem] To provide a semiconductor device capable of effectively preventing deterioration against irradiation of radiation such as X-rays. [Structure] The MOS transistor 11 stops operating and Vcc
When the power is cut off, the gate terminal 1 is activated by the switch 15.
4 and the power source 17 are connected, the drain terminal 12 is connected to the ground potential by the switch 16 and a positive DC power source is applied to the gate terminal of the transistor 11 to set the gate oxide film electric field of the transistor to about 3 MV / cm or more. [Effect] Even if radiation such as X-rays is generated when the Vcc power supply is stopped while the operation is stopped, the generation of noise traps can be significantly suppressed, and at the same time, the generation of positive fixed charges (SiO ₃ +) is suppressed. It

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device having a MOS transistor and its integrated circuit in a semiconductor substrate.

[0002]

2. Description of the Related Art Conventionally, when a semiconductor integrated circuit is used in a radiation environment such as a space or a nuclear reactor, there has been a problem that the device is deteriorated due to continuous radiation and the device malfunctions. Particularly in a MOS transistor, radiation such as X-rays generates electron hole pairs in the gate oxide film, and the holes trap in the oxide film (E ′ center, SiO ₃ ·) and a positive fixed charge (SiO ₃ +). To generate. Traps cause noise, positive fixed charges cause the threshold to fluctuate greatly,
Disable normal operation of the device.

FIG. 2 shows noise characteristics when an n-channel MOS transistor is irradiated with X-rays. The gate length of the transistor is 1.25 μm, the gate width is 15 μm, the gate oxide film thickness is 25 nm, and the drain structure is a normal single drain structure. Measurement noise value is frequency 75H
It is the equivalent input voltage noise of z. From this result, it is clear that the noise increases rapidly as the X-ray dose is increased. This increase in noise indicates an increase in noise traps in the gate oxide film. As described above, the noise trap is generated by the X-ray irradiation, which is a big problem.

[0004]

SUMMARY OF THE INVENTION It is an object of the present invention to provide a semiconductor device capable of preventing or significantly suppressing trap generation in an oxide film even when radiation such as X-rays is applied to a MOS transistor or its integrated circuit. To do.

[0005]

In order to achieve the above object, the present invention provides a gate terminal of a MOS transistor or a MOS transistor which is in a power-off state of Vcc, that is, when the operation is stopped.
A DC power supply is connected to the input terminal of the basic logic gate via a switch to apply a positive gate voltage, thereby significantly suppressing the generation of noise traps. That is,
By applying a positive gate voltage, the electric field of the gate oxide film when the Vcc power supply is cut off is set to about 3 MV / cm or more. When the gate voltage is applied, both the drain terminal and the output terminal of the basic logic gate are fixed to the ground potential.

Further, according to the present invention, the CMOS LSI chip is divided into a portion that retains information by battery backup when Vcc power is cut off and a portion that does not perform battery backup, and a positive gate voltage is applied to the part that does not perform battery backup when Vcc power is cut off. Then, the electric field of the gate oxide film of the transistor is about 3
MV / cm or more.

[0007]

When an n-channel MOS transistor is irradiated with X-rays, a noise trap is generated in the gate oxide film, so that noise increases as shown in FIG. This trap is paired with the positive fixed charge, and therefore the noise increases and the flat band voltage V _{fb of the} MOS transistor decreases (changes in the negative direction). This flat band voltage change is due to the IEEE Trans. On Nuclear Science (IEEE Trans.
Nuclear Science) 1975, NS-22, 215.
As has been published in the papers on page 1 and below, it has been clear from the past that this can be strengthened by applying a positive gate voltage during irradiation. The results are shown in Fig. 3, where the gate voltage is increased and the gate oxide film electric field is about 1.5 MV.
The flat band voltage continues to increase until it becomes / cm. It has been conventionally pointed out that when a gate oxide film electric field is applied during irradiation as described above, the flat band voltage fluctuates compared to when an electric field is not applied, resulting in further deterioration of the device.

On the other hand, when the electric field of the gate oxide film at the time of irradiation was increased to about 6 MV / cm and the noise change was measured, when the electric field was more than about 3 MV / cm, the electric field was higher than that when no electric field was applied. It was newly found that the noise increase can be significantly suppressed. The experimental results are shown in FIG. Here, the gate length of the nMOS transistor of the measurement sample is 0.7 μm, the gate width is 15 μm, the gate oxide film thickness is 13.5 nm, and the X-ray irradiation amount is 2 × 10 ⁶ rad. The measured noise is the power spectrum density of the equivalent input voltage noise, and the measurement frequency is 75 Hz. From this result, it is clear that the noise trap and the generation of the positive fixed charges due to the X-ray irradiation can be remarkably suppressed at the electric field of about 3 MV / cm or more as compared with the case where the electric field is not applied.

Based on this new experimental result, in the present invention, by applying a positive gate voltage, the electric field of the gate oxide film when the Vcc power supply is cut off is about 3 MV / cm or more,
As a result, the generation of traps in the oxide film could be suppressed to a greater extent than before. The mechanism by which trap generation can be remarkably suppressed at an electric field of about 3 MV / cm or more is as follows.

Noise traps in the oxide film are generated by the reaction of holes excited by X-rays with oxygen vacancies, but the application of a positive gate voltage causes a relatively low gate oxide film electric field of 2 MV / cm or less. When is added, this hole is attracted to the interface, and there are many oxygen vacancies near the interface, so trap generation increases. On the other hand, in a high electric field of 2 MV / cm or higher, holes travel at a high speed and the cross-sectional area of collision with holes is reduced, so that trap generation is suppressed. Can be deterred. Due to such a mechanism and action, the present invention can significantly reduce the generation of traps in the oxide film as compared with the prior art.

Further, the present invention uses a CMOS LSI chip as a V
cc The information storage part that requires battery backup when the power is cut off and the part that does not require battery backup are divided into two parts, and a positive gate voltage is applied to the input terminal of the logic gate for this battery backup unnecessary part. This suppresses the generation of traps, and this makes it possible to significantly improve the deterioration resistance as compared with the prior art without destroying the memory information of the chip.

[0012]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A first embodiment of the present invention will be described with reference to FIG. The first embodiment uses an nMOS transistor as a basic device. In FIG. 1, 11 is an nMOS transistor, 12 is a drain terminal, 13 is a source terminal, and 14
Is a gate terminal, 15 and 16 are switches, and 17 is D
C gate voltage power supply. Gate terminal 14 is switch 1
The gate voltage power supply 17 is connected via 5 and the drain terminal 12 is connected to the ground potential via the switch 16.

In this embodiment, when the transistor 11 does not operate, that is, when the Vcc power supply is cut off, the gate terminal 14 and the power supply 17 are connected by the switch 15 and the switch 16 is connected.
Thus, the drain terminal 12 is connected to the ground potential, and a positive DC power source is applied to the gate terminal of the transistor 11. The electric field of the gate oxide film of the transistor is set to about 3 MV / cm or more.

As a result, even if radiation such as X-rays is applied when the Vcc power supply is cut off while the transistor is not operating,
As shown in FIG. 3 and FIG. 4, the generation of noise traps can be significantly suppressed as compared with the conventional case. At the same time, generation of positive fixed charges (SiO ₃ +) was also suppressed. In this way, a MOS type semiconductor device with higher reliability than in the past can be realized.

A second embodiment of the present invention will be described with reference to FIG. This embodiment is based on the switches 15 and 1 of the first embodiment.
6 is realized by a complementary switch. In FIG. 5, 51 is an nMOS transistor, 52 is a drain terminal, 53 is a source terminal, 54 is a gate terminal,
55, 56, 57, 58 are complementary switches, 59 is DC
It is a gate voltage power supply. The gate terminal 54 is a switch 56
Connected to the gate voltage power supply 59 via the drain terminal 5
2 is connected to the ground potential via the switch 58.

In this embodiment, when the switch 57 is opened or turned off, the Vcc power supply is cut off and the transistor 51 does not operate, the switch 56 connects the gate terminal 54 and the power supply 59, and the switch 58 connects the drain terminal 52 and the ground. This is to connect a potential and apply a positive DC power supply to the gate terminal of the transistor 51. The electric field of the gate oxide film of the transistor is set to about 3 MV / cm or more.

The switches 55, 56, 57 and 58 are opened and closed as follows. That is, in order to open the switch, the logic value "1" is supplied from the Vcc power supply or another power supply to the gate terminal of the nMOS transistor forming the complementary switch.
Of the logical value "0" is applied to the gate terminal of the pMOS transistor forming the complementary switch. To close the switch, a positive voltage of logical value "1" is applied to the pMOS transistor from the Vcc power supply or another power supply, and a voltage of 0V is applied to the nMOS transistor.

As described above, the radiation effect similar to that of the first embodiment can be realized.

A third embodiment of the present invention will be described with reference to FIG. This embodiment shows a basic CMOS circuit constructed according to the present invention. In the figure, 61 is an nMOS transistor and 62 is a pM.
The n- and p-type MOS transistors are OS transistors and constitute a CMOS inverter with 63, 64, 65 and 66 as Vcc power supply terminal, Vss ground terminal, gate input terminal and output terminal. Also 671,672,681,68
2, 691 and 692 are complementary switches, 600 is a DC gate voltage power source, and 601 and 602 are CMOS inverters, which represent an inverter string connected to the input. The input terminal 65 is connected to the DC power source 600 via the switch 672, and the output terminal 66 is connected to the switch 69.
It is connected to the ground potential via 2 and Vcc power supply terminal 63
Is also connected to ground potential via switch 682.

In this embodiment, when the CMOS inverter does not operate, that is, when the switch 681 is turned off and the Vcc power supply is cut off, the input terminal 65 is connected to the DC power supply 600 and the Vcc power supply terminal 63 and the output terminal 66 are grounded. By connecting to the potential, a positive DC power source is applied to the gates of both the n and p MOS transistors. And both M
The electric field of the gate oxide film of the OS transistor is about 3 MV / cm or more. The method of opening / closing each switch and supplying the voltage to the switch is the same as that of the second embodiment.

As described above, when Vcc power supply is cut off while the CMOS inverter is not operating, even if radiation such as X-rays is applied, an electric field of about 3 MV / cm or more is applied to the gate oxide films of both MOSs. As shown in FIG. 4, the generation of noise traps can be significantly suppressed as compared with the conventional case. N in FIG.
The experimental results of the MOS transistor are shown, but in the pMOS transistor as well, a positive gate voltage is applied to about 3 MV /
By applying an electric field of cm or more to the gate oxide film,
The same suppression of noise increase appeared. As described above, according to the present invention, it is possible to realize a highly reliable CMOS circuit and a semiconductor device including the same, in which noise traps and generation of positive fixed charges (SiO ₃ +) can be significantly suppressed as compared with the related art.

A fourth embodiment of the present invention will be described with reference to FIG. This embodiment is a prototype of a CMOS LSI chip according to the present invention. In the figure, 71 is a CMOS LSI chip, 72 is a Vcc power supply,
Reference numeral 73 is a backup battery when the Vcc power supply is cut off, and 74 is a DC gate voltage power supply. Reference numeral 75 is a power control unit in the chip, 76 is a demultiplexer, 77 is an LSI portion that performs battery backup when the Vcc power supply is cut off when the chip suspends main operations such as calculation and storage, and 78 is the same V
cc This is the LSI part that does not back up the battery when the power is cut off. A switch 79 connects 78 and 74.

In the chip of this embodiment, a control signal from the power control unit 75 is applied to the demultiplexer 76, and this demultiplexer controls Vcc of each part of the chip. That is, whether power is directly supplied from the Vcc power source 72,
Power is supplied from the battery 73 or not supplied at all. This allows efficient management of chip power consumption. In addition, the chip is divided into an information holding portion 77 that requires battery backup when Vcc power is cut off and a portion 78 that does not require battery backup, and a DC gate voltage power supply VGG is connected to this battery backup unnecessary portion through a switch 79.
74 was connected. As a result, when the chip suspends main operations such as calculation and storage and the Vcc power supply is cut off, the switch 7
It was possible to connect 78 and 74 by means of 9 and to apply a positive gate voltage to the input terminal of the logic gate constituting 78. The electric field of the gate oxide film of the transistor constituting the logic gate is set to about 3 MV / cm or more. In the present embodiment, the power control unit 75 and the demultiplexer 76 are supplied with the power supply voltage from the Vcc power supply 72 even when the chip suspends main operations such as calculation and storage.

The method of opening and closing the switch in this embodiment is the same as the method described in the second and third embodiments, and the voltage is supplied to the switch from the Vcc power supply or another power supply. An example of voltage supply in this embodiment will be described below. In this example, the voltage is supplied to the switch by the Vcc power supply 72 before the Vcc power supply is cut off, and by the backup battery 73 after the Vcc power supply is cut off. The switching and the switching of the gate voltage levels of both the n and p MOS transistors for opening and closing the complementary switches are performed by the demultiplexer by giving a control signal from the power control unit 75 to the demultiplexer 76.

As described above, the generation of traps in the gate oxide film at the 78th portion could be greatly suppressed in the same manner as in the above-described embodiment without destroying the memory information of the chip.
In this way, CMOS LSI with much higher reliability than before
The chip was realized.

[0026]

According to the present invention, even if radiation such as X-rays is irradiated, the generated holes travel at high speed and the cross-sectional area of collision with oxygen vacancies is reduced, so that noise traps are not generated. It was possible to reduce significantly compared to the past. At the same time, the generation of positive fixed charges in the gate oxide film can be reduced much more than before.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing a first embodiment of the present invention.

FIG. 2 is a characteristic diagram showing noise increase due to X-ray irradiation in a conventional nMOS transistor.

FIG. 3 is a characteristic diagram showing gate voltage dependence of flat band voltage change due to X-ray irradiation.

FIG. 4 is a characteristic diagram showing the gate oxide film electric field dependency of noise increase due to X-ray irradiation, and the effect of the present invention.

FIG. 5 is a circuit diagram showing a second embodiment of the present invention.

FIG. 6 is a circuit diagram showing a third embodiment of the present invention.

FIG. 7 is a circuit diagram showing a fourth embodiment of the present invention.

[Explanation of symbols]

11 ... nMOS transistor, 12 ... Drain terminal, 1
3 ... Source terminal, 14 ... Gate terminal, 15, 16 ... Switch, 17 ... DC gate voltage power supply.

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁶ Identification code Office reference number FI technical display location // H05K 10/00

Claims (4)

[Claims] 1. A first DC power supply for electrically connecting to a drain terminal of a MOS transistor through a first switch to supply a power supply voltage, and a gate terminal for electrically connecting through a second switch. A second direct current power supply, and when the first switch is opened or the supply voltage of the first direct current power supply is substantially zero, the second switch is closed to provide a positive gate voltage. A semiconductor device, wherein a gate oxide film electric field is set to 3 MV / cm or more by being applied to the gate terminal. 2. A first DC power supply for electrically supplying a power supply voltage by electrically connecting to a source terminal of a pMOS transistor serving as a power supply terminal of a CMOS inverter circuit through a first switch, and a gate input of the pMOS transistor. A second direct current power source electrically connected to the terminal via a second switch, and when the first switch is opened or the supply voltage of the first direct current power source becomes substantially zero, A positive gate voltage is applied to the gate input terminal by closing the second switch so that the gate oxide film electric field of the n-channel transistor and the p-channel transistor forming the CMOS inverter circuit becomes 3 MV / cm or more. Semiconductor device. 3. A first DC power supply for electrically connecting to a power supply terminal of a CMOS logic gate composed of nMOS and pMOS transistors via a first switch to supply a power supply voltage, and gates of the nMOS and pMOS transistors. A second DC power source electrically connected to the input terminal via a second switch, and when the supply voltage of the first DC power source opened by the first switch becomes substantially 0,
By closing the second switch, a positive gate voltage is applied to the gate input terminal so that the gate oxide film electric field of the n-channel transistor and the p-channel transistor forming the CMOS logic gate becomes 3 MV / cm or more. Characteristic semiconductor device. 4. A first direct-current power supply for supplying a power supply voltage of a CMOS LSI chip and a battery as an alternative power supply to the first direct-current power supply; and a second direct-current power supply. And a power supply voltage from the battery, which is supplied with the power supply voltage from the battery when the supply voltage of the first DC power supply becomes substantially 0 Second L not supplied
The gate of the second LSI part including the SI part is electrically cut off from the CMOS LSI chip or the supply voltage of the first DC power supply is substantially 0 A positive gate voltage is applied to the input terminal from the second DC power supply, and the gate oxide film electric field of the n-channel transistor and the p-channel transistor forming the second LSI portion is set to 3 MV / cm or more. Semiconductor device.