JPH0850564A - Control table management system - Google Patents

Abstract

PURPOSE:To improve the convenience of a flash I/O card FIO, etc., and to improve reliability at the time of unexpected fault generation by shortening average required time for control table saving processing when the power source of the flash I/O card FIO or the like is turned off. CONSTITUTION:Concerning the flash I/O card FIO or the like provided with a flash memory file FMF composed of a nonvolatile semiconductor memory such as a flash memory and a random access memory RAM composed of a nonvolatile semiconductor memory such as a pseudo static RAM and provided with a control table TBL for the sector management or the like of the flash memory file FMF, the control table TBL inside the random access memory RAM is cyclically copied to a saving table STBL inside the flash memory file FMF in a prescribed cycle, when the power source is turned off, the held contents of the control table TBL and the saving table STBL at that time point are compared and collated and only when both the contents are not matched, the saving operation of the control table TBL is selectively executed.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a control table management system, for example, a flash I / O card equipped with a control table for sector management and an efficient saving process of the control table when the power is turned off. Especially effective technology.

[0002]

2. Description of the Related Art There is a flash I / O card (flash file system) which has a memory file composed of a non-volatile semiconductor memory such as a flash memory as its basic constituent element and is coupled to a hard disk interface of a personal computer or the like. The storage area of the memory file of the flash I / O card is divided into sectors in a predetermined unit so as to correspond to that of the hard disk.
Further, the flash I / O card is provided in a volatile semiconductor memory such as a pseudo static RAM (random access memory) or the like, and makes a logical address viewed from the system side correspond to a physical address of each sector of the memory file. It is provided with a logical sector table and a control table such as an erase management table for averaging the number of times of rewriting of each sector by dynamically exchanging a sector with a large number of times of rewriting and a sector with a small number of times of rewriting.

An information processing system such as a flash I / O card (flash file system) having a control table and a personal computer including the flash I / O card is described in, for example, Japanese Patent Application No. 4-318159.

[0004]

In the conventional flash I / O card FIO described above, the control table TBL provided in the random access memory RAM such as the pseudo static RAM is shown in FIG. In addition, when the power of the system is turned off, the data is saved in the save area in the memory file, that is, the flash memory file FMF via the microcomputer MC serving as the control means, and becomes the save table STBL. This save table STBL
Is a random access memory R when the system is turned on.
The control table TBL is read in the AM table area.
Is reproduced as.

However, as the flash I / O card becomes larger in capacity and its storage area becomes larger in scale, the following problems occur in the conventional control table saving method. Etc. That is, in the flash memory that constitutes the flash memory file FMF, as is well known, the stored data is rewritten in units of blocks corresponding to a sector or a plurality of sectors. ) And about 10 μs per byte to write new data. Therefore, for example, even if one block that is a unit of erasing / rewriting is set to 64 KB (kilobytes) and all the control tables can be stored in this one block, the time Ts required for saving the control table at the time of power-off is Is Ts = 1 + 10 × 10 ⁻⁶ × 64 × 10 ³ = 1.64, that is, 1.64 seconds, which is the flash I / O.
This is one of the factors that reduce the convenience of the card and the reliability in the event of a sudden failure.

An object of the present invention is to reduce the average time required for the control table saving process when the power of a flash I / O card or the like is cut off. Another object of the present invention is to enhance the convenience of a flash I / O card having a control table and the like, and to enhance the reliability in the event of a sudden failure.

The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

[0008]

The outline of the representative one of the inventions disclosed in the present application will be briefly described as follows. That is, the memory file includes a non-volatile semiconductor memory such as a flash memory, and the random access memory including a volatile semiconductor memory such as a pseudo static RAM and a control table for sector management of the memory file. Flash I
In an I / O card or the like, the control table in the random access memory is periodically transferred to the save area in the memory file as a save table at a predetermined cycle, and when the power is turned off, the control table in the random access memory and the memory file The save table is compared and collated, and only when the two do not match, the save operation of the control table is selectively executed.

[0009]

According to the above-mentioned means, with a relatively high probability, the save operation of the control table to the save area at the time of power-off is eliminated, and the average time required for the save process of the control table of the flash I / O card or the like is compared between the tables. The time required for verification can be shortened to approximately 128 milliseconds, and even when a sudden failure occurs such that the save operation cannot be executed.
A copy of the latest control table can be kept in the memory file. As a result, it is possible to enhance the convenience of the flash I / O card having the control table and the reliability in the event of a sudden failure.

[0010]

1 is a system configuration diagram of an embodiment of a personal computer including a flash I / O card FIO to which the present invention is applied. An outline of the configuration and operation of a personal computer including a flash I / O card will be described first with reference to FIG. It should be noted that the block surrounded by the dotted line in FIG. 1 is mounted in one box body as the main body of the personal computer, and the block outside the dotted line is selectively equipped with a corresponding connector or the like as its option.

In FIG. 1, a personal computer of this embodiment is a central processing unit CPU of a stored program system, and a system bus SB is connected to the central processing unit CPU.
It comprises an auxiliary processing unit CCPU, a memory control unit MCU and a bus control unit BCU which are coupled via the US. Of these, the auxiliary processing device CCPU is a processing device of a stored program system similar to the central processing device CPU, and assists a part of the processing of the central processing device CPU. Further, the memory control unit MCU has a memory bus MBUS.
Via the main memory MMEM and extended memory EMEM
Connected to the system bus SBUS and memory bus MB
Bus control between US is performed. The main memory MMEM and the extended memory EMEM are, for example, dynamic RAs.
It is constructed on the basis of M and becomes the center of the storage hierarchy of the personal computer.

On the other hand, the bus control unit BCU includes a read-only memory ROM, an input / output bus IOBUS, and a read-only memory ROM.
Display device adapter DPYA, keyboard controller KBDC, floppy disk device FDD, serial port interface SPIF, parallel port interface PPIF, and flash I / O card controller FIO
Is connected to C and these input / output devices and system bus SB
Performs bus control with the US. Of the input / output devices coupled to the input / output bus IOBUS, the read-only memory R
The OM is configured based on, for example, an EEPROM (electrically erasable / writable read-only memory) and stores programs and fixed data necessary for step control of the central processing unit CPU. Further, the display device adapter DPYA is coupled with a display device DPY centering on a CRT (cathode ray tube), and a keyboard control unit KB is provided.
In the DC and flash I / O card control unit FIOC,
A keyboard KBD and a flash I / O card FIO are connected to each other. Further, a serial input / output device such as a communication control device (not shown) is coupled to the serial port interface SPIF, and a parallel input / output device such as a printer (not shown) is coupled to the parallel port interface PPIF.

In this embodiment, the flash I / O card controller FIOC has the same interface condition as the hard disk device and is compatible with this. As will be described later, the flash I / O card FIO has a flash memory file FMF composed of a flash memory as its basic constituent element, and the storage area of this flash memory file is divided into sectors corresponding to the hard disk.

FIG. 2 is a block diagram showing an embodiment of the flash I / O card FIO included in the personal computer shown in FIG. A specific configuration and operation of the flash I / O card FIO will be described with reference to FIG.

In FIG. 2, the flash I / O card F
The IO includes a stored program type microcomputer MC and a flash memory file FMF coupled to the microcomputer MC via a card internal bus IBUS. A card controller CC, a program memory PROM, and a random access memory RAM are further coupled to the card internal bus IBUS, and a clock generator CPG and a timer circuit TIM are coupled to the microcomputer MC.

Here, the flash memory file FMF
Is a non-volatile semiconductor memory (first semiconductor memory) such as a flash memory having a relatively large storage capacity, and serves as a main storage means of the flash I / O card FIO. In this embodiment, the storage area of the flash memory file FMF is divided into sectors corresponding to the hard disk, and the blocks of stored data are erased in units of this sector. In addition, the flash memory file F
In the MF, a save table STBL which is a save area when the power of the control table TBL of the random access memory RAM is cut off is provided. This save table corresponds to the control table TBL of the random access memory RAM and the logical sector table SLST. , Physical sector table SPS
T, erase management table SEMT and bad sector table SBST. The flash memory file F
In the flash memory forming the MF, erase / rewrite of stored data is performed in units of, for example, a block of 64 KB, and therefore, the write operation is performed as described below.
It will be slow enough to exceed a second.

On the other hand, the card controller CC includes an interface controller IFC, a register group REGG and a command decoder COMD. Among them, the interface controller IFC uses the flash I via the file enable signal FE and the read / write signal R / W which are the activation control signals and the data transfer confirmation signal ACK.
/ O card control unit FIOC, flash I /
O card control unit FIOC and flash I / O card F
Performs interface control between IOs. Further, the register group REGG is coupled to the flash I / O card control unit FIOC via a file access bus FBUS, and the interface controller receives control data such as commands and start and end addresses supplied via the file access bus. Capture and hold according to IFC instructions. Further, the command decoder COMD decodes the command held by the command register of the register group REGG and transmits the result to the interface controller IFC. The interface controller IFC receives the decoding result of the command decoder COMD, determines the operation mode of the flash I / O card FIO, asserts the interrupt request signal IRQB, and starts accessing the flash memory file FMF to the microcomputer MC. Etc.

The register group REGG includes a file status register, and a predetermined bit of this file status register has a flash I / O from the system side.
It is used as a power supply flag for notifying the card FIO of power off. In addition, other predetermined bits of the file status register are, on the contrary, the flash I / O card FIO
Is used as a save process end flag for notifying the system side that the control table save process at the time of power off is completed.

Next, the random access memory RAM is
A write data buffer for temporarily storing a series of write data and a control table TBL for sector management, which includes a volatile semiconductor memory (second semiconductor memory) such as a pseudo static RAM having a relatively high write speed.
Etc. In this embodiment, the control table TB
L is not particularly limited, but the logical sector table LS
T, physical sector table PST, erase management table EM
T and bad sector table BST. this house,
The logical sector table LST is used for associating the logical address viewed from the system side with the sector of the flash memory file FMF, that is, the physical address, and the physical sector table PST is used for mapping the logical address assigned to each physical address. . The erase management table EMT is used to manage the erase count of each sector and average the number of rewrites, and the defective sector table BST is used to manage the sector having a defective characteristic.

By the way, random access memory RAM
Logical sector table L constituting the control table TBL of
ST, physical sector table PST, erase management table E
MT and bad sector table BST are flash I /
The stored contents are rewritten and updated as the operation of the O card FIO progresses. Therefore, in this embodiment, as described above, the logical sector table SLST and the physical sector table S are stored in the flash memory file FMF.
A save table STBL including a PST, an erase management table SEMT, and a defective sector table SBST is provided, and a control table TBL of the random access memory RAM is held at a predetermined cycle and at intervals of normal operation of the flash I / O card FIO. The contents are periodically transferred to the save area in the flash memory file FMF, that is, the save table STBL. When the power of the system is turned off, the contents held in the control table TBL of the random access memory RAM at that time and the contents held in the save table STBL of the flash memory file FMF are compared and collated, and then the two do not completely match. Only in such a case, the save operation of the control table TBL to the save table STBL is selectively executed, whereby the average predetermined time of the control table save processing of the flash I / O card FIO is shortened. The specific saving operation of the control table TBL and its characteristics will be described later in detail.

On the other hand, the program memory PROM is EE
It is composed of a PROM or the like and stores programs for access control of the microcomputer MC, sector management, and the like. The clock generator CPG also generates a clock signal necessary for the synchronous operation of the microcomputer MC, and the timer circuit TIM is used for time management of the microcomputer MC. The microcomputer MC controls access to the flash memory file FMF according to the control program stored in the program memory PROM, and uses the control table TBL in the random access memory RAM to control the flash memory file FMF.
Sector management, and selectively and dynamically execute sector replacement processing according to the number of erases,
Average the number of rewrites in each sector. In addition, by the time management with the timer circuit TIM, the contents held in the control table TBL of the random access memory RAM are periodically transferred to the save table STBL of the flash memory file FMF at a predetermined cycle, and the control is performed when the system is powered off. Table TBL and save table STBL
After comparing and collating the stored contents of the above, only when the two do not match, the save table STBL of the control table TBL
The save operation to is selectively executed.

FIG. 3 shows a processing procedure diagram of an embodiment for explaining the control table management method of the flash I / O card FIO of FIG. 2, and FIG. 4 shows an example of the control table saving processing. A flow diagram of an embodiment is shown. Based on these figures, the flash I / O card F of this embodiment
The details and features of the IO control table management method and the control table saving process when the power is turned off will be described.

In FIG. 3, the flash I / O card F
The microcomputer MC, which is the control means of the IO, receives the power-on, that is, the power-on of the system side and executes the rising process, and one of them is the save table ST of the flash memory file FMF which is a non-volatile memory.
The stored contents of BL are read into the control table TBL of the random access memory RAM which is a volatile memory. Also,
When the reading of the control table is completed, the timer circuit TIM is activated to start measuring the transfer cycle Tsv of the control table. After that, the microcomputer MC
Random access memory RA with relatively high writing speed
Various arithmetic processes are efficiently executed based on the control table TBL in the M, and the flash I / O card FI
The contents held in the control table TBL are rewritten and updated in accordance with the progress of the operation of O.

Next, when the timing of the transfer cycle Tsv by the timer circuit TIM is completed, the microcomputer MC
Is the save table S of the flash memory file FMF.
The block corresponding to TBL is erased, and the contents held in the control table TBL of the random access memory RAM are read and transferred to the save area of the flash memory file FMF, that is, the save table STBL. When the transfer of the control table is completed, the timer circuit TIM
Is restarted and the timing of the transfer time Tsv in the control table is restarted. After that, the microcomputer MC repeats the same time measurement and transfer operation while seeing the interval of the normal access processing, whereby the flash memory file F
The contents held in the save table STBL of the MF are rewritten so as to match the latest contents held in the control table TBL of the random access memory RAM. As a result, there is a sufficiently high probability that the contents held in the save table STBL of the flash memory file FMF at the time of power-off and the contents held in the control table TBL of the random access memory RAM at that time point match.

By the way, when the power-off, that is, the power-off is notified from the system side via the file status register of the card controller CC, the microcomputer MC firstly holds the contents held in the control table TBL of the random access memory RAM and the flash memory file. F
The stored contents of the save table STBL of the MF are sequentially read out and compared and compared. At this time, the microcomputer MC, as shown in FIG.
After presetting the address counter ADC to zero by means of steps ST2 and ST3, the table data TDA and TDB at the start address of the control table TBL of the random access memory RAM and the save table STBL of the flash memory file FMF are read out respectively, and both are carried out at step ST4. Compare and collate by.
As a result, if these table data match, the address counter ADC is updated in step ST5. In step ST6, it is determined whether or not the value of the address counter ADC is the final value, that is, the comparison and collation of the table data has been completed for all the addresses. If the final address has not been reached yet, the above-mentioned processing from step ST2 is repeated, When the address is finished, the control table TB of the random access memory RAM
The saving process is terminated without saving L. The end of the control table save process is notified to the system via the save process end flag of the file status register of the card controller CC as described above.

On the other hand, if the table data TDA and TDB do not match in step ST4, the microcomputer MC immediately suspends the table data comparing and collating operation and starts the saving operation of the control table TBL of the random access memory RAM. At this time, the microcomputer MC first starts the erase operation of the corresponding block of the save table STBL of the flash memory file FMF in step ST7. After the end of the erase operation, the address counter ADC is preset in step ST8, and then the control table TBL of the random access memory RAM is set in step ST9.
Read the table data TDC of the start address from
Flash memory file FM in step ST10
Write to the start address of the save table STBL of F.
Then, the table data saving operation in steps ST9 and ST10, the update of the address counter ADC in step ST11, and the step ST12.
Repeat the address judgment with all addresses,
The control table saving process ends.

As is well known, a pseudo static RAM
The read operation of the random access memory RAM consisting of the above and the flash memory file FMF consisting of the flash memory are both completed in a relatively short time of, for example, about 1 μs per byte. Therefore, when the storage area of the block corresponding to the control table TBL and the save table STBL is set to 64 KB, the time Tc required for the table data read and comparison / comparison operations for all addresses is: Tc = 1 × 10 ⁻⁶ × 64 × 10 ³ × 2 = 128 × 10 ^−3, that is, 128 ms (millisecond). As a result, the save processing time Ts when the stored contents of the control table TBL and the save table STBL completely match and the save operation of the control table TBL is not required is only 128 ms required for this read / comparison operation. Will be greatly shortened.

On the other hand, when the stored contents of the control table TBL and the save table STBL do not completely match, especially when this mismatch occurs at the final address,
The control table save processing time Ts of the flash I / O card FIO is calculated in addition to the table data comparison and collation operation.
Block erase that takes about 1 second and about 10μ per byte
It becomes maximum due to the retracting operation of the control table TBL requiring s, and Ts = 1 × 10 ⁻⁶ × 64 × 10 ³ × 2 + 1 + 10 × 10 ⁻⁶ × 64 × 10 ³ = 1.768, that is, 1.768 seconds. Reach However, in the flash I / O card FIO of this embodiment, as described above, the control table TBL of the random access memory RAM is periodically added to the save table STBL of the flash memory file FMF at a predetermined cycle and in between the normal operations. And the probability that the contents held in both tables match when the power is turned off is sufficiently high. Therefore, the average time required for the control table saving process of the flash I / O card FIO becomes a value close to the process time Tc when only the table data comparison and collation operation is performed, that is, 128 ms, and is sufficiently shortened. The latest copy of the control table can be retained in the memory file, including when a sudden failure occurs such that the save operation cannot be executed. As a result, it is possible to enhance the convenience of the flash I / O card provided with the control table and enhance the reliability in the event of a sudden failure.

The operation and effect obtained by the above embodiment are as follows. That is, (1) a memory file composed of a non-volatile semiconductor memory such as a flash memory, and a random access memory composed of a volatile semiconductor memory such as a pseudo static RAM and having a control table for sector management of the memory file. In a flash I / O card, etc. provided,
The control table in the random access memory is periodically transferred to the save area in the memory file as a save table at a predetermined cycle, and when the power is turned off, the control table in the random access memory and the save table in the memory file are compared. By collating and selectively executing the save operation of the control table only when both do not match,
With a relatively high probability, the save operation to the save area of the control table at power-off is eliminated, and the average time required for save processing of the control table such as a flash I / O card is about 128 mm necessary for comparing and collating table data. The effect is that it can be significantly shortened to about a second. (2) According to the above item (1), it is possible to enhance the convenience of the flash I / O card having the control table.

(3) According to the above item (1), the flash I
Even if a sudden failure such that the save operation cannot be executed in the / O card and the system including the same, the effect that the latest copy of the control table can be held in the memory file can be obtained. (4) According to the above item (3), it is possible to improve the reliability in the event of a sudden failure of the flash I / O card or the like.

Although the invention made by the present inventor has been specifically described based on the embodiments, the invention is not limited to the above embodiments, and various modifications can be made without departing from the scope of the invention. Needless to say. For example, in FIG. 1, the flash I / O card controller FI
The OC does not have to be coupled to the hard disk interface. In addition, the classification as the personal computer main body, the system configuration, the bus form, etc.
Various embodiments can be adopted.

In FIG. 2, the flash memory file FMF can be configured by, for example, an EEPROM, and the program memory PROM and random access memory RAM can also be configured by various other semiconductor memories. Further, in this embodiment, the control table T
The logical sector table LST, the physical sector table PST, the erase management table EMT, and the defective sector table BST forming the BL are all transferred or saved to the save table STBL of the flash memory file FMF. For example, the physical sector table PST is logical. Since it can be reproduced based on the sector table LST, it can be excluded from the target. The configuration of the control table TBL is not restricted by this embodiment, and the block configuration of the flash I / O card FIO, its bus form, the control table management procedure and the save processing flow shown in FIGS. Various embodiments can be adopted.

The control table TBL of the random access memory RAM is periodically stored in the flash memory file FMF.
Cycle management for transferring to the evacuation table STBL of
As shown in FIG. 5, it can be performed by a timer circuit TIM2 provided in the card controller CC. Further, as shown in FIG. 6, a table transfer controller TDTC is provided in the card controller CC, and the table transfer controller TDTC is used by the table transfer controller TDTC.
The transfer to the save table STBL may be controlled. In this case, the comparison and collation operation of the table when the power is turned off is also performed by the microcomputer MC, but the evacuation operation when the two tables do not match may be transferred to the table transfer controller TDTC.

In the above description, the invention mainly made by the present inventor is applied to a flash I / O card and a personal computer including the flash I / O card, which is the field of application of the invention, but the invention is not limited thereto. However, the present invention can be applied to, for example, various semiconductor memory files that do not take a card form and various digital systems including memory files. INDUSTRIAL APPLICABILITY The present invention can be widely applied to a system including at least a nonvolatile semiconductor memory provided for a memory file and a volatile semiconductor memory provided for a control table, and a control table management thereof.

[0035]

The effects obtained by the typical ones of the inventions disclosed in the present application will be briefly described as follows. That is, a flash including a memory file including a non-volatile semiconductor memory such as a flash memory and a random access memory including a volatile semiconductor memory such as a pseudo-static RAM and including a control table for sector management of the memory file. I
In an I / O card or the like, the control table in the random access memory is periodically transferred to the save area in the memory file as a save table at a predetermined cycle, and when the power is turned off, the control table in the random access memory and the memory file By comparing and collating with the save table of the control table and selectively executing the save operation of the control table only when the two do not match, there is a relatively high probability that the save operation of the control table to the save area at power-off is eliminated. ,
The average time required to save the control table of a flash I / O card or the like can be significantly reduced to about 128 milliseconds required for comparison and collation of table data, and the save operation cannot be executed suddenly. It is possible to keep a copy of the latest control table in the memory file, including when a major failure occurs. As a result, it is possible to enhance the convenience of the flash I / O card having the control table and the reliability in the event of a sudden failure.

[Brief description of drawings]

FIG. 1 is a system configuration diagram showing an embodiment of a personal computer including a flash I / O card to which the present invention is applied.

2 is a block diagram showing an embodiment of a flash I / O card included in the personal computer of FIG.

3 is a processing procedure diagram showing an embodiment for explaining a control table management method of the flash I / O card of FIG.

FIG. 4 is a flowchart showing an embodiment of a control table saving process of the flash I / O card of FIG.

FIG. 5 is a block diagram showing a second embodiment of a flash I / O card to which the present invention is applied.

FIG. 6 is a block diagram showing a third embodiment of a flash I / O card to which the present invention is applied.

FIG. 7 is a processing procedure diagram showing an example for explaining a control table management method for a flash I / O card developed by the inventors of the present application prior to the present invention.

8 is a flowchart showing an example of a control table saving process of the flash I / O card of FIG.

[Explanation of symbols]

CPU ... Central processing unit, SBUS ... System bus, CCPU ... Auxiliary processing unit, MCU ... Memory control unit, MBUS ... Memory bus, MMEM.
..Main memory, EMEM ... Extended memory, BCU
... Bus control unit, IOBUS ... Input / output bus, ROM ... Read-only memory, DPYA ...
Display device adapter, DPY ... Display device, KBDC ... Keyboard control unit, KBD ...
・ Keyboard, FDD ... Floppy disk device, S
PIF: serial port interface, PPIF
... Parallel port interface, FIOC ...
Flash I / O card controller, FIO ... Flash I / O card. CC: Card controller, IF
C ... Interface controller, REGG ...
Register group, COMD ... Command decoder, IBU
S ... Card internal bus, MC ... Microcomputer, CPG ... Clock generator, TIM, TIM1
~ TIM2 ... Timer circuit, PROM ... Program ROM (read only memory), RAM ... Random access memory, FMF ... Flash memory file, TBL ... Control table, STBL ...
Evacuation table, LST, SLST ... Logical sector table, PST, SPST ... Physical sector table, E
MT, SEMT ... Erase management table, BST, SB
ST: Bad sector table. TDTC: Table transfer controller.

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Hirohiko Yoshida 5-20-1 Kamimizuhoncho, Kodaira-shi, Tokyo Inside Hiritsu Cho-LS Engineering Co., Ltd. (72) Inventor Takashi Kikuchi Tokyo 5-20-1 Kamimizuhoncho, Kodaira-shi Hitsudori Super S.I. Engineering Co., Ltd. (72) Inventor Kyoo Okubo 5-20-1 Kamimizuhoncho, Kodaira-shi, Tokyo SII Engineering Co., Ltd. (72) Inventor Shigeru Kadowaki 5-20-1 Kamimizuhonmachi, Kodaira-shi, Tokyo Hiratsuru LSI Engineering Co., Ltd. (72) Inventor Masamichi Kishi Tokyo 5-20-1 Kamimizuhonmachi, Kodaira-shi Hiritsu Cho-LS Engineering Co., Ltd. (72) Inventor Hirohito Fukuda 5-20-1 Kamimizuhonmachi, Kodaira-shi, Tokyo Within Hitsuritsu Cho-LS Engineering Co., Ltd. (72) Inventor Kunihiro Katayama 1099, Ozenji Temple, Aso-ku, Kawasaki-shi, Kanagawa Ltd. Inside Hitachi Systems Development Laboratory (72) Inventor Toshio Kanno 5-20-1 Kamimizuhonmachi, Kodaira-shi, Tokyo Incorporated company Hitachi Ltd. Semiconductor Business Division

Claims (3)

[Claims] 1. A volatile first having a relatively high writing speed.
The contents of the control table provided in the semiconductor memory of FIG. 3 and selectively updated as the operation progresses are saved in a save area provided in the nonvolatile second semiconductor memory in which the writing speed is relatively slow at a predetermined cycle. A control table management method characterized by periodical transfer. 2. The contents of the control table when the power is turned off are selectively saved in the save area only when they do not match the contents of the save area at that time. 1. Control table management method. 3. The first and second semiconductor memories are included in a flash I / O card, and the first semiconductor memory comprises a pseudo static RAM, and the second semiconductor memory. Is a flash memory.
Control table management method.