JPH08153719A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPH08153719A JPH08153719A JP6294263A JP29426394A JPH08153719A JP H08153719 A JPH08153719 A JP H08153719A JP 6294263 A JP6294263 A JP 6294263A JP 29426394 A JP29426394 A JP 29426394A JP H08153719 A JPH08153719 A JP H08153719A
- Authority
- JP
- Japan
- Prior art keywords
- wiring
- interlayer insulating
- insulating film
- aluminum
- polyimide
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/04042—Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0555—Shape
- H01L2224/05556—Shape in side view
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
- H01L2224/45099—Material
- H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/45117—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
- H01L2224/45124—Aluminium (Al) as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/484—Connecting portions
- H01L2224/48455—Details of wedge bonds
- H01L2224/48456—Shape
- H01L2224/48458—Shape of the interface with the bonding area
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/484—Connecting portions
- H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/484—Connecting portions
- H01L2224/4847—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Electrodes Of Semiconductors (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
Description
【０００１】[0001]
【産業上の利用分野】本発明は、多層配線構造を有する
半導体装置に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device having a multilayer wiring structure.
【０００２】[0002]
【従来の技術】従来、半導体装置に多層配線を形成する
場合、層間絶縁膜にはＳｉＯ2 が用いられてきたが、層
間絶縁性、コンタクト用窓の段差の緩和および製造上の
便利さからポリイミド等の合成樹脂系の絶縁物が用いら
れるようになってきている。2. Description of the Related Art Conventionally, when a multilayer wiring is formed in a semiconductor device, SiO 2 has been used as an interlayer insulating film. However, polyimide is used because of its interlayer insulating property, relief of step difference in contact window, and convenience in manufacturing. Synthetic resin-based insulators such as those have come to be used.
【０００３】図３は従来の半導体装置の一例の平面図お
よび断面図である。FIG. 3 is a plan view and a sectional view of an example of a conventional semiconductor device.
【０００４】シリコン基板１に能動素子領域としてゲー
ト領域２、ソース領域３を形成し、アルミニウムでゲー
ト領域２に接続する第１配線４を形成する。ポリイミド
の第１層間絶縁膜５で表面を覆い、ソース領域３の上を
開口し、第１配線４を絶縁被覆する。アルミニウムでソ
ース領域３に接続する第２配線６を形成する。アルミニ
ウム線７を第２配線６に接続する。A gate region 2 and a source region 3 are formed as active element regions on a silicon substrate 1, and a first wiring 4 connected to the gate region 2 is formed of aluminum. The surface is covered with a first interlayer insulating film 5 of polyimide, the source region 3 is opened, and the first wiring 4 is insulation-coated. The second wiring 6 connected to the source region 3 is formed of aluminum. The aluminum wire 7 is connected to the second wiring 6.
【０００５】この形状は、ソース領域とゲート領域２と
をインターディジットの関係（指と指とを組み合わせた
形状）に配置しているので、一つのソース領域に流れる
電流が少なくなり、電流集中を緩和している。また、ア
ルミニウム線７ををソース領域３の上でボンディング接
続しているから、専用ボンディング・パッド・エリアを
必要とせず、チップ面積を縮小できるという利点があ
る。In this shape, since the source region and the gate region 2 are arranged in an interdigit relationship (shape in which fingers are combined with each other), the current flowing in one source region is reduced and current concentration is reduced. Has eased. Further, since the aluminum wire 7 is bonded and connected on the source region 3, there is an advantage that a dedicated bonding pad area is not required and the chip area can be reduced.
【０００６】図４は図３に示す半導体装置の製造方法を
説明するための工程順に示した断面図である。4A to 4D are cross-sectional views showing the method of manufacturing the semiconductor device shown in FIG. 3 in order of steps.
【０００７】図４（ａ）に示すように、シリコン基板１
に能動素子領域としてゲート領域２、ソース領域３を熱
拡散またはイオン注入法で形成する。マスク１１を設
け、アルミニウムでゲート領域２に接続する第１配線４
を形成する。そして、マスク１１を除去する。As shown in FIG. 4A, the silicon substrate 1
A gate region 2 and a source region 3 are formed as active element regions by thermal diffusion or ion implantation. First wiring 4 provided with mask 11 and connected to gate region 2 with aluminum
To form. Then, the mask 11 is removed.
【０００８】次に、図４（ｂ）に示すように、新しくマ
スク（図示せず）を用いてポリイミドで第１層間絶縁膜
５を形成して第１配線４を覆って絶縁し、ソース領域３
の上を開口する。そして、マスクを除去する。Next, as shown in FIG. 4B, a first mask 4 (not shown) is used to form a first interlayer insulating film 5 of polyimide to cover the first wiring 4 and insulate the source region. Three
Open the top. Then, the mask is removed.
【０００９】次に、図４（ｃ）に示すように、アルミニ
ウムでソース領域３に接続する第２配線６を形成する。Next, as shown in FIG. 4C, a second wiring 6 connected to the source region 3 is formed of aluminum.
【００１０】次に、図４（ｄ）に示すように、超音波ボ
ンディング法でアルミニウム線７を第２配線６に接続す
る。Next, as shown in FIG. 4D, the aluminum wire 7 is connected to the second wiring 6 by the ultrasonic bonding method.
【００１１】図５は従来の半導体装置の他の例の平面図
である。FIG. 5 is a plan view of another example of the conventional semiconductor device.
【００１２】図３に示した種類の半導体装置は色々の形
に変形することができる。図５（ａ）に示すものは、ソ
ース領域３を二つに分け、ソース領域とソース領域の間
にゲート領域２を設け、各々のソース領域３上の第２配
線６にアルミニウム線７を接続したものである。この形
状は、ソース領域を多数個に分割し、アルミニウム線７
でつないでいるので、一つのソース領域に流れる電流が
少なくなり、電流集中を緩和し、しかもアルミニウム線
７をソース領域３上の第２配線６でボンディング接続し
ているから、専用ボンディング・パッド・エリアを必要
とせず、チップ面積を縮小できるという利点がある。The semiconductor device of the type shown in FIG. 3 can be modified in various ways. In the structure shown in FIG. 5A, the source region 3 is divided into two, the gate region 2 is provided between the source regions, and the aluminum line 7 is connected to the second wiring 6 on each source region 3. It was done. This shape divides the source region into a number of aluminum wires 7
Since they are connected to each other, the current flowing in one source region is reduced, current concentration is alleviated, and the aluminum wire 7 is connected by the second wiring 6 on the source region 3, so that a dedicated bonding pad, There is an advantage that the chip area can be reduced without requiring an area.
【００１３】図５（ｂ）に示すものは、図３に示したも
のと類似であるが、ソース領域３につながる専用ボンデ
ィング・パッド・エリア１０を設けた点において異なっ
ている。この形にすると、ゲート領域２に接続する第１
配線４と、ソース領域３に接続する第２配線６とが同一
平面上に同時に形成でき、製造工程数を減らすことがで
きるという利点がある反面、専用ボンディング・パッド
・エリア１０の分だけチップ面積が大きくなるという欠
点がある。勿論、図３（ｂ）に示したような多層配線構
造にすることもできる。The structure shown in FIG. 5B is similar to the structure shown in FIG. 3 except that a dedicated bonding pad area 10 connected to the source region 3 is provided. With this shape, the first region connected to the gate region 2
The wiring 4 and the second wiring 6 connected to the source region 3 can be simultaneously formed on the same plane, which has the advantage that the number of manufacturing steps can be reduced, but the chip area is reduced by the dedicated bonding pad area 10. Has the drawback of becoming large. Of course, a multi-layer wiring structure as shown in FIG.
【００１４】[0014]
【発明が解決しようとする課題】上述のように、第１層
間絶縁膜５にポリイミドを用い、図３（ａ）または図５
（ａ）に示すようにソース領域３の上でアルミニウム線
７を超音波ボンディング法で接続した場合、図６に示す
ように、第２配線６が第１層間絶縁膜５から剥がれると
いうボンディング不良が発生することがある。これは、
ポリイミドとアルミニウムとの密着性が余り強くないた
めと、多層配線構造による段差の所でアルミニウムの第
２配線６が薄くなっていて切れ易くなっているためと考
えられる。ボンディング不良が発生すると、信頼性が低
下するのみならず、歩留りが低下するのでコストが高く
なるという問題がある。As described above, polyimide is used for the first interlayer insulating film 5, and the first interlayer insulating film 5 shown in FIG.
When the aluminum wire 7 is connected on the source region 3 by the ultrasonic bonding method as shown in (a), the second wiring 6 is peeled off from the first interlayer insulating film 5 as shown in FIG. May occur. this is,
It is considered that the adhesion between the polyimide and aluminum is not so strong, and that the second wiring 6 made of aluminum is thin and easy to be cut at the step due to the multilayer wiring structure. When a bonding failure occurs, not only the reliability is lowered, but also the yield is lowered, so that there is a problem that the cost is increased.
【００１５】図５（ｂ）に示すように、段差のない専用
ボンディング・パッド・エリア１０を設け、ここにアル
ミニウム線７をボンディングすると第２配線６の剥がれ
を減らすことができるが、専用ボンディング・パッド・
エリア１０を設けた分だけチップ面積が大きくなるとい
う問題と、図３（ａ）または図５（ａ）に示したように
必要に応じてソース領域３の形状を自由に変えることが
できなくなり、設計の自由度が制限されるという問題が
ある。As shown in FIG. 5B, if a dedicated bonding pad area 10 having no step is provided and an aluminum wire 7 is bonded thereto, peeling of the second wiring 6 can be reduced. pad·
The problem that the chip area is increased by providing the area 10 and the shape of the source region 3 cannot be freely changed as necessary as shown in FIG. 3A or FIG. There is a problem that the degree of freedom in design is limited.
【００１６】本発明の目的は、アルミニウム線の超音波
ボンディングにおいて、アルミニウムの第２配線とポリ
イミドの第１層間絶縁膜との間に剥がれによる歩留り低
下とコスト高を防ぎ、信頼性を高め、設計の自由度の確
保、ソース・ボンディング・パッドの削除によるチップ
面積の低減、電流集中の緩和が実現できる半導体装置を
提供することにある。An object of the present invention is to improve the reliability and design in ultrasonic bonding of aluminum wires by preventing a decrease in yield and cost due to peeling between the second wiring of aluminum and the first interlayer insulating film of polyimide, and by increasing the cost. It is an object of the present invention to provide a semiconductor device in which the degree of freedom can be secured, the chip area can be reduced by eliminating the source bonding pad, and the current concentration can be relaxed.
【００１７】[0017]
【課題を解決するための手段】本発明は、能動素子領域
が設けられている半導体基板上に複数層の配線層の各々
が合成樹脂系の第１層間絶縁膜で絶縁されて形成されて
いる多層配線構造を有する半導体装置において、前記第
１層間絶縁膜がポリイミドからなり、少なくとも最上層
の前記第１層間絶縁膜とその上の配線層との間にリンを
含むガラスの第２層間絶縁膜を設けたことを特徴とす
る。According to the present invention, each of a plurality of wiring layers is formed on a semiconductor substrate on which an active element region is provided, insulated by a synthetic resin first interlayer insulating film. In a semiconductor device having a multilayer wiring structure, the first interlayer insulating film is made of polyimide, and a second glass interlayer insulating film containing phosphorus between at least the uppermost first interlayer insulating film and a wiring layer thereabove. Is provided.
【００１８】本発明は、前記第２層間絶縁膜が前記ポリ
イミドを熱分解させない低温度で形成されるリンを含む
ガラスからなることを特徴とする。The present invention is characterized in that the second interlayer insulating film is made of glass containing phosphorus which is formed at a low temperature so as not to thermally decompose the polyimide.
【００１９】本発明は、前記第２層間絶縁膜がリン珪酸
ガラスからなることを特徴とする。The present invention is characterized in that the second interlayer insulating film is made of phosphosilicate glass.
【００２０】本発明は、前記第２層間絶縁膜がホウリン
珪酸ガラスからなることを特徴とする。The present invention is characterized in that the second interlayer insulating film is made of borophosphosilicate glass.
【００２１】[0021]
【作用】アルミニウム線の超音波ボンディングにおい
て、アルミニウムの第２配線とポリイミドの第１層間絶
縁膜との間に剥がれを生ずるのは、アルミニウムとポリ
イミドとの密着性が余り強くないことに起因する。剥が
れを防止するためには、アルミニウムとポリイミドの両
方に密着性の良い材料を設けるのが良い。このような材
料としてリンを含むガラスが選ばれる。リンを含まない
珪酸ガラスを第２層間絶縁膜として用いると第２層間絶
縁膜にクラックが入ることから、リンが珪酸ガラスの熱
膨張率を大きくしてポリイミドの熱膨張率に近づけると
同時に、ポリイミドとの密着性を改善していると考えら
れる。リンを含む珪酸ガラスはアルミニウムその他の金
属との密着性が良好であるので、超音波ボンディングに
おいてアルミニウムの第２配線とポリイミドの第１層間
絶縁膜との間に剥がれを生ずることはない。In the ultrasonic bonding of the aluminum wire, the peeling between the second wiring of aluminum and the first interlayer insulating film of polyimide is caused because the adhesion between aluminum and polyimide is not so strong. In order to prevent peeling, it is preferable to provide both aluminum and polyimide with a material having good adhesion. A glass containing phosphorus is selected as such a material. When phosphorus-free silicate glass is used as the second interlayer insulating film, cracks occur in the second interlayer insulating film. Therefore, phosphorus increases the coefficient of thermal expansion of silicate glass to approach that of polyimide, and at the same time It is thought that the adhesiveness with is improved. Since the silicate glass containing phosphorus has good adhesion to aluminum and other metals, peeling does not occur between the second wiring of aluminum and the first interlayer insulating film of polyimide in ultrasonic bonding.
【００２２】リンを含むガラスは、ポリイミドが熱分解
しない温度で形成しなければならない。ポリイミドが熱
分解すると絶縁機能を失うからである。ポリイミドの熱
分解温度は約４００℃であるから、第２層間絶縁膜は、
スパッタ法または４００℃未満の低温ＣＶＤ法で形成ス
ル。The glass containing phosphorus must be formed at a temperature at which the polyimide does not decompose thermally. This is because the insulating function is lost when the polyimide is thermally decomposed. Since the thermal decomposition temperature of polyimide is about 400 ° C., the second interlayer insulating film is
Formed by spattering or low temperature CVD below 400 ° C.
【００２３】リンを含むガラスとして、リン珪酸ガラス
が選ばれる。Phosphorus silicate glass is selected as the glass containing phosphorus.
【００２４】リンを含むガラスとして、ホウリン珪酸ガ
ラスが選ばれる。Boron silicate glass is selected as the glass containing phosphorus.
【００２５】[0025]
【実施例】図１は本発明の半導体装置の第１の実施例の
製造方法を説明するための工程順に示した断面図であ
る。1A to 1D are sectional views showing a method of manufacturing a semiconductor device according to a first embodiment of the present invention in the order of steps.
【００２６】図１（ａ）に示すように、シリコン基板１
に能動素子領域としてゲート領域２、ソース領域３を熱
拡散またはイオン注入法で形成する。マスク１１を設
け，アルミニウムでゲート領域２に接続する第１配線４
を形成する。そして、マスク１１を除去する。As shown in FIG. 1A, a silicon substrate 1
A gate region 2 and a source region 3 are formed as active element regions by thermal diffusion or ion implantation. First wiring 4 provided with mask 11 and connected to gate region 2 with aluminum
To form. Then, the mask 11 is removed.
【００２７】次に、図１（ｂ）に示すように、ポリイミ
ドを全面に被着して第１層間絶縁膜５を形成し、その上
にリン珪酸ガラスを被着して第２層間絶縁膜８を形成す
る。リン珪酸ガラスの第２層間絶縁膜８の形成に際し、
ポリイミドの熱分解温度（約４００℃）以下の低温で第
２層間絶縁膜８を形成し、ポリイミドを熱分解させない
ようにする必要がある。このような低温形成方法として
低温ＣＶＤ法またはスパッタ法がる。第２層間絶縁膜８
は、０．１〜２μｍ、好ましくは０．３〜１．２μｍの
厚さに形成する。Next, as shown in FIG. 1B, polyimide is deposited on the entire surface to form a first interlayer insulating film 5, and phosphosilicate glass is deposited thereon to form a second interlayer insulating film. 8 is formed. When forming the second interlayer insulating film 8 of phosphosilicate glass,
It is necessary to form the second interlayer insulating film 8 at a temperature lower than the thermal decomposition temperature of polyimide (about 400 ° C.) so that the polyimide is not thermally decomposed. As such a low temperature forming method, there is a low temperature CVD method or a sputtering method. Second interlayer insulating film 8
Is formed to a thickness of 0.1 to 2 μm, preferably 0.3 to 1.2 μm.
【００２８】次に、図１（ｃ）に示すように、ホトリソ
グラフィ技術を用いてソース領域３の上を開口してコン
タクト用窓１２をあける。Next, as shown in FIG. 1C, the contact window 12 is opened by opening the source region 3 by using the photolithography technique.
【００２９】次に、図１（ｄ）に示すように、アルミニ
ウムでソース領域３に接続する第２配線６を形成する。Next, as shown in FIG. 1D, a second wiring 6 connected to the source region 3 is formed of aluminum.
【００３０】次に、図１（ｅ）に示すように、超音波ボ
ンディング法でアルミニウム線７を第２配線６に接続す
る。Next, as shown in FIG. 1E, the aluminum wire 7 is connected to the second wiring 6 by the ultrasonic bonding method.
【００３１】リン珪酸ガラスをアルミニウムの第２配線
とポリイミドの第１層間絶縁膜との間に設けると、超音
波ボンディングにおけるアルミニウムの第２配線の剥が
れを防止するすることができる。これは、リン珪酸ガラ
スがアルミニウムとポリイミドの両方に密着性が良いこ
と、リン珪酸ガラスの熱膨張率がリンを含まないＳｉＯ
2 ガラスよりもポリイミドの熱膨張率に近いことによる
ものと考えられる。When phosphosilicate glass is provided between the aluminum second wiring and the polyimide first interlayer insulating film, peeling of the aluminum second wiring in ultrasonic bonding can be prevented. This is because the phosphosilicate glass has good adhesion to both aluminum and polyimide, and the coefficient of thermal expansion of the phosphosilicate glass is SiO containing no phosphorus.
It is considered that this is because the coefficient of thermal expansion is closer to that of polyimide than that of 2 glass.
【００３２】第１の実施例による本発明品と従来品とに
ついて超音波ボンディングを行い、ボンディング強度試
験を行って比較した結果を表１に示す。強度試験は、ア
ルミニウム線を引っ張る引っ張り試験で５００ｇｆ
（４．９０３Ｎ）以上を合格とした。試験個数は各々５
０個である。また、本発明品はリン珪酸ガラスの第２層
間絶縁膜８の厚さを０．３〜１．２μｍにしている。Table 1 shows the results of comparison between ultrasonic bonding and a bonding strength test performed on the product of the present invention according to the first embodiment and the conventional product. The strength test is a tensile test of 500 gf by pulling an aluminum wire.
(4.903 N) or more was passed. 5 tests each
It is 0. Further, in the product of the present invention, the thickness of the second interlayer insulating film 8 of phosphosilicate glass is set to 0.3 to 1.2 μm.
【００３３】[0033]
【表１】 [Table 1]
【００３４】表１に示されるように、従来品ではボンデ
ィング不良が８３％も発生したのに対して本発明品では
ボンディング不良は０であり、リンを含む珪酸ガラスを
設ける効果が確認された。ボンディング不良がなくなる
ため、図５に示したようなボンディングを行うことがで
き、ソース領域の設計の自由度の向上、ソース・パッド
が不要になることによるチップ面積の低減、電流集中の
緩和が実現できる。第１の実施例では第２層間絶縁膜と
してリン珪酸ガラスを用いたが、ホウリン珪酸ガラスを
全く同等に用いることができる。また、製造工程も第１
の実施例に限定されず、少し変更しても本発明の半導体
装置を製造することができる。次に、これを説明する。As shown in Table 1, in the conventional product, 83% of the defective bonding occurred, whereas in the product of the present invention, the defective bonding was 0, and the effect of providing the silicate glass containing phosphorus was confirmed. Since the bonding failure is eliminated, the bonding as shown in FIG. 5 can be performed, the degree of freedom in designing the source region is improved, the chip area is reduced by eliminating the source pad, and the current concentration is reduced. it can. Although phosphosilicate glass is used as the second interlayer insulating film in the first embodiment, borophosphosilicate glass can be used in the same manner. Also, the manufacturing process is the first
However, the semiconductor device of the present invention can be manufactured with a slight modification. Next, this will be described.
【００３５】図２は本発明の半導体装置の第２の実施例
の製造方法を説明するための工程順に示した断面図であ
る。2A to 2D are cross-sectional views showing a sequence of steps for explaining a method of manufacturing a semiconductor device according to a second embodiment of the present invention.
【００３６】図２（ａ）に示すように、シリコン基板１
に能動素子領域としてゲート領域２、ソース領域３を熱
拡散またはイオン注入法で形成する。マスク１１を設
け，アルミニウムでゲート領域２に接続する第１配線４
を形成する。そして、マスク１１を除去する。As shown in FIG. 2A, the silicon substrate 1
A gate region 2 and a source region 3 are formed as active element regions by thermal diffusion or ion implantation. First wiring 4 provided with mask 11 and connected to gate region 2 with aluminum
To form. Then, the mask 11 is removed.
【００３７】次に、図２（ｂ）に示すように、新しくマ
スク（図示せず）を用いてポリイミドで第１層間絶縁膜
５を形成して第１配線４を覆って絶縁し、ソース領域３
の上を開口してコンタクト窓１３をあける。そして、マ
スクを除去する。Next, as shown in FIG. 2B, a new mask (not shown) is used to form a first interlayer insulating film 5 of polyimide to cover and insulate the first wiring 4 and to form a source region. Three
To open the contact window 13. Then, the mask is removed.
【００３８】次に、図２（ｃ）に示すように、第２層間
絶縁膜としてホウリン珪酸ガラス膜９を全面に被着す
る。そして、ホトリソグラフィ技術を用いてソース領域
３の上を開口してコンタクト用窓１４をあける。ホウリ
ン珪酸ガラス膜９もまた、リン珪酸ガラスと同様に、ポ
リイミドの熱分解温度（約４００℃）以下の低温で形成
する。Next, as shown in FIG. 2C, a borophosphosilicate glass film 9 is deposited on the entire surface as a second interlayer insulating film. Then, the contact window 14 is opened by opening the source region 3 by using the photolithography technique. The borophosphosilicate glass film 9 is also formed at a low temperature equal to or lower than the thermal decomposition temperature of polyimide (about 400 ° C.), like the phosphosilicate glass.
【００３９】次に、図２（ｄ）に示すように、アルミニ
ウムでソース領域３に接続する第２配線６を形成する。Next, as shown in FIG. 2D, a second wiring 6 connected to the source region 3 is formed of aluminum.
【００４０】次に、図２（ｅ）に示すように、超音波ボ
ンディング法でアルミニウム線７を第２配線６に接続す
る。Next, as shown in FIG. 2E, the aluminum wire 7 is connected to the second wiring 6 by the ultrasonic bonding method.
【００４１】ホウリン珪酸ガラスを用いても、リン珪酸
ガラスと同様に、アルミニウム線の超音波ボンディング
におけるアルミニウムの第２配線の剥がれを防止するす
ることができる。第１および第２の実施例から、珪酸ガ
ラス（ＳｉＯ2 ）にリンを含ませることによりアルミニ
ウムとポリイミドの両方に密着性が良くなること、リン
を含む珪酸ガラスの熱膨張率がリンを含まないＳｉＯ2
ガラスよりもポリイミドの熱膨張率に近いことによるも
のと考えられる。Even if borophosphosilicate glass is used, peeling of the aluminum second wiring in ultrasonic bonding of an aluminum wire can be prevented as in the case of phosphosilicate glass. According to the first and second examples, the inclusion of phosphorus in silicate glass (SiO 2 ) improves the adhesion to both aluminum and polyimide, and the coefficient of thermal expansion of phosphorus-containing silicate glass does not include phosphorus. SiO 2
It is considered that this is because the coefficient of thermal expansion is closer to that of polyimide than that of glass.
【００４２】発明者は、第２層間絶縁膜としてＳｉＯ2
膜、Ｓｉ3 Ｎ4 膜を用いた実験を行い、ボンディング強
度試験を行った所、ボンディング強度不良は０であっ
た。しかしながら、成膜後のＳｉＯ2 膜には大きなクラ
ックが発生し、Ｓｉ3 Ｎ4 膜には多数の小さいクラック
が発生した。これは、ＳｉＯ2 膜とＳｉ3 Ｎ4 膜の熱膨
張率がポリイミドの熱膨張率よりもかなり小さいことに
起因すると考えられる。リンを添加することにより珪酸
ガラスは熱膨張率がポリイミドのそれに近くなり、クラ
ックを防止すると考えられる。The inventor has used SiO 2 as the second interlayer insulating film.
An experiment using a film and a Si 3 N 4 film was conducted and a bonding strength test was conducted. As a result, the bonding strength defect was 0. However, large cracks occurred in the formed SiO 2 film, and many small cracks occurred in the Si 3 N 4 film. It is considered that this is because the thermal expansion coefficient of the SiO 2 film and the Si 3 N 4 film is considerably smaller than that of polyimide. It is considered that the addition of phosphorus makes the silicate glass have a thermal expansion coefficient close to that of polyimide and prevents cracking.
【００４３】アルミニウムの第２配線とポリイミドの第
１層間絶縁膜との間にリンを含む珪酸ガラスを設けるこ
とによりアルミニウムの剥がれを防止するすることがで
き、歩留り低下とコスト高を防ぐことができ、信頼性を
向上させることができる。また、ボンディング不良をな
くすことができるため、図１（ａ）あるいは図５（ａ）
に示したようなボンディングを行うことができ、ソース
領域の設計の自由度の向上、ソース・ボンディング・パ
ッドの削除によるチップ面積の低減、電流集中の緩和が
実現できる。By providing a silicate glass containing phosphorus between the second wiring made of aluminum and the first interlayer insulating film made of polyimide, it is possible to prevent the aluminum from peeling off, and to prevent a decrease in yield and a high cost. , Reliability can be improved. In addition, since the defective bonding can be eliminated, the structure shown in FIG.
It is possible to carry out the bonding as shown in, and to improve the degree of freedom in designing the source region, reduce the chip area by eliminating the source bonding pad, and alleviate the current concentration.
【００４４】[0044]
【発明の効果】以上説明したように、本発明では、リン
を含む珪酸ガラスをアルミニウムの第２配線とポリイミ
ドの第１層間絶縁膜との間に設けたので、アルミニウム
線の超音波ボンディングにおけるアルミニウムの第２配
線とポリイミドの第１層間絶縁膜との間に剥がれを防止
するすることができ、歩留り低下とコスト高を防ぎ、信
頼性を向上させることができる。As described above, according to the present invention, since the silicate glass containing phosphorus is provided between the second wiring made of aluminum and the first interlayer insulating film made of polyimide, aluminum in ultrasonic bonding of aluminum wires is performed. It is possible to prevent peeling between the second wiring and the first interlayer insulating film of polyimide, prevent a decrease in yield and cost, and improve reliability.
【００４５】また、ボンディング不良がなくなるため、
ソース・ボンディング・パッドを別に設ける必要がなく
なり、これによりチップ面積を低減し、電流集中を緩和
することができ、さらに、設計の自由度を確保すること
ができる。Further, since there is no defective bonding,
Since it is not necessary to separately provide a source bonding pad, the chip area can be reduced, current concentration can be relaxed, and the degree of freedom in design can be secured.
【図１】本発明の半導体装置の第１の実施例の製造方法
を説明するための工程順に示した断面図である。1A to 1D are cross-sectional views showing a method of manufacturing a semiconductor device according to a first embodiment of the present invention in the order of steps.
【図２】本発明の半導体装置の第２の実施例の製造方法
を説明するための工程順に示した断面図である。2A to 2D are sectional views showing the manufacturing method of the second embodiment of the semiconductor device of the present invention in the order of steps for explaining the manufacturing method.
【図３】従来の半導体装置の一例の平面図および断面図
である。FIG. 3 is a plan view and a cross-sectional view of an example of a conventional semiconductor device.
【図４】図３に示す半導体装置の製造方法を説明するた
めの工程順に示した断面図である。4A to 4C are cross-sectional views showing the method of manufacturing the semiconductor device shown in FIG.
【図５】従来の半導体装置の他の例の平面図である。FIG. 5 is a plan view of another example of the conventional semiconductor device.
【図６】従来の半導体装置のボンディング不良の例を説
明する断面図である。FIG. 6 is a cross-sectional view illustrating an example of defective bonding of a conventional semiconductor device.
１ 半導体基板 ２ ゲート領域 ３ ソース領域 ４ 第１配線 ５ 第１層間絶縁膜 ６ 第２配線 ７ アルミニウム線 ８ 第２層間絶縁膜 ９ ホウリン珪酸ガラス膜 １１ マスク 1 semiconductor substrate 2 gate region 3 source region 4 first wiring 5 first interlayer insulating film 6 second wiring 7 aluminum wire 8 second interlayer insulating film 9 borophosphosilicate glass film 11 mask
Claims (4)
板上に複数層の配線層の各々が合成樹脂系の第１層間絶
縁膜で絶縁されて形成されている多層配線構造を有する
半導体装置において、 前記第１層間絶縁膜がポリイミドからなり、少なくとも
最上層の前記第１層間絶縁膜とその上の配線層との間に
リンを含むガラスの第２層間絶縁膜を設けたことを特徴
とする半導体装置。1. A semiconductor device having a multi-layer wiring structure in which each of a plurality of wiring layers is formed on a semiconductor substrate provided with an active element region by being insulated by a synthetic resin-based first interlayer insulating film. The first interlayer insulating film is made of polyimide, and a glass second interlayer insulating film containing phosphorus is provided between at least the uppermost first interlayer insulating film and a wiring layer thereabove. Semiconductor device.
熱分解させない低温度で形成されるリンを含むガラスか
らなることを特徴とする請求項１記載の半導体装置。2. The semiconductor device according to claim 1, wherein the second interlayer insulating film is made of glass containing phosphorus which is formed at a low temperature so as not to thermally decompose the polyimide.
らなることを特徴とする請求項１記載の半導体装置。3. The semiconductor device according to claim 1, wherein the second interlayer insulating film is made of phosphosilicate glass.
スからなることを特徴とする請求項１記載の半導体装
置。4. The semiconductor device according to claim 1, wherein the second interlayer insulating film is made of borophosphosilicate glass.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP6294263A JPH08153719A (en) | 1994-11-29 | 1994-11-29 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP6294263A JPH08153719A (en) | 1994-11-29 | 1994-11-29 | Semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH08153719A true JPH08153719A (en) | 1996-06-11 |
Family
ID=17805457
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP6294263A Pending JPH08153719A (en) | 1994-11-29 | 1994-11-29 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH08153719A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2003124479A (en) * | 2001-10-18 | 2003-04-25 | Mitsubishi Electric Corp | Semiconductor device and its manufacturing method |
| JP2018206938A (en) * | 2017-06-05 | 2018-12-27 | ルネサスエレクトロニクス株式会社 | Semiconductor device and manufacturing method of the same |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5617041A (en) * | 1979-07-20 | 1981-02-18 | Toshiba Corp | Manufacture of semiconductor device |
| JPS61187346A (en) * | 1985-02-15 | 1986-08-21 | Hitachi Ltd | Semiconductor device |
| JPH01103867A (en) * | 1987-10-16 | 1989-04-20 | Sanyo Electric Co Ltd | Transistor |
| JPH06310610A (en) * | 1993-04-27 | 1994-11-04 | Canon Inc | Semiconductor device and its manufacture |
-
1994
- 1994-11-29 JP JP6294263A patent/JPH08153719A/en active Pending
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5617041A (en) * | 1979-07-20 | 1981-02-18 | Toshiba Corp | Manufacture of semiconductor device |
| JPS61187346A (en) * | 1985-02-15 | 1986-08-21 | Hitachi Ltd | Semiconductor device |
| JPH01103867A (en) * | 1987-10-16 | 1989-04-20 | Sanyo Electric Co Ltd | Transistor |
| JPH06310610A (en) * | 1993-04-27 | 1994-11-04 | Canon Inc | Semiconductor device and its manufacture |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2003124479A (en) * | 2001-10-18 | 2003-04-25 | Mitsubishi Electric Corp | Semiconductor device and its manufacturing method |
| JP2018206938A (en) * | 2017-06-05 | 2018-12-27 | ルネサスエレクトロニクス株式会社 | Semiconductor device and manufacturing method of the same |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US4970574A (en) | Electromigrationproof structure for multilayer wiring on a semiconductor device | |
| TWI397972B (en) | Semiconductor device manufacturing method | |
| US6028347A (en) | Semiconductor structures and packaging methods | |
| TW200428500A (en) | Semiconductor device and semiconductor device manufacturing method | |
| JP2001358169A (en) | Semiconductor device | |
| JPH08153719A (en) | Semiconductor device | |
| WO1987002828A1 (en) | Glass intermetal dielectric | |
| JPH0714028B2 (en) | Method for manufacturing three-dimensional semiconductor device | |
| JPH0680794B2 (en) | Method for manufacturing semiconductor integrated circuit device | |
| JPH04731A (en) | Semiconductor device and manufacture thereof | |
| JPH03112135A (en) | Semiconductor device and manufacture thereof | |
| JPH0629294A (en) | Manufacture of semiconductor device | |
| JPS63308924A (en) | Semiconductor device | |
| JP2001168282A (en) | Semiconductor integrated circuit and its manufacture method | |
| JPH0621061A (en) | Semiconductor device | |
| JPH0198253A (en) | Manufacture of solid type semiconductor device | |
| JPS62245641A (en) | Structure of pad part of semiconductor device | |
| JPS63269549A (en) | Manufacture of semiconductor integrated circuit | |
| JPH0583180B2 (en) | ||
| JP2000232100A (en) | Semiconductor device and its manufacture | |
| JPH0653270A (en) | Semiconductor device | |
| JPH0456239A (en) | Semiconductor device | |
| JPS6037150A (en) | Manufacture of semiconductor device | |
| JPS63252445A (en) | Manufacture of semiconductor device | |
| JPH0817824A (en) | Semiconductor device and its manufacture |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| A02 | Decision of refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A02 Effective date: 20010904 |