JPH0790675A - Production of electronic parts - Google Patents

Abstract

PURPOSE:To form dense plating films by setting the lower limit current value at the time of pulse-off of a pulse power source at a current value of specific % of the set current value at the time of pulse-on. CONSTITUTION:Conductive films are formed on the outside surfaces of electronic part elements in order to produce the electronic parts. The plating films are then formed by electroplating using the pulse power source on the conductive films. The lower limit current value at the time of pulse-off of the pulse power source is set at the current value of 10 to 90% of the set current value at the time of pulse=on. Excessive currents flow and the abnormal growth of the plating films takes place at the rise of pulse-on when the lower limit current value of the pulse is' 10% of the set current value. The dense property of the plating films degrade when the lower limit current value exceeds 90%. As a result, the reliability in soldering, etc., is improved.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing an electronic component, and more particularly, to forming a conductive film on the outer surface of an electronic component element and plating the conductive film by electroplating using a pulse power source. The present invention relates to a method of manufacturing an electronic component that forms a film.

[0002]

2. Description of the Related Art In a manufacturing process of electronic parts, a plating film may be formed by electroplating on a conductive film formed on an outer surface of an electronic part element. For example, a plating film is formed on a conductive film in a manufacturing process of an external electrode of a chip type multilayer ceramic capacitor.

FIG. 2 is an enlarged sectional view showing the external electrodes of such a chip type monolithic ceramic capacitor. As shown in FIG. 2, internal electrodes 2 and internal electrodes 3 are alternately formed in the ceramic element 1. The internal electrodes 2 extend to one end of the ceramic element,
Extends to the other end of the ceramic element 1 not shown. An external electrode 4 electrically connected to the internal electrode 2 is formed at one end of the ceramic element 1. External electrode 4
First, a conductive film 4a is first formed on the outer surface of one end of the ceramic element 1, a first plating film 4b is formed on the conductive film 4a by electroplating, and a second plating film 4c is further formed. It is configured by Generally, as the conductive film 4a, a film of Ag or Ag-Pd is formed as a material having excellent conductivity, a Ni film or the like is formed as the first plating film 4b, and Sn or Sn / is formed as the second plating film 4c. A Pb film or the like is formed.

Such a plating film is usually formed by using a DC power supply, but in order to improve the denseness of the plating film, pulse plating is generally performed by using a pulse power supply.

[0005]

The current in such a pulse power supply is made to flow in a state in which pulse-on and pulse-off are repeated as shown in FIG. 3, and is a state of 0 A in which no current flows in the pulse-off state.

FIG. 4 is an enlarged view showing a current change in a pulse portion surrounded by a one-dot chain line in FIG. As shown in FIG. 4, when the pulse is turned on, an excess current larger than the set value flows. Therefore, there is a problem that the plating film grows abnormally.

Again referring to FIG. 2, for this reason, the first plating film 4b and the second plating film 4c are replaced by the conductive film 4a.
Grows inwardly by a distance L from the end portion, and thereby stray capacitance and the like fluctuate. Therefore, there arises a problem that the reliability of the product is lowered.

An object of the present invention is to solve the above conventional problems and to manufacture an electronic component capable of stably forming a dense plating film without causing abnormal growth in the formation of the plating film. To provide a method.

[0009]

The manufacturing method of the present invention comprises a step of forming a conductive film on the outer surface of an electronic component element, and a step of forming a plating film on the conductive film by electroplating using a pulse power source. And the lower limit current value at the time of pulse off of the pulse power supply is set to 10 to 9 of the set current value at the time of pulse on.
The feature is that the current value is set to 0%.

[0010]

In the present invention, the lower limit current value when the pulse of the pulse power supply is turned off is 10 to 90% of the set current value when the pulse is turned on.
The current value is set to. FIG. 1 is a diagram showing changes in pulse current in the present invention. As shown in FIG.
According to the present invention, the lower limit current value of the pulse is set within the range of 90% to 10% of the set current value. If the lower limit current value of the pulse is less than 10% of the set current value, excessive current will flow at the rise of pulse ON, as in the conventional case.
It causes abnormal growth of the plating film. When the lower limit current value of the pulse exceeds 90%, the effect of using the pulse power source is reduced and the denseness of the plating film is reduced.

[0011]

EXAMPLE As shown in FIG. 2, in the external electrode of the chip type monolithic ceramic capacitor, the second electrode was formed on the Ni plating film.
An example in which a Sn plating film is formed as the plating film will be described.

First, in order to confirm that the denseness of the plating film is improved by pulse plating, Sn plating was performed using a DC power supply and a pulse power supply. DC plating is 1
0A DC power supply is used, and pulse plating has a set current value of 10
A, a lower limit current value at pulse-off 0A, a pulse-off interval of 1 msec, and a pulse-on interval of 1 msec were plated with Sn to form external electrodes on the chip-type multilayer ceramic capacitor. The chip type monolithic ceramic capacitor thus obtained was subjected to high temperature and high humidity conditions (100 ° C., 95% RH).
After being left for 4 hours in the above), it was dried and soldered to perform a solderability test. The solderability was evaluated by evaluating the area where the solder was attached. H as the type of solder
It was soldered at 230 ° C. using 60A. Rosin 25% IPA was used as the flux. The number of samples was 20 and the solder adhesion area of each was evaluated.
It was shown to.

[0013]

[Table 1]

As is clear from the results in Table 1, the solder adhesion area of the plating film formed by pulse plating is significantly higher than that by direct current plating, and it can be seen that the denseness of the plating film is improved.

Next, Sn plating was performed on the external electrodes of the chip type multilayer ceramic capacitor by changing the lower limit current value at the time of palph off. The pulse lower limit current value was changed within the range of 0 A to 10 A as shown in Table 2. Regarding the formed plating film, the width of abnormal growth of plating, that is, the width of L shown in FIG. 2 was measured and shown in Table 2 as the plating growth width.

The chip-type monolithic ceramic capacitor obtained was also subjected to high temperature and high humidity conditions (100 ° C. 95%).
After standing for 4 hours at RH or more), this was dried and a solderability test was conducted. The solderability was measured by measuring the solder adhesion area in the same manner as above. That is, the measurement was performed by measuring the area of the portion covered with solder. The number of samples was 20. The obtained results are shown in Table 2.

[0017]

[Table 2]

As is apparent from Table 2, the set current value 10
By setting the pulse lower limit current value to 10% of A, that is, 1 A, it can be seen that the plating growth width sharply decreases. Further, it can be seen that when the pulse lower limit current value is set to exceed 9A, which is 90% of the set current value 10A, the solder adhesion area sharply decreases.

Therefore, according to the present invention, by setting the lower limit current value within the range of 10 to 90% of the set current value, abnormal growth of the plating film is suppressed and a dense plating film is formed. be able to.

In the above embodiments, the chip type multilayer ceramic capacitor was described as an example of the electronic component, and the plating film formed on the external electrode was described as an example of the plating film formed on the conductive film. The present invention is not limited to these, and may be applied to ceramic parts other than capacitors and electronic parts other than ceramic parts. Furthermore, a plating film is formed by electroplating on a conductive film in a part other than external electrodes. It also applies in some cases.

Further, although the Sn plating film formed on the Ni plating film is exemplified in the above-mentioned embodiment, the present invention is also applied when forming the Ni plating film which is a base film of the Sn plating film. Good.

[0022]

According to the present invention, by setting the lower limit current value of the pulse power of the pulse power supply when forming the plating film on the conductive film to a current value of 10 to 90% of the current value of the palph on, the plating film is formed. It is possible to form a dense plating film without causing abnormal growth of. Therefore, for example, reliability can be improved in soldering or the like.

[Brief description of drawings]

FIG. 1 is a diagram showing a change in current of a pulse power supply during pulse plating in the manufacturing method according to the present invention.

FIG. 2 is a cross-sectional view showing the vicinity of external electrodes of a chip type multilayer ceramic capacitor.

FIG. 3 is a diagram showing a change in current of a pulse power supply in conventional pulse plating.

FIG. 4 is an enlarged view showing a pulse portion surrounded by an alternate long and short dash line in FIG.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 ... Ceramic element 2,3 Internal electrode 4 ... External electrode 4a ... Base conductive film of external electrode 4b ... 1st plating film 4c ... 2nd plating film

Claims (1)

[Claims] 1. A step of forming a conductive film on an outer surface of an electronic component element, and a step of forming a plating film on the conductive film by electroplating using a pulse power source, wherein pulse off of the pulse power source is performed. A method of manufacturing an electronic component, wherein the lower limit current value at that time is set to a current value which is 10 to 90% of a set current value at the time of pulse-on.