JPH07202702A - D/a conversion circuit - Google Patents

Abstract

PURPOSE:To obtain a highly precision D/A conversion circuit in which the response and the stability are established in a compatible way. CONSTITUTION:A pulse signal generating circuit 21 generates a PWM signal proportional to a received digital value for a prescribed period. When a pulse of the PWM signal is received at a charging input terminal, a 1st peak hold circuit 22 is charged by said PWM signal as a power supply and holds a peak level of the charged voltage and discharged when a succeeding pulse is given to a discharge input terminal. The charging, peak holding and discharging are repeated alternately. A 2nd peak hold circuit 23 repeats alternately the charging, peak holding, discharging of the PWM signal alternately but implements the process in a reverse timing to that of the 1st peak hold circuit 22. A switch circuit 24 selects a holding output voltage of the 1st peak hold circuit 22 and the 2nd peak hold circuit 23 to provide an output of the selected voltage as an analog voltage.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a digital-analog conversion circuit, and more particularly, it relates to a digital-analog conversion circuit capable of achieving both responsiveness and stability.

[0002]

2. Description of the Related Art FIG. 7 is a block diagram showing an example of a conventional digital-analog conversion circuit. The digital-analog conversion circuit 50 uses the PWM circuit 21 to generate a pulse signal having a constant cycle, a constant amplitude, and a pulse width according to the input digital value, and the pulse signal is generated by the LPF circuit 52. The output voltage is smoothed and output as an analog voltage.

[0003]

In the above conventional digital-analog conversion circuit 50, it is difficult to set the time constant of the LPF circuit 52, and it is difficult to achieve both responsiveness and stability. That is, if the time constant of the LPF circuit 52 with respect to the period τ of the pulse signal is reduced, the response is improved, but as shown in FIG.
Causes the analog voltage to fluctuate. On the other hand, when the time constant of the LPF circuit 52 with respect to the period τ of the pulse signal is increased, the stability is improved, but the responsiveness of the analog voltage is deteriorated as shown by the solid line in FIG. Show good cases). Therefore, an object of the present invention is to provide a digital-analog conversion circuit that can achieve both responsiveness and stability.

[0004]

DISCLOSURE OF THE INVENTION Digital of the Invention
The analog conversion circuit includes a pulse signal generation circuit that generates a pulse signal having an amplitude-time product corresponding to an input digital value for each predetermined period, and charging, peak hold, and discharge of the pulse signal for each predetermined period. And a second peak-and-hold circuit for alternately repeating charging and discharging of the pulse signal at a timing opposite to the charging and discharging timing of the first peak-and-hold circuit. A peak hold circuit; and a switch circuit that alternately selects the held output voltage of the first peak hold circuit and the output voltage of the second peak hold circuit to output an analog voltage. What is done is a structural feature.

In the above structure, the pulse signal generating circuit is a time division type D such as a PWM circuit or a PAM circuit.
An A / A converter or an integral type D / A converter can be used.

[0006]

In the digital-analog conversion circuit of the present invention, the pulse signal generation circuit generates the pulse signal of the amplitude-time product according to the input digital value at a predetermined cycle,
Input to the first peak-hold circuit and the second peak-hold circuit. The first peak hold circuit is
When the pulse signal is input, the pulse signal is charged as a power source to perform peak hold of the charging voltage. Then, when a pulse signal is next input, discharge is performed. In this way, the charging and peak-holding of the pulse signal and the discharging thereof are alternately repeated with the input of the pulse signal as a trigger. On the other hand, the second peak-hold circuit also repeats charging and peak-holding of the pulse signal and discharging thereof, triggered by the input of the pulse signal. However, the timing is opposite to that of the first peak hold circuit. Then, the switch circuit selects one of the hold voltage of the first peak hold circuit and the hold voltage of the second peak hold circuit, which is held, and outputs it as an analog voltage.

By reducing the charging time constant of the peak hold circuit with respect to the pulse signal generation period τ, the response is improved. However, due to the reason explained in the prior art, the stability becomes poor with only one peak hold circuit. However, since the two peak hold circuits that operate at opposite timings are used and the held voltage that is held is selected and output, the analog voltage is apparently stable. Therefore, both responsiveness and stability can be achieved.

[0008]

The present invention will be described in more detail with reference to the embodiments shown in the drawings. The present invention is not limited to this. FIG. 1 is a block diagram of an embodiment of a digital-analog conversion circuit of the present invention. The digital-analog conversion circuit 20 includes a pulse signal generation circuit 21 that generates a pulse signal having an amplitude-time product corresponding to an input digital value in a predetermined cycle, and a pulse signal input to a charging input terminal (see FIG. 3). D) is charged as a power source to perform peak hold, and then discharges again when a pulse signal (key in FIG. 3) is input to the discharge input terminal. , A second peak-hold circuit 23 that repeats the charging and peak-holding and discharging at the timing opposite to that of the first peak-holding circuit 22, and a hold of the first peak-holding circuit 22. A switch circuit 24 for selecting the held voltage or the held voltage of the second peak hold circuit 23 and outputting it as an analog voltage; The first peak hold circuit 22, the second peak hold circuit 23 and the switch circuit 24
And a control circuit 25 for controlling the operation of.

FIG. 2 is a detailed circuit example of the digital-analog conversion circuit 20. Pulse signal generation circuit 21
Is constituted by the PWM circuit 21. First peak
The hold circuit 22 includes an AND circuit G1 and a charging resistor R.
1, a diode D1, a capacitor C1, and a discharging transistor T1. The second peak hold circuit 23 includes an AND circuit G2 and a charging resistor R2.
, A diode D2, a capacitor C2, and a discharging transistor T2. Switch circuit 24
Is composed of two analog switches AS1 and AS2. The control circuit 25 has two flip-flops 25.
1, 256, two NOT circuits 252, 255, and 2
It is composed of two AND circuits 253 and 254.

Next, the operation of the digital-analog conversion circuit 20 will be described. First, the pulse signal generation circuit 21
Generates a pulse signal PWM having a constant period τ, a constant amplitude A, and a pulse width W according to the input digital value, as shown in FIG. The flip-flop 251 is connected so as to invert the output according to the clock signal and receives the pulse signal PWM as the clock signal. Therefore, as shown in (a) and (c) of FIG.
The signals 1Q and not1Q are output.

The pulse signal PWM and the FF signal 1Q are input to the AND circuit G1. Therefore, the AND circuit G
As shown in FIG. 3D, 1 outputs a pulse every other pulse of the pulse signal PWM. This pulse charges the capacitor C1 via the resistor R1 and the diode D1. AN
The D circuit G2 has a pulse signal PWM and an FF signal not.
1Q is input. Therefore, the AND circuit G2 outputs a pulse every other pulse of the pulse signal PWM, as shown in FIG. This pulse has an opposite phase to that in FIG.
Then, this pulse charges the capacitor C2 via the resistor R2 and the diode D2.

The NOT circuit 252, as shown in FIG. 3F, has an inverted pulse signal notP obtained by inverting the pulse signal PWM.
Output WM.

The AND circuit 253 has an inverted pulse signal n.
The otPWM and the FF signal not1Q are input. Therefore, the AND circuit 253, as shown in FIG.
3 is output from the rising edge of the pulse in FIG. 3 to the falling edge of the pulse in FIG. 3E, and the H pulse is output from the falling edge of the pulse in FIG. 3E to the rising edge of the pulse in FIG. When this pulse is L, the discharge transistor T1 is turned off,
When it is H, the discharging transistor T1 is turned on. Therefore, the discharging transistor T1 is off from the start of charging the capacitor C1 to the end of charging the capacitor C2. Further, it is on from the end of charging the capacitor C2 to the start of charging the capacitor C1, and the capacitor C1 is discharged during this period. Therefore, the voltage V of the capacitor C1
1 changes as shown in FIG.

The AND circuit 254 has an inverted pulse signal n
The otPWM and the FF signal 1Q are input. Therefore,
As shown in FIG. 3C, the AND circuit 254 is H from the fall of the pulse of FIG. 3E to the rise of the pulse of E of FIG. 3, and from the rise of the pulse of E of FIG. The L pulse is output until the pulse falls. When this pulse is H, the discharging transistor T2 is turned on, and when it is L, the discharging transistor T2 is turned off. Therefore, the discharging transistor T2 is off from the start of charging the capacitor C2 to the end of charging the capacitor C1. Further, it is on from the end of charging the capacitor C1 to the start of charging the capacitor C2, and the capacitor C2 is in the meantime.
To discharge. Therefore, the voltage V2 of the capacitor C2 is
It changes as shown in FIG.

The NOT circuit 255 outputs a pulse obtained by inverting the pulse indicated by X in FIG. 3, as shown in FIG.

Since the flip-flop 256 is connected so that it is cleared by the L of the pulse shown in FIG. 3 and becomes H by the rise of the pulse of K shown in FIG. 3, as shown in FIGS. , FF signals 2Q and not2Q are output. The analog switch AS1 is turned on when the FF signal 2Q is H, and turned off when the FF signal 2Q is L. The analog switch AS2 is turned on when the FF signal not2Q is H, and L
It turns off when. Therefore, the output analog voltage is the voltage V1, V2 as shown by the thick line in FIG.
The held voltage becomes the selected voltage signal.

The above digital-analog conversion circuit 20
According to, according to
Time constants of the hold circuits 22 and 23 (R1 * C1, R2 *
Good response can be obtained by reducing C2), and good stability can be obtained because the stable one of the voltages V1 and V2 is selected and output. That is, as shown in FIG.
The analog voltage does not fluctuate in the cycle τ of the pulse signal, and as shown in FIG. 6, the responsiveness of the output analog voltage improves even when the input digital value changes abruptly.

[0018]

According to the digital-analog conversion circuit of the present invention, both responsiveness and stability can be achieved. Therefore, a highly accurate digital-analog conversion circuit can be obtained.

[Brief description of drawings]

FIG. 1 is a block diagram of an embodiment of a digital-analog conversion circuit of the present invention.

FIG. 2 is a detailed circuit diagram of the digital-analog conversion circuit of FIG.

FIG. 3 is a waveform diagram of each part of the circuit of FIG.

FIG. 4 is an explanatory diagram of a relationship between a hold voltage and an analog voltage.

FIG. 5 is a graph showing a change in analog voltage observed in a short period of about a pulse signal period.

FIG. 6 is a graph showing changes in analog voltage observed during a period sufficiently longer than the period of a pulse signal.

FIG. 7 is a block diagram of an example of a conventional digital-analog conversion circuit.

FIG. 8 is a graph showing a change in analog voltage observed in a short period of about a pulse signal cycle.

FIG. 9 is a graph of changes in analog voltage observed during a period sufficiently longer than the period of a pulse signal.

[Explanation of symbols]

 20 Digital-Analog Converter Circuit 21 Analog Signal Generation Circuit 22 First Peak-Hold Circuit 23 Second Peak-Hold Circuit 24 Switch Circuit 25 Control Circuit

Claims (1)

[Claims] 1. Amplitude according to an input digital value
A pulse signal generation circuit that generates a pulse signal of a time product for each predetermined period, a first peak hold circuit that alternately repeats charging, peak hold, and discharge of the pulse signal for each predetermined period, and a first peak hold circuit for the first peak hold circuit. A second peak and hold circuit which alternately repeats charging and peak holding and discharging of the pulse signal at a timing opposite to the charging and discharging timing of the first peak and hold circuit;
Of the output voltage of the peak-hold circuit and the output voltage of the second peak-hold circuit are alternately selected to output an analog voltage. -Analog conversion circuit.