JPH0661826A - Power MOS control circuit - Google Patents

Abstract

PURPOSE:To prevent occurrence of EMI due to a transient phenomenon and destruction of the control circuit due to kick back by interposing a discharge control MOS transistor(TR) in series between a gate of a power MOSTR and a charge extraction MOSTR. CONSTITUTION:When a gate potential Vc of a power MOSTR MA is decreased by the extraction of a gate charge by a charge extraction MOSTRM1, a current Iout from the TRMA to a load L is decreased and an output voltage Vout is decreased. When the gate potential Vc is too much decreased, a gate-source voltage Vgs is reduced, the quantity of conduction is reduced and an output current lout is decreased. Thus, the output voltage Vout is reduced, the voltage Vgs is again extended, the quantity of conduction is increased, the output current Iout is increased and then the potential Vc is again reduced due to the increase in the quantity of conduction. The output voltage Vout is interrupted through the repetition above. Thus, the output current Iout when the power MOSTRMA is switched from ON to OFF is interrupted while tracing a changing locus where EMI or a transient phenomenon such as kick back is minimized.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a power MOS control circuit, and more particularly to a technique effectively applied to control the switching characteristics of a power MOS transistor, for driving an inductive load such as a motor. The present invention relates to a technology effectively used for a power circuit that operates.

[0002]

2. Description of the Related Art In recent years, a power MOS transistor has come to be widely used as a power element for switching and driving an inductive load such as a motor (for example, CQ Publishing Co., Ltd., September 10, 1982, "Practical Use"). Electronic Circuit Handbook 5 "pp. 234-236).

FIG. 8 shows an example of a power circuit using a power MOS transistor MA. The power circuit is composed of a power MOS transistor MA, a drive circuit 1 and a power MOS controller 2.

The power MOS transistor MA has a power source V
The power supply to the load L is ON / OFF controlled by being interposed in series between the DD and the load L.

The drive circuit 1 has a booster circuit (charge pump circuit) 11 and a logic circuit 12, and has a logic control signal Vin, which is externally applied, of high ("H") and low (").
The power MOS transistor MA is driven on / off according to L ″).

The power MOS control circuit 2 uses the power M
A charge extraction MOS transistor M1 inserted in parallel to the gate of the OS transistor MA, and charging remaining on the gate of the power MOS transistor MA when the power MOS transistor MA is switched from on to off. Discharge the electric charge. Thereby, the gate control voltage V of the power MOS transistor MA
The output current Iout to the load L can be quickly turned off (cut off) by rapidly lowering c.

[0007]

However, the present inventors have clarified that the above-mentioned technique has the following problems.

That is, in the above-described conventional power MOS control circuit, as shown in FIG. 9, the output current Iout is rapidly turned off (cut off) by the power MOS transistor, so that the EMI caused by the transient phenomenon at the time of the off.
(Electromagnetic interference) is likely to occur, and further, when the load is inductive such as a motor, circuit breakdown due to the kickback effect is likely to occur.

SUMMARY OF THE INVENTION An object of the present invention is to provide a technique for appropriately controlling the energization of a load by a power MOS transistor and preventing the generation of EMI due to a transient phenomenon and the destruction of a circuit due to kickback. .

The above and other objects and characteristics of the present invention will be apparent from the description of this specification and the accompanying drawings.

[0011]

Among the inventions disclosed in the present application, a brief description will be given to the outline of typical ones.
It is as follows.

That is, a charge extraction MOS transistor is inserted in parallel to the gate of the power MOS transistor, and the power M is inserted between the gate of the power MOS transistor and the charge extraction MOS transistor.
A discharge control MOS transistor whose conduction is automatically controlled by a voltage between the gate of the OS transistor and the output electrode is interposed in series.

[0013]

According to the above-mentioned means, the residual gate charge after the power MOS transistor is controlled to be switched from ON to OFF can be smoothly discharged under the control such that the output current does not change suddenly.

Thus, the object of properly controlling the energization of the load by the power MOS transistor and preventing the occurrence of EMI due to a transient phenomenon and the destruction of the circuit due to kickback is achieved.

[0015]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT A preferred embodiment of the present invention will be described below with reference to the drawings.

In the drawings, the same reference numerals indicate the same or corresponding parts.

FIG. 1 shows a power M to which the technique of the present invention is applied.
1 shows an embodiment of an OS control circuit, in which MA is a power MOS transistor interposed between a power supply VDD and a load L to turn on / off power supply to the load L, and 1 is a logic control given from the outside. The power MOS transistor MA depending on whether the signal Vin is high (“H”) or low (“L”).
Drive circuit for turning on / off the transistor, 2 is the power MOS
It is a power MOS control circuit that controls the switching characteristics when the transistor MA shifts from on to off.

The drive circuit 1 has a booster circuit (charge pump circuit) 11 and a logic circuit 12 and the like, and turns on / off the power MOS transistor MA in response to high and low of a logic control signal Vin applied from the outside. To do.

The power MOS control circuit 2 is a power MOS
A charge extraction MOS transistor M1 is inserted in parallel to the gate of the transistor MA, and the power MOS
The power MOS transistor M is provided between the gate of the transistor MA and the charge extraction MOS transistor M1.
A voltage Vgs (= between the gate and source (output electrode) of A)
Vc-Vout) is used to interpose in series a discharge control MOS transistor M2 whose conduction is automatically controlled.

In this case, the power MOS transistor MA
The n-channel type is used for the charge extraction MOS transistor M1, and the p-channel type MOS transistor M2 is used for the discharge control MOS transistor M2.

The conduction of the discharge control p-channel MOS transistor M2 is automatically controlled by the gate-source voltage Vgs of the power MOS transistor MA.
Specifically, the gate of the power MOS transistor MA
The conduction amount is small while the source voltage Vgs is small, and is automatically controlled so that the conduction amount increases as the gate-source voltage Vgs increases.

Next, the operation will be described.

In FIG. 1, first, when the external logic control signal Vin is high, the drive circuit 1 outputs power M.
The gate voltage Vc of the OS transistor MA is driven to a high level, whereby the power MOS transistor MA is turned on and the output current Iout flows through the load L.

Next, when the logic control signal Vin from the outside is switched from high to low, the power M by the drive circuit 1 is changed.
The gate drive of the OS transistor MA is stopped, and the charge extraction MOS transistor M1 is turned on by the row of the logic signal Vin, and the power M
The charge that remains in the gate of the OS transistor MA is extracted.

At this time, the gate charge is extracted by the charge extraction MOS transistor M1 by the discharge control MOS.
Since the transistor M2 is interposed in series, the operation is performed as follows.

That is, an external logic control signal Vin
Immediately after switching from high to low, the power MOS
Since the source of the transistor MA is almost at the same potential as the power supply VDD and the gate-source voltage Vgs is small, the conduction amount of the discharge control MOS transistor M2 is small. As a result, the charge extraction MOS transistor M1 has the power M
The gate charge of the OS transistor MA is extracted relatively gently.

When the gate potential (Vc) of the power MOS transistor MA decreases due to the extraction of the gate charge by the charge extraction MOS transistor M1, this reduces the output current Iout flowing from the power MOS transistor MA to the load L and reduces the power. MO
Source potential of S transistor MA, that is, output voltage Vo
ut decreases.

When the gate-source voltage Vgs increases due to the decrease in the output voltage Vout,
The conduction amount of the discharge control MOS transistor M2 increases, and the extraction of the gate charge of the power MOS transistor MA by the charge extraction MOS transistor M1 is accelerated.

When the gate potential Vc is lowered too much by pulling out the gate electrode, the gate-source voltage Vgs is reduced, the conduction amount is reduced, and at the same time, the output current Iout is reduced.
Also decreases. As a result, the output voltage Vout decreases,
The gate-source voltage Vgs expands again, the conduction amount increases, and at the same time, the output current Iout also increases. The gate potential Vc decreases again as the amount of conduction increases. By repeating this, that is, the output voltage Vout can be lowered (turned off) while monitoring the output voltage Vout.

As described above, as shown in FIG. 2, the output current Iout when the power MOS transistor MA is switched from ON to OFF changes with a locus that minimizes transient phenomena such as EMI and kickback. Is cut off while going through. The change state of the output current Iout at this time can be arbitrarily set by the gate width / channel length of the discharge control MOS transistor M2.

As a result, the power MOS transistor M
While properly controlling the energization of the load L by the switching operation of A, it is possible to prevent the occurrence of EMI due to a transient phenomenon and the destruction of the circuit due to kickback. The circuit of FIG. 1 is a so-called high-side driver, but a low-side driver in which the position of the load L is inserted between the power supply VDD and the power transistor MA as shown in FIG.

FIGS. 4, 5 and 6 each show a further preferred embodiment of the present invention.

In the embodiment shown in FIG. 4, the discharge control MO is used.
S transistor M2 and charge extraction MOS transistor M
By inserting the resistor R1 between 1 and 1, the upper limit of the gate charge discharge rate of the power MOS transistor MA is controlled.

In the embodiment shown in FIG. 5, a Zener diode Z1 for clamping a voltage above a certain level is connected from the gate to the source of the power MOS transistor MA. In this case, when Vin is Low, that is, when M1 is ON, the gate potential Vc and the output voltage Vout settle down in a state of being lowered to the ground potential. At this time, however, the output voltage Vout is temporarily reduced to the forward voltage VF of the Zener diode. In the above case, a current flows into the circuit from the output terminal through the Zener diode Z1, but this current can be cut off by the discharge control MOS transistor M2. The positive kickback voltage can be clamped to the power supply VDD by the diode D1 incorporated in the power MOS transistor MA.

In the embodiment shown in FIG. 6, the MOS transistor M3 is connected between the gate and source of the power MOS transistor MA. As a result, there is a difference in the threshold voltage Vth between the power MOS transistor MA and the MOS transistor M2, and even if the MOS transistor M2 is cut off before the power MOS transistor MA, the charge pulling-out MOS transistor M3 can completely remove the power MOS transistor. The gate charge of MA can be extracted. Therefore, the power MOS transistor M
It becomes possible to completely turn off A.

FIG. 7 shows an example of a motor drive circuit to which the technique of the present invention is applied.

The drive circuit shown in the figure has four power MOS transistors MA, MB, M connected in a bridge shape.
It is possible to drive the motor as the load L in the forward and reverse directions by selectively turning on two C and MD by two symmetrical ones.

Although the invention made by the present inventor has been specifically described based on the embodiments, the present invention is not limited to the above embodiments, and various modifications can be made without departing from the scope of the invention. Needless to say.

In the above description, the case of applying the invention made by the present inventor to a motor control circuit using a power MOS, which is the field of application which is the background of the invention, has been mainly described, but the invention is not limited to this. It can also be applied to circuits that require high-current switching.

[0040]

The outline of the typical inventions among the inventions disclosed in the present application will be briefly described as follows.

That is, it is possible to obtain an effect that it is possible to prevent the generation of EMI due to a transient phenomenon and the destruction of the circuit due to kickback while properly controlling the energization of the load by the power MOS transistor.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing a first embodiment of a power MOS control circuit (high side driver) to which the technique of the present invention is applied.

FIG. 2 is an output current control waveform diagram of a power MOS transistor controlled by a power control circuit of the present invention.

FIG. 3 is a circuit diagram used as a low side driver circuit.

FIG. 4 is a circuit diagram showing a main part of a second embodiment of the present invention.

FIG. 5 is a circuit diagram showing a main part of a second embodiment of the present invention.

FIG. 6 is a circuit diagram showing a main part of a third embodiment of the present invention.

FIG. 7 is a circuit diagram showing an outline of a conventional power MOS control circuit.

FIG. 8 is an output current control waveform diagram of a power MOS transistor controlled by a conventional power control circuit.

FIG. 9 is an output waveform diagram of a power MOS transistor controlled by a conventional power control circuit.

[Explanation of symbols]

 1 Drive Circuit 2 Power MOS Control Circuit MA Power MOS Transistor M1 Charge Extraction MOS Transistor M2 Discharge Control MOS Transistor R1 Resistor Z1 Zener Diode VDD Power Supply L Load M3 Charge Extraction MOS Transistor

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Shuichi Horiuchi 15 Asahidai, Moroyama-cho, Iruma-gun, Saitama Prefecture Inside Hitachi Eastern Tobu Semiconductor Co., Ltd.

Claims (1)

[Claims] 1. A charge extraction MOS transistor is inserted in parallel to the gate of the power MOS transistor, and a gate of the power MOS transistor and an output electrode are provided between the gate of the power MOS transistor and the charge extraction MOS transistor. A power MOS control circuit characterized in that a discharge control MOS transistor whose conduction is automatically controlled by a voltage between them is interposed in series.