JPH06119773A - Semiconductor memory - Google Patents

Abstract

PURPOSE:To obtain a high speed and highly integrated memory cell with high reliability by connecting a ferroelectric substance capacitor and a paraelectric substance capacitor in series and impressing a prescribed fixed voltage. CONSTITUTION:This memory is constituted so that the paraelectric substance capacitor CO and the ferroelectric substance capacitor CFE whose insulation film is made from ferroelectric substance are connected in series, and voltage in a connection node VN is detected by a voltage monitor. In information writing operation, the voltage VIS is impressed to a terminal V1, and the transition of two voltage stable points VN0, VN1 occurring in the VN is performed by making the impressed voltage in the V1 VIS to and from V1L, and write is executed. Further, in reading operation, though the voltage in the node VN is detected by the voltage monitor circuit and read is executed, at this time, since inversion in the polarization of the CFE is unnecessitated, the voltage in the V1 is made the fixed voltage inducing no polarization. Thus, delay in read due to the inversion in the polarization is eliminated, and fatigue in the ferroelectric substance film is suppressed, and the voltage is obtained regardless of the area of the capacitor, and high integration is obtained.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a non-volatile semiconductor memory using a ferroelectric substance.

[0002]

2. Description of the Related Art Ferroelectric random access memory (FRAM) using a ferroelectric material has almost the same performance as a conventional dynamic random access memory, but is also non-volatile. FIG. 13 shows F
As an example of the RAM, USP. 4, 873, 664. This memory is M
One bit of information is stored in the memory cell pair of C11 and MCB11. In this memory cell, a ferroelectric material is used as a capacitor insulating film, and the polarization direction of the ferroelectric material represents stored information. To read this stored information, for example, the data line pair BL1 and BLB1 is set to a floating state of 0V, and then the word line WL1 is set to a high potential to set the plate PL1.
To high potential. Then, both BL1 and BLB1 are boosted, but due to the difference in the polarization direction of the ferroelectric substance of the memory cell pair MC11 and MCB11, a difference occurs in the potential between BL1 and BLB1. This is because the difference in polarization direction causes an effective difference in capacitor capacitance. This is amplified by the sense circuit to determine the polarization direction of the capacitor insulating film. Some FRAM configurations other than the example of FIG. 13 have been proposed, but the basic principle for reading information is similar to this.

[0003]

However, the read method utilizing the effective difference in the capacitance of the capacitors as described above has the following problems.

(1) Every time the information in the memory cell is read, the polarization is inverted with a probability of about 1/2. Therefore, the ferroelectric film is rapidly fatigued. This is because the difference in the capacitance of the capacitors occurs depending on whether the polarization is inverted or not when the plate is set to a high potential, and the directions of polarization are always aligned in one direction after reading.

(2) The time required for the polarization reversal delays the time required for the read operation.

(3) In order to obtain a sufficient amount of signals, the area of the ferroelectric capacitor needs to be large to some extent, which becomes a factor to hinder high integration. This is because the effective difference in the capacitance of the capacitors depends on the amount of movement of the charges due to the polarization reversal. Furthermore, the amount of charge (remanent polarization) per unit area of the ferroelectric film is determined by the substance regardless of the film thickness.

The present invention provides a new memory cell structure of an FRAM for solving the above problems (1), (2) and (3).

[0008]

A memory cell having two capacitors (CO, CFE) connected in series, and a voltage applying means for applying a constant voltage across the capacitor column (CO, CFE). , The above two capacitors (C
A detection circuit (voltage monitor circuit) for detecting the voltage of a connection node (VN) of O, CFE) is provided on the semiconductor substrate, and one of the two capacitors is a ferroelectric having a ferroelectric substance sandwiched between capacitor electrodes. The semiconductor memory is composed of a body capacitor (CFE), and the other of the two capacitors is a semiconductor memory composed of a paraelectric capacitor (CO) having a paraelectric material sandwiched between capacitor electrodes.

In order to detect the voltage with higher accuracy, a field effect transistor whose gate is connected to the connection node is used in the detection circuit.

[0010]

When a constant voltage (V1) is applied to both terminals of the memory cell capacitor column (CO, CFE), the connection node (VN) of the two capacitors (CO, CFE) becomes
Two voltage stabilization points (VN
0, VN1). Two voltage stabilization points (VN0, V
The information stored in the memory cell can be detected depending on the state of N1).

[0011]

FIG. 1A is a first embodiment of the present invention showing a cell structure of a ferroelectric memory. A paraelectric capacitor CO having a paraelectric material as an insulating film and a ferroelectric capacitor CFE having a ferroelectric material as an insulating film are connected in series, and a connection node VN between the paraelectric capacitor CO and the ferroelectric capacitor CFE is connected. A voltage monitor circuit for detecting the voltage of the connection node VN is connected. A voltage application means (not shown) for applying a voltage for inducing polarization to the ferroelectric capacitor CFE at the time of writing information is connected to the terminal V1. This voltage applying means applies a constant voltage to the terminal V1 to the extent that polarization is not induced when reading information.

When a voltage V1S is applied to a terminal V1 different from the terminal connected to the connection node VN of the paraelectric capacitor, VN has two voltage stabilization points VN0 and VN1 as shown in FIG. 1 (b). . Here, for simplification, the voltage of the terminal different from the terminal connected to the connection node VN of the ferroelectric capacitor is set to 0V (GND).

To shift from one stable point to the other stable point, a voltage V1L sufficiently lower than the voltage V1S or a voltage V1H sufficiently higher than the voltage V1S may be applied to the V1 terminal. That is, in order to shift the voltage of the connection node VN from VN0 to VN1, the voltage of the V1 terminal may be temporarily lowered from the voltage V1S to V1L and then returned to V1S again. Similarly, the connection node V
To shift the voltage of N from VN1 to VN0,
The voltage of the terminal is raised from the voltage V1S to V1H, and again V1S
Just go back to. As a result, the write operation in the memory cell of the present invention can be performed.

It is preferable that the capacitance of the paraelectric capacitor CO be equal to or greater than that of the ferroelectric capacitor CFE so that the potential of VN follows the voltage change of the V1 terminal sensitively. Therefore, as the insulating film used for CO, it is preferable to use a perovskite oxide such as SrTiO ₃ which exhibits paraelectric properties at room temperature and which has a large dielectric constant comparable to that of a ferroelectric substance. For example, SrTi
With O ₃ , a high dielectric constant of about 200 can be obtained.

The read operation is performed by detecting the voltage of the connection node VN by the voltage monitor circuit shown in FIG. According to this embodiment, it is not necessary to invert the polarization of the ferroelectric capacitor during the read operation of the memory cell, so that fatigue of the ferroelectric film is suppressed and a highly reliable ferroelectric memory can be obtained. Moreover, since the polarization inversion does not occur during the read operation, there is no delay in the read time. further,
The voltages of VN0 and VN1 are almost the same value as the coercive voltage of the ferroelectric film (intercept with VN of the hysteresis curve), but this coercive voltage is almost determined by the substance and film thickness regardless of the capacitor area. To be done. Therefore, a sufficient signal voltage can be secured even if the area of the ferroelectric capacitor is reduced, and a highly integrated ferroelectric memory can be realized. In addition, the voltage V1H required for polarization reversal can be reduced by reducing the film thickness, so that it is easy to reduce the voltage. For example, with PZT, the coercive voltage is about 1 V for a film thickness of 200 nm, and 2 V
A power supply can be used.

FIG. 2 shows a memory cell constructed using the principle of FIG. VWW and VGL are, for example, Vcc
/ 2. The threshold voltage of the field effect transistor TR1 whose gate is connected to the connection node VN is, for example, 0V.
Then, when the connection node VN is at the stable point on the negative voltage side, the field effect transistor TR1 is in the off state, and when it is at the stable point on the positive voltage side, the field effect transistor TR1 is in the on state. Therefore, the word line VWR
Also, in the memory cell selected by the data line VBL orthogonal to this, the stored information can be detected depending on whether or not a current flows between VBL and VGL.

FIG. 3 shows an example of an array formed by using the memory cells shown in FIG. VWW1 to V
WWn and VWWB1 to VWWBn are VWW shown in FIG.
Corresponding to VWR1 to VWRn and VWRB1 to VWR
Bn corresponds to VWR shown in FIG. 2, and VBL1 to VBLm
And VDL1 to VDLm correspond to VBL shown in FIG.
VGL1, VGL2 and VGDL1, VGDL2 are shown in FIG.
Corresponds to VGL shown in FIG.

The write operation is performed by applying a voltage which is orthogonal to each other, for example, between VWW1 and VGL1. The read operation is performed, for example, in the memory cell MC.
11 field effect transistor and its dummy cell DC11
Which of the field effect transistors is ON is converted into a current flowing through the data line VBL1 selected by BS1 and its dummy data line VDL1 and detected. The write operation and the read operation will be further described below with reference to FIGS. 4 and 5.

FIG. 4 is an operation waveform showing a write operation in the array of FIG. Here, the memory cell MC1
1 shows the case of writing information. Write word line VW
W1 is changed from Vcc / 2 to Vcc, and VGL1 is changed to Vcc /
When the value is changed from 2 to 0, the voltage Vcc is applied to the terminals of the paraelectric capacitor and the ferroelectric capacitor connected in series of the memory cell MC11, so that the paraelectric capacitor and the ferroelectric capacitor connected in series are connected. Node VN1
The voltage of 1 is the stable point on the high voltage side.

On the other hand, for the dummy cell DC11 paired with the memory cell MC11, the write word line VW is used.
WB1 is changed from Vcc / 2 to 0, and VGDL1 is changed to Vcc /
When the voltage is changed from 2 to Vcc, the voltage -Vcc is applied to the terminals of the paraelectric capacitor and the ferroelectric capacitor connected in series of the dummy cell DC11, so that the paraelectric capacitor and the ferroelectric capacitor connected in series are connected. The voltage of the node VDN11 becomes a stable point on the low voltage side.

At this time, the same VWW1, VGL1, VWW
A voltage of Vcc / 2 is applied to the terminals of the paraelectric capacitor and the ferroelectric capacitor connected in series to other memory cells connected to B1 and VGDL1, but this voltage is more than V1H which does not destroy the stored information. Use a low voltage. That is, in the hysteresis curve of FIG. 1B, after applying Vcc / 2 to the terminals of the paraelectric capacitor and the ferroelectric capacitor connected in series in the memory cell at the stable point of VN0 or VN1, VWW and VGL are applied. Is returned to Vcc / 2 and the voltage between terminals of the paraelectric capacitor and the ferroelectric capacitor connected in series is set to 0, the voltage is set to return to the stable point of VN0 or VN1 before voltage application.

In order to set the connection node VN of the paraelectric capacitor and the ferroelectric capacitor connected in series of the memory cells to the stable point on the low voltage side, the opposite operation may be performed.

FIG. 5 is an operation waveform showing a read operation in the array of FIG. Here, the memory cell MC1
The case where the information of No. 1 is read is shown. The data line VBL1 and the dummy data line VDL1 are selected by BS1 and a voltage of Vd, for example, is supplied via the N-channel transistors TRN1 and TRN2. Next, the word lines VWR1 and V
Select WRB1. If the transistor TR1 in the memory cell MC11 is in the ON state, the data line VBL1 becomes conductive with VGL1 at the level of Vcc / 2, so that the potential of the data line VBL1 becomes lower than Vd. On the other hand, since the transistor in the dummy cell DC11 is in the off state, the voltage of VDL1 remains Vd. The voltage difference between VBL1 and VDL1 generated in this way is detected and amplified by the voltage amplifier AMP to read information.

The capacitance of the paraelectric capacitor CO in the memory cell is the transistor TR1 having VN as its gate.
The gate capacitance of the transistor TR2
It is necessary to design so that the potential of VN hardly changes even when the transistor TR1 is turned on and the drain voltage of the transistor TR1 is Vd. According to the embodiment of the present invention described with reference to FIGS. 3 to 5, since rewriting of information is unnecessary as compared with the conventional method of detecting the voltage difference caused by the effective difference in the capacitor capacitance, the read speed is increased. There is an effect that can be done. Further, since it is not necessary to set the data line voltage amplitude to the voltage amplitude required for rewriting, data can be transferred to the next stage with a small data line voltage amplitude, and the reading speed is increased.

FIG. 6 shows a second embodiment of the memory cell of the present invention. The memory cell shown in FIG. 6 is different from the memory cell shown in FIG. 2 in that the transistor TR2 is not provided.
Therefore, this memory cell can be highly integrated. Although the ferroelectric capacitor CFE is on the word line VW side in FIG. 6, it may be on the VGL side as in FIG. The write operation is similar to that of the memory cell shown in FIG. However, when VGL and VBL have the same potential,
An unnecessary current is prevented from flowing to the transistor TR1 of the memory cell.

The read operation of the memory cell shown in FIG. 6 will be described with reference to FIG. FIG. 7 is a state diagram showing the relationship between the voltage of the connection node VN of the ferroelectric capacitor CFE and the paraelectric capacitor CO of the memory cell of FIG. 6 and the charge amount Q of the capacitor.

FIG. 7A shows the relationship when the memory cell holds information, and FIG. 7B shows the relationship when the information is read from the memory cell.

The hysteresis curve is the ferroelectric capacitor C
In the state of FE, the straight line shows the state of the paraelectric capacitor CO, and the intersection point becomes the stable point of VN. Normally, the word line VW is set to a negative voltage VWL, the voltage VN is VNL0,
The transistor TR1 of the memory cell is turned off at any stable point of VNL1. That is, both VNL0 and VNL1 are set to be equal to or lower than the threshold voltage Vth of the transistor TR1. At the time of reading, the selected word line VW is set to a positive voltage VWH that does not destroy the stored information, and when the connection node VN is at the stable point (VNH1) on the high voltage side, the transistor T of the memory cell is read.
When R1 is in the on state and is at the stable point (VNL1) on the low voltage side, it is turned off. As a result, the read operation can be performed by the same method as described with reference to FIG.

FIG. 8 shows a device structure of the memory cell shown in FIG. As VGL, for example, a laminated structure of Al and Pt is used. An insulating film HE having a high dielectric constant such as SrTiO ₃ is formed thereon, and a connection node VN is formed using Pt or the like. VN is connected to the gate of a transistor formed of Al or the like. PZ on top of VN
Ferroelectric film FE such as T is formed, and VW is formed on it.
To form. As a result, the paraelectric capacitor CO is formed by VGL, HE and VN, and VN, FE and VW are formed.
This forms a ferroelectric capacitor. When writing information, the potential of VN can easily follow the potential of VW,
The capacitance of the paraelectric capacitor CO is designed to be equal to or greater than the capacitance of the ferroelectric capacitor CFE. Therefore, a perovskite oxide having a high dielectric constant is used as the insulating film of the paraelectric capacitor CO, the capacitor area of the paraelectric capacitor CO is made larger than that of the ferroelectric capacitor CFE, or It is preferable to make the insulating film thickness of the dielectric capacitor CO smaller than that of the ferroelectric capacitor CFE.

FIG. 9 shows another device structure of the memory cell shown in FIG. In this case, the paraelectric capacitor CO and the ferroelectric capacitor CFE are upside down.

FIG. 10 shows a layout of the memory cell shown in FIG.

In the device structure of the memory cell shown in FIG. 9, by making the paraelectric capacitor on the VW side, it becomes easy to design its area larger than that of the ferroelectric capacitor, and at a relatively low voltage. A write operation can be performed.

FIG. 11 shows still another device structure of the memory cell shown in FIG. In the device structure shown in FIG. 11, paraelectric films are formed on the sidewalls of VGL and VN. The area of the paraelectric capacitor can be increased by increasing the thickness of the electrode. Therefore, it is possible to obtain a ferroelectric memory which is highly integrated and can perform a writing operation at a relatively low voltage.

FIG. 12 shows a third embodiment of the memory cell of the present invention. In the memory cell shown in FIG. 12, the paraelectric capacitor in the memory cell of FIG. 6 also serves as the gate capacitance of the transistor. According to this embodiment, an extremely highly integrated ferroelectric memory can be realized.

[0035]

Since it is not necessary to change the voltage value applied across the ferroelectric capacitor when reading information,
Unnecessary inversion of polarization can be avoided, and a ferroelectric memory with less fatigue of the ferroelectric and high speed can be realized.

Further, since the voltage difference between the two stable points depending on the polarization direction of the ferroelectric capacitor does not depend on the area of the ferroelectric capacitor, a sufficient signal voltage can be obtained even if the capacitor area is reduced, and high S / N can realize a highly integrated memory.

[Brief description of drawings]

FIG. 1 is a configuration (a) of a ferroelectric memory cell of the present invention and a state diagram (b) of a storage node VN.

FIG. 2 is a structure of a ferroelectric memory cell of the present invention.

FIG. 3 is an array configuration using the memory cell of FIG.

FIG. 4 is a write operation in the array of FIG.

5 is a read operation in the array of FIG.

FIG. 6 is a structure of a ferroelectric memory cell of the present invention.

FIG. 7 is a state diagram of the storage node VN of FIG.

FIG. 8 is a cross-sectional view of the memory cell of FIG.

9 is a cross-sectional view of a memory cell similar to FIG.

FIG. 10 is a layout of a memory cell similar to that of FIG.

11 is a cross-sectional view of the memory cell of FIG.

FIG. 12 is a structure of a ferroelectric memory cell of the present invention.

FIG. 13 is an array configuration of a conventional ferroelectric memory.

[Explanation of symbols]

VN ... Information storage node, V1 ... Information writing terminal, CO
… Paraelectric capacitors, CFE… Ferroelectric capacitors,
VN0, VN1 ... Voltage stable point, V1S ... V when information is held
1, V1H ... V1 when transitioning from VN1 to VN0,
V1L ... V1 and VW when shifting from VN0 to VN1
W, VWW1 ... Word line for writing information, VWR, VWR
1 ... Information read word line, VBL, VBL1 ... Data line, VGL, VGL1 ... Ground line, MC, MC11
... memory cell, BS1 ... data line selection line, VNL0, VNL
NL1 ... Voltage stable point when information is held, VNH0, VNH1
… Voltage stability point when reading information, FE… Ferroelectric film, H
E ... Paraelectric film, S ... Source, D ... Drain, SUB ...
Substrate, WL1 ... Word line, BL1, BLB1 ... Data line pair, PL1 ... Plate line, BLP ... Precharge signal.

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁵ Identification number Reference number within the agency FI Technical indication location H01L 27/04 C 8427-4M 27/108 (72) Inventor Yoshinobu Nakagome 1 Higashi Koikeku, Kokubunji, Tokyo 280-chome, Central Research Laboratory, Hitachi, Ltd. (72) Inventor Masakazu Aoki 1-280, Higashi-Kengikubo, Kokubunji, Tokyo Metropolitan Research Center, Hitachi, Ltd.

Claims (6)

[Claims] 1. A memory cell having two capacitors connected in series, a voltage applying means for applying a voltage to both ends of the capacitor column, and a detection circuit for detecting a voltage at a connection node of the two capacitors. On a semiconductor substrate, and one of the two capacitors is a ferroelectric capacitor in which a ferroelectric substance is sandwiched between capacitor electrodes.
The other of the two capacitors is a paraelectric capacitor in which a paraelectric material is sandwiched between capacitor electrodes, which is a semiconductor memory. 2. The detection circuit has a field effect transistor whose gates are electrically connected to the connection nodes of the two capacitors, and the voltage at the connection node of the two capacitors is the source of the field effect transistor. The semiconductor memory according to claim 1, wherein the current is converted into a current between the drain and the drain. 3. The memory according to claim 2, wherein the detection circuit has a selection field effect transistor for interrupting a current flowing through the source-drain of the field effect transistor. 4. The memory according to claim 1, wherein the paraelectric material is a perovskite oxide. 5. The memory according to claim 1, wherein the ferroelectric substance is a perovskite oxide. 6. The memory according to claim 1, wherein the ferroelectric substance is BaTiO3.