JPH0554005A - Multiprocessor system - Google Patents

Abstract

(57) [Abstract] [Purpose] In a multiprocessor system, multiple semaphore registers are provided when there is no need to perform an address check on the main memory and the main memory is divided into multiple areas to control usage rights for each processor. The TAS process can be realized by only one register read though it is a simple circuit. [Structure] The main memory 6 is divided into a plurality of areas, and the semaphore register 5 is associated with each of the divided areas. For example, when the processor 1 accesses the main memory, the semaphore register control circuit 3 reads the content from the semaphore register 5 corresponding to the divided area of the main memory, and writes the predetermined data "1" regardless of the read content. .. If the read content is other than the predetermined data, the processor 1 acquires the right to use the main memory.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a multiprocessor system including at least two processors which communicate with each other by sharing a storage area, and more particularly to exclusive control of main memory usage between the processors.

[0002]

2. Description of the Related Art Generally, in this type of system, when a processor performs a test and set (hereinafter, referred to as "TAS") for exclusive control with respect to a specific address having a main memory, the processor has a memory on a system bus. After outputting the access prohibition signal to prohibit the memory access of other processors,
A TAS memory read request is issued to read the test data at TAS. Then, when this read data is returned, the processor performing the TAS checks whether or not the read data is the data to be set. if,
If the read data is set data, this TAS request processor determines that another processor is processing a task of the same purpose, and turns off the memory access prohibition signal output to the system bus to prohibit memory access. Cancel the state. On the other hand, if the read data is reset data, the TAS request processor outputs a memory write request for writing the set data to the specific address, and then turns off the memory access prohibition signal. In this case, the task processing right is given to the TAS request processor. Such a TAS procedure is executed by firmware control of each processor, but particularly when the test data read by the TAS request is reset data, memory access is required twice, and memory access on the system bus is required. The prohibition signal is also output for a long time, during which no other processor can access the memory. In order to solve such a defect, recently, when a TAS request is made, the test data is read from a specific address in the main memory, the read data is sent to the TAS request processor, and the predetermined set data is specified. Japanese Patent Laid-Open No. 2-12 discloses an invention of a TAS system which simplifies the TAS procedure on the processor side by performing unconditionally writing data to the address contents in one memory access for the TAS request processor.
No. 1053.

[0003]

As described above, the test data is read from the specific address having the main memory, the read data is sent to the TAS request processor, and the predetermined set data is not stored in the content of the specific address. Even if the data writing to be performed under the condition is performed by one memory access, there are the following drawbacks. A) An address check on the main memory is required to determine whether the processor is performing the TAS process, which complicates the circuit and increases the processing time. A) When the main memory is divided into a plurality of areas to control the usage right for each processor, a plurality of address checks are required, and the checked addresses must be used when setting predetermined data. Yes The circuit becomes complicated. C) For one TAS process, memory read, memory write, and two memory bus cycles occur, memory access becomes impossible during that time, and the system performance decreases.

The object of the present invention is to overcome these drawbacks,
There is no need to perform address check on the main memory, and when dividing the main memory into a plurality of areas to control the usage right for each processor, it is a simple circuit that requires only one semaphore register to perform one TAS process. It is to provide a multiprocessor system that can be realized only by register read of.

[0005]

In order to achieve the above-mentioned object, a multiprocessor system according to the present invention has at least two processors, and n or more, where n that can be accessed from a plurality of processors is an integer of 1 or more. A main memory divided into parts, n semaphore registers accessible to the plurality of processors and associated with each divided part of the main memory, and from the plurality of processors to the semaphore registers Access from only one processor is permitted at the same time, and the content of the semaphore register is output to the processor at the time of read access, and predetermined set data is output to the semaphore register regardless of the content. A semaphore register control circuit for writing to the main memory and the plurality of processors for the main memory. 1 at the same time of the access from the
A main memory control device that permits only access from one processor, and when any processor accesses the main memory device, the corresponding semaphore register is read, and if the read value is other than the predetermined set data , The right to use the area of the main storage device corresponding to the semaphore register can be acquired.

[0006]

The present invention will be described in more detail with reference to the drawings. FIG. 1 is a circuit block diagram showing the configuration of a multiprocessor system according to the present invention. Each of the plurality of processors 1, 2, ... N is configured to be able to access the semaphore register 5 via the semaphore register control circuit 3. The main memory 6 can be accessed via the main memory control circuit 4.

FIG. 2 is a diagram showing the relationship between the main memory and the semaphore register. The area of the main memory 6 is divided into n areas, and n semaphore registers 5 are provided in association with the areas. Figure 2
In this example, addresses 0 to FFF, 1000 to 1FFF ...
-It is divided into 5 areas of 4000 to 4FFF and 5 semaphore registers 5 are associated with each other.

FIG. 3 is a circuit block diagram showing an embodiment of the semaphore register control circuit of FIG. 1, which is an example of a case where two processors share a main memory. The semaphore register control circuit 3 selects a circuit 3a for controlling access from the CPUs (processors) 1 and 2 and data, addresses, read / write (R / W) for the CPUs 1 and 2, read data, and READY. It is composed of a circuit portion that outputs a signal. CPU 1 and 2
The address bus, the R / W line, and the data bus are connected to the semaphore register 5 via selection circuits 11, 12 and 13, respectively. The amplifiers 14 and 15 read data from the CPUs 1 and 2. Further, the READY signal to the CPUs 1 and 2 is also output via the amplifiers 16 and 17.

The access signal from the CPUs 1 and 2 is F
F (flip-flop circuit) 20 and 21 are set. For example, if there is an access from the CPU 1, the FF 28 is set via the AND gate 27, and the selection circuits 11, 12 and 13 are set to the CPU by the set signal of the FF 28.
Select side 1. At the same time, the amplifier 16 outputs a READY signal. Then, the AND gate 23 is closed via the inverter circuit 22 to prohibit access from the CPU 2. On the other hand, if there is access from CPU2, FF2
1 is set, AND gate 23, OR gate 25,
The FF 29 is set via the AND gate 26. F
The output of F29 causes the inverter circuit 24 to close the AND gate 27 and prohibit access from the CPU 1. At the same time, the FF 28 is reset, and the reset signals cause the selection circuits 11, 12 and 13 to select the CPU 2 side. At the same time, the amplifier 17 is READ by the set signal of FF29.
Output Y signal.

FIG. 4 is a flow chart showing the control procedure of the multiprocessor system according to the present invention, which is an example when the processor 1 requests the use of the main memory. When the processor 1 outputs a use request signal to the main memory (S
1), access from the processor 2 is prohibited by the access control circuit 3a shown in FIG. 3, and the address bus, R / R of the processor 1 is controlled by the output of the access control circuit 3a.
Select W line and data bus. A read signal is input from the processor 1 and data is read from an address (semaphore register corresponding to a divided area in the main memory) designated by the processor 1 (S2). After reading the data, the processor 1 sends a write signal to put the semaphore register 5 into the write mode and writes the data "1" to the same address regardless of the contents (S3). If the read data is "1", the processor 1 determines that the request is rejected (S4) and ends the access. When the read data is "0", it is determined that the request is permitted (S5), and thereby the area corresponding to the semaphore register in the main memory is accessed via the main memory control circuit 4 (S6). When the processor 1 finishes accessing the main memory, it puts the semaphore register in the write mode and writes the data "0" to abandon the use right (S7).

FIG. 5A is a diagram showing an example of a hardware configuration in which the processor accesses and reads the semaphore register and then writes the data "1" into the semaphore register. The read amplifier 19 corresponds to the amplifier 14 or 15 in FIG. 3, and the delay circuit 18 and the OR gates 18a and 18b are provided in front of the selection circuits 12 and 13. Figure 5
When the read signal is transmitted as shown in (b), the contents of the semaphore register 5 are read by the read amplifier 19 and the read signal is delayed by the delay circuit 18 and input to the OR gate 18b as a write signal. A write signal is input to the semaphore register 5 from the OR gate 18b, and data "1" is input via the OR gate 18a.
Is written. Then, after the end of the main memory access, a write signal is sent and the data “0” is written in the semaphore register 5.

FIG. 6 is a time chart showing the flow of processing for the processors 1 and 2. When the processor 1 is accessed to enter the read mode, the circuit of FIG. 5A causes the read mode to be followed by the hardware write mode. Therefore, the address signal sent from the processor 1 is only once in the read mode. When there is a subsequent access request from the processor 2, the processor 2 becomes accessible after the completion of the hard write.

[0013]

Since the multiprocessor system according to the present invention is configured as described above, it has the following advantages. First, since the reading of the semaphore register corresponds to the TAS processing as it is, conventionally it was necessary to perform the address check surrounded by the one-dot chain line in FIG. 4, but the circuit configuration is simplified without the need. Further, since it is only necessary to prepare the semaphore register corresponding to the divided area of the main memory, it is possible to cope with it by adding a simple circuit. FIG. 9 shows a conventional write / read configuration of a semaphore register, which can be accommodated by adding semaphore registers corresponding to the number of divided regions, and delay circuits and OR circuits as shown in FIG.
Further, a bus lock mechanism for prohibiting other access at the time of TAS processing becomes unnecessary. As is apparent from comparison between the address control circuit 3a of the semaphore register control circuit according to the present invention in FIG. 3 and the conventional address control circuit in FIG. 7, the CPU1-LOCK and CPU2 shown in FIG.
-A circuit related to LOCK, that is, FFs 21 and 3
Circuit parts such as 0, 36, AND gates 33, 35 and OR gate 34 are deleted. Of course, the LOCK signal generation circuit on the side that sends out the LOCK signal can be deleted. In the conventional technique, as shown in FIG. 8, for example, after a read cycle is reached by the access of the CPU 1, a signal for locking the CPU 1 is sent, and then a write cycle is started. And CPU2
When there is an access request from, it is possible to access after the write cycle. However, according to the present invention, as is apparent from FIG. 6, the TAS process can be realized by only one register read, so that the performance of the system can be improved.

[Brief description of drawings]

FIG. 1 is a circuit block diagram showing a configuration of a multiprocessor system according to the present invention.

FIG. 2 is a diagram showing a relationship between a main memory and a semaphore register.

FIG. 3 is a circuit block diagram showing an embodiment of the semaphore register control circuit of FIG.

FIG. 4 is a flowchart showing a control procedure of the multiprocessor system according to the present invention.

FIG. 5 is a diagram for explaining a read / write hardware configuration of a semaphore register.

FIG. 6 is a time chart showing a processing flow for processors 1 and 2.

FIG. 7 is a circuit diagram showing an example of a conventional address control circuit.

FIG. 8 is a diagram for explaining a conventional operation cycle when a processor accesses.

FIG. 9 is a circuit diagram showing a read / write configuration of a conventional semaphore register.

[Explanation of symbols]

 1, 2 ... Processor 3 ... Semaphore register control circuit 4 ... Main memory control circuit 5 ... Semaphore register 6 ... Main memory 11, 12, 13 ... Selection circuit 14, 15, 16, 17 ... Amplifier 18 ... Delay circuit 20, 21, 28, 29 ... FF 22, 24 ... Inverter circuit 23, 26, 27 ... AND gate 25 ... OR gate

Claims (1)

[Claims] 1. At least two or more processors, a main memory device divided into n or more parts in which n is an integer of 1 or more, accessible from the plurality of processors, and the main memory accessible from the plurality of processors. N n semaphore registers associated with each divided part of the storage device, and at the same time, permitting only one processor to access the semaphore registers from the plurality of processors, and A semaphore register control circuit that outputs the contents of the semaphore register to the processor at the time of read access and writes predetermined set data to the semaphore register regardless of the contents, and the plurality of processors to the main storage device. Main access that allows access from only one processor at a time A memory controller, and when any processor accesses the main memory, the corresponding semaphore register is read, and if the read value is other than the predetermined set data, the main memory corresponding to the semaphore register. A multiprocessor system characterized by being configured so as to acquire the right to use the area.