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JPH0548033A - Semiconductor device and manufacturing method thereof - Google Patents

Semiconductor device and manufacturing method thereof

Info

Publication number
JPH0548033A
JPH0548033A JP3200147A JP20014791A JPH0548033A JP H0548033 A JPH0548033 A JP H0548033A JP 3200147 A JP3200147 A JP 3200147A JP 20014791 A JP20014791 A JP 20014791A JP H0548033 A JPH0548033 A JP H0548033A
Authority
JP
Japan
Prior art keywords
fin
insulating film
semiconductor substrate
film
semiconductor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
JP3200147A
Other languages
Japanese (ja)
Inventor
Akinao Ogawa
明直 小川
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP3200147A priority Critical patent/JPH0548033A/en
Publication of JPH0548033A publication Critical patent/JPH0548033A/en
Withdrawn legal-status Critical Current

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  • Semiconductor Integrated Circuits (AREA)
  • Semiconductor Memories (AREA)

Abstract

(57)【要約】 【目的】 DRAMのキャパシタのストレージノードな
どに用いられるフィン形状の構造体に関し,形状の安定
性,後工程における平坦化の歩留まりを向上させて,半
導体装置の信頼性を向上させる。 【構成】 半導体基板1の表面に第1の絶縁膜2および
第2の絶縁膜を形成する。第2の絶縁膜および第1の絶
縁膜2を選択的に除去して,半導体基板1が露出するコ
ンタクト窓3を開口する。全面に半導体層または導体層
を堆積させた後,所定の形状にパターニングする。第2
の絶縁膜を除去する。熱処理を施して,半導体層または
導体層から成るフィン4を半導体基板1の方向に湾曲さ
せる。
(57) [Abstract] [Purpose] For a fin-shaped structure used for a storage node of a DRAM capacitor, the stability of the shape and the yield of planarization in a post process are improved, and the reliability of a semiconductor device is improved. Let [Structure] A first insulating film 2 and a second insulating film are formed on a surface of a semiconductor substrate 1. The second insulating film and the first insulating film 2 are selectively removed to open the contact window 3 exposing the semiconductor substrate 1. After depositing a semiconductor layer or a conductor layer on the entire surface, it is patterned into a predetermined shape. Second
The insulating film of is removed. Heat treatment is applied to bend the fin 4 made of a semiconductor layer or a conductor layer toward the semiconductor substrate 1.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明は,半導体装置およびその
製造方法,特にDRAMのキャパシタのストレージノー
ドなどに用いられるフィン形状の構造体に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a method of manufacturing the same, and more particularly to a fin-shaped structure used for a storage node of a DRAM capacitor.

【0002】近年,半導体装置の高集積化,微細化に伴
い,半導体装置のパターンを形成する際に,単に2次元
的にレイアウトするだけでなく,3次元的に形成して集
積度を高める方法が採られている。3次元化の1つの方
法として,フィン構造が提案されており,DRAMのキ
ャパシタなどに適用されている。
In recent years, with the increasing integration and miniaturization of semiconductor devices, a method of forming a pattern of a semiconductor device is not limited to a two-dimensional layout but a three-dimensional formation to increase the degree of integration. Has been taken. A fin structure has been proposed as one of three-dimensionalization methods and is applied to DRAM capacitors and the like.

【0003】[0003]

【従来の技術】従来,フィン形状の構造体を形成するの
に,次の方法が採られていた。 Si 基板の表面にS
iO2 膜およびSi3 4 膜を順次形成する。
2. Description of the Related Art Conventionally, the following method has been adopted to form a fin-shaped structure. Si on the surface of the Si substrate
An iO 2 film and a Si 3 N 4 film are sequentially formed.

【0004】 Si3 4 膜の表面にSiO2 膜を形
成する。 Si3 4 膜上のSiO2 膜,Si3 4
膜,およびSiO2 膜を選択的に除去してSi 基板が露
出するコンタクト窓を形成する。
A SiO 2 film is formed on the surface of the Si 3 N 4 film. The Si 3 N 4 film on the SiO 2 film, Si 3 N 4
The film and the SiO 2 film are selectively removed to form a contact window exposing the Si substrate.

【0005】 全面にポリシリコンを堆積させた後,
形成すべきフィンの形状にパターニングする。 Si
3 4 膜上のSiO2膜を除去する。
After depositing polysilicon on the entire surface,
Patterning is performed in the shape of the fin to be formed. Si
The SiO 2 film on the 3 N 4 film is removed.

【0006】[0006]

【発明が解決しようとする課題】従来のフィンは,前記
の工程後,フィンを構成するポリシリコン層が持つス
トレスなどにより,フィンの形状が複雑に歪曲してしま
う,という問題があった。
The conventional fin has a problem that the shape of the fin is complicatedly distorted after the above-mentioned steps due to stress of the polysilicon layer forming the fin.

【0007】また,従来のフィンの形状では,フィンの
形成によって生じる段差が厳しく,後工程での平坦化が
困難である,という問題もあった。本発明は,これらの
問題点を解決して,意図的にフィンを湾曲させて,半導
体装置の性能を向上させた半導体装置およびその製造方
法,特にDRAMのキャパシタのストレージノードなど
に用いられるフィン形状の構造体およびその製造方法を
提供することを目的とする。
Further, in the conventional fin shape, there is a problem that the step caused by the fin formation is severe and it is difficult to flatten in the subsequent process. The present invention solves these problems and intentionally bends the fin to improve the performance of the semiconductor device, and a method of manufacturing the same, and in particular, a fin shape used for a storage node of a capacitor of DRAM or the like. An object of the present invention is to provide a structure and a manufacturing method thereof.

【0008】[0008]

【課題を解決するための手段】上記の目的を達成するた
めに,本発明に係る半導体装置は,半導体基板上に形成
されたフィン形状の構造体であって,フィンを半導体基
板の表面方向に湾曲させるように構成する。
In order to achieve the above-mentioned object, a semiconductor device according to the present invention is a fin-shaped structure formed on a semiconductor substrate, and the fin is arranged in the surface direction of the semiconductor substrate. It is configured to be curved.

【0009】本発明に係る半導体装置の製造方法は,半
導体基板上に形成されたフィン形状の構造体の製造方法
であって,半導体基板の表面に第1の絶縁膜および第2
の絶縁膜を形成する工程と,第2の絶縁膜および第1の
絶縁膜を選択的に除去して,半導体基板が露出するコン
タクト窓を開口する工程と,全面に半導体層または導体
層を堆積させた後,所定の形状にパターニングする工程
と,前記第2の絶縁膜を除去する工程と,熱処理を施し
て,半導体層または導体層から成るフィンを半導体基板
の方向に湾曲させる工程とを含むように構成する。
A method of manufacturing a semiconductor device according to the present invention is a method of manufacturing a fin-shaped structure formed on a semiconductor substrate, wherein the first insulating film and the second insulating film are formed on the surface of the semiconductor substrate.
Forming an insulating film, forming a contact window exposing the semiconductor substrate by selectively removing the second insulating film and the first insulating film, and depositing a semiconductor layer or a conductor layer on the entire surface. After that, a step of patterning into a predetermined shape, a step of removing the second insulating film, and a step of performing a heat treatment to bend the fin made of the semiconductor layer or the conductor layer toward the semiconductor substrate are included. To configure.

【0010】図1は本発明の基本構成を示す図である。
同図において,1は半導体基板,2は絶縁膜,3はコン
タクト窓,4は半導体または導電体から成るフィンであ
る。
FIG. 1 is a diagram showing the basic configuration of the present invention.
In the figure, 1 is a semiconductor substrate, 2 is an insulating film, 3 is a contact window, and 4 is a fin made of a semiconductor or a conductor.

【0011】[0011]

【作用】本発明に係るフィン形状の構造体は,フィン4
を意図的に半導体基板1の表面方向に湾曲させているの
で,フィン4の形状を再現性良く,安定に形成すること
ができる。また,後工程における平坦化も容易になる。
The fin-shaped structure according to the present invention includes the fin 4
Is intentionally curved toward the surface of the semiconductor substrate 1, so that the shape of the fin 4 can be formed stably with good reproducibility. In addition, flattening in the post process becomes easy.

【0012】本発明に係るフィン4は,次のようにして
形成する。すなわち,半導体基板1の表面に絶縁膜2お
よび他の絶縁膜を順次形成し,これら2つの絶縁膜を選
択的に開口してコンタクト窓3を形成する。その後,全
面に半導体層または導体層を堆積させ,フィン4の形状
にパターニングし,フィン4下の絶縁膜を除去した後,
熱処理を施すことによりフィン4を意図的に半導体基板
の表面方向に湾曲させる。
The fin 4 according to the present invention is formed as follows. That is, the insulating film 2 and another insulating film are sequentially formed on the surface of the semiconductor substrate 1, and these two insulating films are selectively opened to form the contact window 3. After that, a semiconductor layer or a conductor layer is deposited on the entire surface, patterned into the shape of the fin 4, and the insulating film under the fin 4 is removed.
By performing heat treatment, the fin 4 is intentionally curved in the surface direction of the semiconductor substrate.

【0013】[0013]

【実施例】図2は本発明の一実施例を示す図であり,本
発明をDRAMのキャパシタの形成に適用したものであ
る。
2 is a diagram showing an embodiment of the present invention, in which the present invention is applied to the formation of a DRAM capacitor.

【0014】同図において,11はp型Si 基板,12
はフィールドSiO2 膜(FOX),13はポリシリコ
ンゲート,14はn型ドレイン,15はSiO2 膜,1
6はSi3 4 膜,18はコンタクト窓,19はポリシ
リコンから成るフィンで形成したストレージノード,2
0はキャパシタ絶縁膜,21および22はセルプレート
である。
In the figure, 11 is a p-type Si substrate, and 12
Is a field SiO 2 film (FOX), 13 is a polysilicon gate, 14 is an n-type drain, 15 is a SiO 2 film, 1
6 is a Si 3 N 4 film, 18 is a contact window, 19 is a storage node formed by a fin made of polysilicon, 2
Reference numeral 0 is a capacitor insulating film, and 21 and 22 are cell plates.

【0015】本実施例のポリシリコンから成るフィンで
形成したストレージノード19は,一様に湾曲している
ので,形状が安定していると共に,後工程における平坦
化が容易となる。
Since the storage node 19 formed by the fin made of polysilicon of this embodiment is uniformly curved, the shape is stable and the flattening in the post-process becomes easy.

【0016】次に,図2に至る製造方法を工程順に説明
する。 [工程1,図3]p型Si 基板11の表面に,LOCO
S法によりフィールド酸化膜(FOX)12を形成した
後,通常の方法によりポリシリコンゲート13およびド
レイン14を形成する。
Next, the manufacturing method up to FIG. 2 will be described in the order of steps. [Step 1, FIG. 3] LOCO is formed on the surface of the p-type Si substrate 11.
After forming the field oxide film (FOX) 12 by the S method, the polysilicon gate 13 and the drain 14 are formed by the usual method.

【0017】全面に膜厚1000ÅのSiO2 膜15お
よび膜厚100ÅのSi3 4 膜16を順次形成する。
Si3 4 膜16の表面に膜厚約5000ÅのSiO2
膜17を形成する。
A SiO 2 film 15 having a film thickness of 1000 Å and a Si 3 N 4 film 16 having a film thickness of 100 Å are sequentially formed on the entire surface.
The surface of the Si 3 N 4 film 16 has a thickness of about 5000 Å SiO 2
The film 17 is formed.

【0018】フォトリソグラフィ技術によって,SiO
2 膜17,Si3 4 膜16,およびSiO2 膜15を
選択的にエッチングして,Si 基板11の表面が露出す
るコンタクト窓18を開口する。
By photolithography technology, SiO
The 2 film 17, the Si 3 N 4 film 16 and the SiO 2 film 15 are selectively etched to open a contact window 18 exposing the surface of the Si substrate 11.

【0019】全面にポリシリコン層19を1000Åの
厚さに堆積させる。フォトリソグラフィ技術によって,
ポリシリコン層19をフィンの形状にパターニングす
る。
A polysilicon layer 19 is deposited on the entire surface to a thickness of 1000Å. By photolithography technology,
The polysilicon layer 19 is patterned into a fin shape.

【0020】[工程2,図3,図4]SiO2 膜17を
エッチングによって除去する。 [工程3,図4,図2]800〜900℃,30分間程
度の熱処理を施して,ポリシリコン層19をSi 基板1
1方向に一様に湾曲させてストレージノード19を形成
する。
[Step 2, FIG. 3, FIG. 4] The SiO 2 film 17 is removed by etching. [Step 3, FIG. 4, FIG. 2] Heat treatment is performed at 800 to 900 ° C. for about 30 minutes to form the polysilicon layer 19 on the Si substrate 1.
The storage node 19 is formed by being uniformly curved in one direction.

【0021】ストレージノード19の表面全体にキャパ
シタ絶縁膜20を形成する。キャパシタ絶縁膜20の表
面全体にポリシリコンを堆積させて,セルプレート21
および22を形成する。
A capacitor insulating film 20 is formed on the entire surface of the storage node 19. Polysilicon is deposited on the entire surface of the capacitor insulating film 20, and the cell plate 21
And 22 are formed.

【0022】以上の各工程を経て,本実施例のDRAM
のキャパシタが完成する。本実施例では,フィンが1枚
の場合を示したが,2枚以上のフィン構造の場合も本実
施例と全く同様にフィンを一様に湾曲させることが可能
である。この場合,後工程における平坦化のメリット
は,より大きくなる。
Through the above steps, the DRAM of this embodiment
Capacitor is completed. In the present embodiment, the case where the number of fins is one is shown, but even in the case of a fin structure having two or more fins, the fins can be uniformly curved in exactly the same manner as this embodiment. In this case, the merit of the flattening in the subsequent process becomes larger.

【0023】[0023]

【発明の効果】本発明によれば,DRAMのキャパシタ
のストレージノードなどに用いられるフィン形状の構造
体において,意図的にフィンを湾曲させているので,形
状の安定性,後工程における平坦化の歩留まり向上,半
導体装置の信頼性の向上に寄与するところが大きい。
According to the present invention, in a fin-shaped structure used for a storage node of a DRAM capacitor, the fins are intentionally curved, so that the stability of the shape and the flattening in the subsequent process can be achieved. It greatly contributes to the improvement of yield and the reliability of semiconductor devices.

【図面の簡単な説明】[Brief description of drawings]

【図1】本発明の基本構成を示す図である。FIG. 1 is a diagram showing a basic configuration of the present invention.

【図2】本発明の一実施例製造方法の一工程を示す図で
ある。
FIG. 2 is a diagram showing a step in a manufacturing method according to an embodiment of the present invention.

【図3】本発明の一実施例製造方法の一工程を示す図で
ある。
FIG. 3 is a diagram showing a step in a manufacturing method according to an embodiment of the present invention.

【図4】本発明の一実施例製造方法の一工程を示す図で
ある。
FIG. 4 is a diagram showing a step in a manufacturing method according to an embodiment of the present invention.

【符号の説明】[Explanation of symbols]

1 半導体基板 2 絶縁膜 3 コンタクト窓 4 フィン 1 semiconductor substrate 2 insulating film 3 contact window 4 fin

Claims (2)

【特許請求の範囲】[Claims] 【請求項1】 半導体基板上に形成されたフィン形状の
構造体であって, フィンを半導体基板の表面方向に湾曲させたことを特徴
とする半導体装置。
1. A semiconductor device comprising a fin-shaped structure formed on a semiconductor substrate, wherein the fin is curved in a surface direction of the semiconductor substrate.
【請求項2】 半導体基板上に形成されたフィン形状の
構造体の製造方法であって, 半導体基板の表面に第1の絶縁膜および第2の絶縁膜を
形成する工程と, 第2の絶縁膜および第1の絶縁膜を選択的に除去して,
半導体基板が露出するコンタクト窓を開口する工程と, 全面に半導体層または導体層を堆積させた後,所定の形
状にパターニングする工程と, 前記第2の絶縁膜を除去する工程と, 熱処理を施して,半導体層または導体層から成るフィン
を半導体基板の方向に湾曲させる工程とを含むことを特
徴とする半導体装置の製造方法。
2. A method of manufacturing a fin-shaped structure formed on a semiconductor substrate, comprising: forming a first insulating film and a second insulating film on a surface of the semiconductor substrate; and a second insulating film. Selectively removing the film and the first insulating film,
A step of opening a contact window exposing the semiconductor substrate; a step of depositing a semiconductor layer or a conductor layer on the entire surface and then patterning into a predetermined shape; a step of removing the second insulating film; and a heat treatment. And a step of bending a fin made of a semiconductor layer or a conductor layer in the direction of the semiconductor substrate.
JP3200147A 1991-08-09 1991-08-09 Semiconductor device and manufacturing method thereof Withdrawn JPH0548033A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP3200147A JPH0548033A (en) 1991-08-09 1991-08-09 Semiconductor device and manufacturing method thereof

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP3200147A JPH0548033A (en) 1991-08-09 1991-08-09 Semiconductor device and manufacturing method thereof

Publications (1)

Publication Number Publication Date
JPH0548033A true JPH0548033A (en) 1993-02-26

Family

ID=16419574

Family Applications (1)

Application Number Title Priority Date Filing Date
JP3200147A Withdrawn JPH0548033A (en) 1991-08-09 1991-08-09 Semiconductor device and manufacturing method thereof

Country Status (1)

Country Link
JP (1) JPH0548033A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5973349A (en) * 1992-03-13 1999-10-26 Fujitsu Limited Stacked capacitor semiconductor device
US5998825A (en) * 1996-10-18 1999-12-07 Sony Corporation Capacitor structure of semiconductor memory cell and method for fabricating capacitor structure of semiconductor memory cell
US6133600A (en) * 1996-08-20 2000-10-17 Micron Technology, Inc. Memory device with improved domed capacitors

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5973349A (en) * 1992-03-13 1999-10-26 Fujitsu Limited Stacked capacitor semiconductor device
US6133600A (en) * 1996-08-20 2000-10-17 Micron Technology, Inc. Memory device with improved domed capacitors
US5998825A (en) * 1996-10-18 1999-12-07 Sony Corporation Capacitor structure of semiconductor memory cell and method for fabricating capacitor structure of semiconductor memory cell
US6287934B1 (en) 1996-10-18 2001-09-11 Sony Corporation Capacitor structure of semiconductor memory cell and method for fabricating capacitor structure of semiconductor cell

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