JPH0540629A - Information processor - Google Patents

Abstract

PURPOSE:To provide an information processor which is not required to set a stop cycle to a load instruction when the store and load instructions are continuously processed on a pipeline. CONSTITUTION:A data holding circuit 4 is provided to hold the data on a store instruction that is carried out earlier together with an address holding circuit 11 which holds the address of the store instruction, an address comparator 12 which compares the address of the circuit 11 with the address of the load instruction, and a data processing part 5 which generates the load data. When the comparator 12 detects a coincident part between the address stored in the circuit 11 and the read address of the load instruction, the part 5 generates the load data to be given to a register file 1 with a load instruction based on the store data held by the circuit 4 and the data read out of 8 date cache memory 3.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an information processing apparatus capable of processing a store instruction and a load instruction following the store instruction at high speed.

[0002]

2. Description of the Related Art Conventionally, a pipeline processing method, a parallel processing method, and the like have been used to increase the execution speed of an information processing apparatus. FIG. 6 shows a schematic configuration of such a conventional information processing apparatus. In FIG. 6, 1 is a register file, 2 is an arithmetic processing unit having the register file 1, and 3 is a data cache memory that functions as a buffer memory of the main memory. Reference numeral 28 is a store instruction data bus, and 30 is a load instruction data bus.

The operation of the information processing apparatus having the above configuration will be described. Here, it is assumed that the store instruction and the load instruction should be executed in this order. Further, the arithmetic processing unit 2 is assumed to perform pipeline processing. FIG. 7 shows the order of stages of respective instructions when the store instruction and the load instruction are pipelined in the information processing apparatus of FIG. In FIG. 7, F is an instruction fetch stage, L is an instruction decode stage, E is an instruction execution stage, M is a memory stage, and S is a store stage.

In the store instruction executed first, the tag is read from the data cache memory 3 in the instruction execution stage E, and when a cache hit is confirmed, the data is written in the data cache memory 3 in the memory stage M. Be done. On the other hand, in the load instruction to be executed next to the store instruction, the tag is read from the data cache memory 3 in the instruction execution stage E, the cache hit is confirmed, and the data is read in the instruction execution stage E. .. In this way, when the load instruction is executed next to the store instruction by pipeline processing, the memory stage M for writing data to the data cache memory 3 in the store instruction and the data cache memory in the load instruction The instruction execution stage E for reading the data from 3 overlaps.

When such a stage overlap occurs, if the storage address in the store instruction and the read address in the load instruction do not match,
Pipeline processing can be performed by the following two methods. That is, the first method is, as shown in FIG. 6, a data bus 28 for a store instruction and a data bus 30 for a load instruction.
Are independently provided, and the data cache memory 3 has a two-port memory cell configuration. As a result, it is possible to simultaneously read the load data and write the store data. In the second method, the data read from the data cache memory 3 in the instruction execution stage E of the load instruction is processed first, and the data write to the data cache memory 3 in the memory stage M of the store instruction is performed. That is, it is delayed and processed in the store stage S.

[0006]

However, if there is a portion that matches the storage address of the store instruction and the read address of the load instruction, it must be done after the store data has been written to the data cache memory 3 first. For example, the correct load data cannot be read from the data cache memory 3 into the register file 1 by the load instruction. In such a case, in the first method, even if the data cache memory 3 has a two-port memory cell configuration, the data storage and the data reading overlap with each other, resulting in malfunction. Further, in the second method, an erroneous operation occurs in which old data before the store data is written by the store instruction is read as the load data.

When the storage address of the store instruction and the read address of the load instruction match in this way, as shown in FIG. 7, one cycle is stopped before the instruction execution stage E of the load instruction to be executed later. Cycle A is provided. By providing this stop cycle A, the memory stage M of the store instruction and the instruction execution stage E of the load instruction are not executed at the same time, and no malfunction occurs.

However, such a stop cycle A
, The load instruction execution stage E is processed after one stop cycle A, which causes a problem that the processing efficiency in the pipeline processing is lowered. Such a problem similarly occurs in an information processing device that performs parallel processing.

The present invention solves the above problems, and an object of the present invention is to provide a stop cycle without
An object of the present invention is to provide an information processing device capable of pipeline processing or parallel processing of a store instruction and a load instruction to be executed next to the store instruction.

[0010]

In order to achieve the above object, the invention of claim 1 is an information processing apparatus for pipeline processing a store instruction and a load instruction to be executed next to the store instruction. The storage address in the instruction,
When there is a part that matches the read address of the load instruction to be executed next, the store data in the store instruction is temporarily held in the data holding circuit, and this held data and the data cache are held. The load data in the load instruction is generated based on the data read from the memory.

Specifically, the means taken by the invention of claim 1 is as follows.
Targeting an information processing device capable of pipeline processing a store instruction and a load instruction to be executed next to the store instruction,
An arithmetic processing unit having a register file, a data cache memory, a data holding circuit for temporarily holding store data to be read from the register file and stored in the data cache memory based on the store instruction, and the store instruction Address holding circuit for holding the storage address in the load instruction, an address comparator for comparing the address held in the address holding circuit with the read address in the load instruction, and the address holding circuit for the address holding circuit. Data stored in the data holding circuit and the data read from the data cache memory when it is detected that there is a matching portion between the storage address held in the memory and the read address in the load instruction. Based on and before in the load instruction It is an arrangement comprising a data processing unit that generates load data to the register file.

According to a second aspect of the present invention, in an information processing apparatus for concurrently processing a store instruction and a load instruction to be executed next to the store instruction in parallel, the storage address of the store instruction and then the storage address of the store instruction. When there is a part that matches the read address of the load instruction to be executed, the load data in the load instruction is generated based on the store data in the store instruction and the data read from the data cache memory. It is a thing.

Specifically, the means taken by the invention of claim 2 is as follows.
An arithmetic processing unit having a register file, a data cache memory, a storage address in the store instruction, and the storage instruction for the information processing apparatus capable of parallel processing a store instruction and a load instruction to be executed next to the store instruction. An address comparator for comparing the read address in the load instruction and the address comparator, when the address comparator detects that there is a matching portion between the storage address in the store instruction and the read address in the load instruction A data processing unit for generating load data to the register file in the load instruction based on the store data in the store instruction and the data read from the data cache memory. Is.

[0014]

According to the structure of the present invention, the address comparator has a coincident portion between the storage address in the store instruction held in the address holding circuit and the read address in the load instruction. If the load instruction is detected, based on the store data of the data holding circuit that temporarily holds the data to be stored in the data cache memory in the store instruction and the data read from the data cache memory, Since the data processing unit that generates the load data to the register file is provided, it becomes possible to pipeline the store instruction and the load instruction without providing a stop cycle.

According to the second aspect of the present invention, when the address comparator detects that there is a coincident portion between the store address in the store instruction and the read address in the load instruction, the store is performed. Since the data processing unit that generates the load data to the register file in the load instruction based on the store data to be stored in the data cache memory in the instruction and the data read from the data cache memory is provided, And the load instruction can be processed in parallel without providing a stop cycle.

[0016]

Embodiments of the information processing apparatus according to the present invention will be described below with reference to the drawings. 1 of the present invention
2 shows a schematic configuration of an information processing apparatus according to the embodiment of FIG. As shown in FIG. 1, the information processing apparatus of the present embodiment includes an arithmetic processing unit 2 having a register file 1, a data cache memory 3 functioning as a buffer memory of a main memory,
A data holding circuit 4 for temporarily holding the data read from the register file 1 by the store instruction, an address holding circuit 11 for holding the storage address in the store instruction, an address of the address holding circuit 11 and the store instruction An address comparator 12 for comparing the read address of the load instruction to be executed next, and store it in the register file 1 based on the store data held in the data holding circuit 4 and the data read from the data cache memory 3. And a data processing unit 5 for generating load data.

The store data from the register file 1 is transferred to the data holding circuit 4 by the first store instruction data bus 6, and the data held in the data holding circuit 4 is stored in the second store instruction data bus 8. To the data cache memory 3 and to the data processing unit 5 by the bypass data bus 9. Further, the data of the data cache memory 3 is transferred to the data processing unit 5 by the second load instruction data bus 10, and the load data generated by the data processing unit 5 is transferred to the register file by the first load instruction data bus 7. Forwarded to 1. The execution address output from the arithmetic processing unit 2 is the first
Is input to the address comparator 12 and the address holding circuit 11 via the address bus 13. Address holding circuit 1
The address held in 1 is the second address bus 1
4 is input to the address comparator 12. The comparison result of the address comparator 12 is input to the data processing unit 5 via the comparison signal line 15. Further, a signal indicating the size of data in each instruction is input to the data processing unit 5 from the arithmetic processing unit 2 via the data size signal line 16.

In the information processing apparatus of this embodiment, it is assumed that the store instruction and the load instruction to be subsequently executed are pipelined in this order. FIG. 2 shows the order of the stages of each instruction when the store instruction and the load instruction are pipelined in the information processing apparatus of FIG. In FIG. 2, F is the instruction fetch stage, L
Is an instruction decode stage, E is an instruction execution stage, M is a memory stage, and S is a store stage.

In this embodiment, when the store address of the store instruction and the read address of the load instruction to be executed next do not match, the store instruction is executed from the data cache memory 3 in the instruction execution stage E. After the tag is read and the cache hit is confirmed, the data is written in the data cache memory 3 in the memory stage M. On the other hand, in the load instruction to be executed next to the store instruction, the tag is read from the data cache memory 3 in the instruction execution stage E, and after the cache hit is confirmed, the data is read in the instruction execution stage E. Read out. When the store address of the store instruction and the read address of the load instruction match, the instruction execution stage E for reading the load data is executed before the store data is stored, and the store data is stored in the store stage. It is done in S.

The operation of the information processing apparatus of this embodiment will be described in detail below. First, a storage instruction outputs a storage address from the arithmetic processing unit 2 to the first address bus 13 and holds it in the address holding circuit. Next, the read address is output from the arithmetic processing unit 2 to the first address 13 by the load instruction, is input to the address comparator 12, and the storage address in the store instruction is output from the address holding circuit 11 to the address comparator 12. Entered in. The address comparator 12 compares the storage address in the store instruction with the read address in the load instruction to check whether there is a coincident portion between the storage address and the read address.

FIG. 3 shows the positional relationship between the storage address A1 of the store data in the store instruction and the read address A2 of the load data in the load instruction.
The address compared by the address comparator 12 is the maximum size of address data handled in the store instruction and the load instruction, and is different from the storage address in the store instruction and the read address in the load instruction, respectively. There are cases. Here, the address compared by the address comparator 12 is an address in 8-byte units, and this is 8
Defined as a byte address. As shown in FIG.
The storage address A1 in the store instruction is 1000,
When the data size is 8 bytes, the read address A2 in the load instruction is address 1008, and the data size is 8 bytes, that is, when there is no part that matches the 8-byte address of the store instruction and the 8-byte address of the load instruction think of. In this case, the store instruction and the load instruction have no data dependency relationship with each other, and the store instruction and the load instruction are pipelined as in the above-mentioned conventional example.

On the other hand, as shown in FIG. 3B, the store address A1 of the store instruction is 1000, the data size is 4 bytes, and the read address A2 of the load instruction is 100.
Consider the case where the address is 0 and the data size is 8 bytes. In this case, there is a portion that matches the 8-byte address of the store instruction and the 8-byte address of the load instruction. That is, the 4-byte store data from the address 1000 to the address 1003 of the storage address A1 corresponds to the read address A2 of 1
It is included as part of the load data from addresses 000 to 1003.

In this case, the comparison signal line 15 outputs a signal from the comparator 12 indicating the coincidence portion between the store address in the store instruction and the read address in the load instruction.
Is sent to the data processing unit 5. On the other hand, the data processing unit 5 sends a signal indicating the size of the store data in the store instruction and a signal indicating the size of the load data in the load instruction from the arithmetic processing unit 2 to the data size signal line 16. Entered through. Further, the data processing unit 5 receives the store data held in the data holding circuit 4 via the bypass data bus 9 and stores the data held in the data cache memory 3 before the execution of the store instruction. It is input via the second load instruction data bus 10. Then, the data processing unit 5 analyzes the signal of the comparison signal line 15 and the signal of the data size signal line 16, and based on the store data from the data holding circuit 4 and the data from the data cache memory 3 before executing the store instruction. Then, the load data in the load instruction is generated. That is, as shown in FIG. 3B, of the data from the data cache memory 3 before execution of the store instruction, which is stored in the address A2, the data from the address 1000 to 1
The data up to address 003 is replaced with the data from address 1000 to address 1003 of address A1 in the store instruction, and load data to be loaded by the load instruction is generated.

As shown in FIG. 3C, the store address A1 of the store instruction is address 1004, the data size is 4 bytes, and the read address A2 of the load instruction is 100.
Even if the address is 0 and the data size is 8 bytes, there is a portion that matches the 8-byte address of the store instruction and the 8-byte address of the load instruction. That is, storage address A1
4 bytes of store data from addresses 1004 to 1007 are included as part of the load data from addresses 1004 to 1007 of the read address A2.

In this case, of the data from the data cache memory 3 before execution of the store instruction stored in the address A2, the data from address 1004 to address 1007 is 1004 of the address A1 in the store instruction.
It is replaced with the data from the address to the address 1007, and the load data to be loaded by the load instruction is generated.

As described with reference to FIGS. 3B and 3C,
The load data generated by data replacement is
In the instruction execution stage E of the load instruction, it is transferred to the register file 1 via the first load instruction data bus 7. The store data held in the data holding circuit 4 is stored in the data cache memory 3 in the store stage S of the store instruction.

In the present embodiment, when the address comparator 12 detects that there is a coincident portion between the storage address in the store instruction held in the address holding circuit 11 and the read address in the load instruction. Based on the data read from the data cache memory 3 and the data in the data holding circuit 4 which temporarily holds the data to be stored in the data cache memory 3 in the store instruction in the data processing unit. Since the load data to the register file 1 in the load instruction is generated, it is not necessary to provide a stop cycle when performing pipeline processing.

The present embodiment can be similarly applied to an information processing apparatus that pipeline-processes a plurality of load instructions after a store instruction.

FIG. 4 shows a schematic configuration of an information processing apparatus according to the second embodiment of the present invention. In the information processing apparatus of this embodiment, the store instruction and the load instruction are processed in parallel as shown in FIG. 5, and the address holding circuit 11 and the data holding circuit 4 shown in FIG. 1 are not provided. The configurations of the register file 1, the arithmetic processing unit 2, the data cache memory 3, the address comparator 12, and the data processing unit 5 are the same as those in the embodiment shown in FIG. The notation of each stage in the store instruction and the load instruction is the same as that in the first embodiment described above.

In this embodiment, the store data from the register file 1 is transferred to the data cache memory 3 by the store instruction data bus 28 and transferred to the data processing unit 5 by the bypass data bus 29.
Further, the data of the data cache memory 3 is transferred to the data processing unit 5 by the second load instruction data bus 20, and the data generated by the data processing unit 5 is transmitted by the first load instruction data bus 27 to the register file 1. Transferred to. The execution address of the store instruction output from the arithmetic processing unit 2 is input to the address comparator 12 via the first address bus 23, and the execution address of the load instruction output from the arithmetic processing unit 2 is the second address. Address bus 2
4 is input to the address comparator 12. The comparison result of the address comparator 12 is input to the data processing unit 5 via the comparison signal line 25. Further, a signal indicating the size of the store data in the store instruction is input from the arithmetic processing unit 2 to the data processing unit 5 via the first data size signal line 21, and the size of the load data in the load instruction is input. The signal indicating the level is the second data size signal line 22
Is input to the data processing unit 5 via.

Also in this embodiment, if the store address of the store instruction and the read address of the load instruction to be executed next do not match, the data cache in the instruction execution stage E in the store instruction. After the tag is read from the memory 3 and the cache hit is confirmed, the data is written in the data cache memory 3 in the memory stage M. On the other hand, the load instruction to be executed next to the store instruction is also executed simultaneously with the store instruction, the tag is read from the data cache memory 3 in the instruction execution stage E of the load instruction, and after the cache hit is confirmed, the instruction Data is read in the effective stage E. If there is a part that matches the store address of the store instruction and the read address of the load instruction,
As the load data, the load data is generated in the load instruction based on the store data and the data stored in the data cache memory 3, and at the same time, the store data is stored in the data cache memory 3.

The operation of the information processing apparatus of this embodiment will be described in detail below. First, a storage instruction outputs a storage address from the arithmetic processing unit 2 to the address comparator 12 via the first address bus 23, and at the same time, a load instruction outputs a read address from the arithmetic processing unit 2 to the second address bus 24. Is output to the address comparator 12 via. In the address comparator 12, the storage address in the store instruction and the read address in the load instruction are compared, and it is checked whether or not there is a part where the storage address and the read address match.

The positional relationship between the store data storage address A1 in the store instruction and the load data read address A2 in the load instruction is the same as that in FIG. The address is an 8-byte address, as in the first embodiment described above.
As shown in FIG. 3A, when the storage address A1 in the store instruction is 1000 addresses, the data size is 8 bytes, the read address A2 in the load instruction is 1008 addresses, and the data size is 8 bytes, that is, If there is no part that matches the 8-byte address of the store instruction and the 8-byte address of the load instruction, the store instruction and the load instruction have no data dependency relationship with each other, and the store instruction and the load instruction are processed in parallel. ..

On the other hand, as shown in FIG. 3B, the store address A1 of the store instruction is 1000, the data size is 4 bytes, and the read address A2 of the load instruction is 100.
If the address is 0 and the data size is 8 bytes, there is a portion that matches the 8-byte address of the store instruction and the 8-byte address of the load instruction. That is, storage address A1
4 bytes of store data from address 1000 to address 1003 are included as part of the load data from address 1000 to address 1003 of the read address A2.

In this case, the comparison signal line 25 outputs a signal from the comparator 12 indicating the coincidence portion between the storage address in the store instruction and the read address in the load instruction.
Is sent to the data processing unit 5. On the other hand, the data processing unit 5 receives the signal indicating the size of the store data in the store instruction and the signal indicating the size of the load data in the load instruction from the arithmetic processing unit 2 as the first data size. It is inputted via the signal line 21 and the second data size signal line 22. In the data processing unit 5, the data stored in the data cache memory 3 before the execution of the store instruction is stored in the second load instruction data bus 2
Input via 0. Further, the store data from the register file 1 is input to the data processing unit 5 via the bypass data bus 29. The data processing unit 5 analyzes the signal on the comparison signal line 25 and the signals on the first and second data size signal lines 21 and 22, and based on the store data and the data in the data cache memory 3 before executing the store instruction. Then, the load data in the load instruction is generated. That is, of the data from the data cache memory 3 before execution of the store instruction stored at the address A2, the data from the address 1000 to the address 1003 is the data from the address A1 at the address A1 to the address 1003 in the store instruction. And load data to be loaded by the load instruction is generated.

As shown in FIG. 3C, the store address A1 of the store instruction is address 1004, the data size is 4 bytes, and the read address A2 of the load instruction is 100.
If the address 0 and the data size are 8 bytes, of the data from the data cache memory 3 before execution of the store instruction stored in the address A2, the address 1004 to 1
The data up to the address 007 is replaced with the data from the addresses 1004 to 1007 of the address A1 in the store instruction, and the load data to be loaded by the load instruction is generated.

As described above with reference to FIGS. 3B and 3C, the load data generated by the data replacement is the first load instruction in the instruction execution stage E of the load instruction. It is transferred to the register file 1 via the data bus 27 for data.

In this embodiment, when the address comparator 12 detects that there is a coincident portion between the storage address in the store instruction and the read address in the load instruction, the data cache is executed in the store instruction. Based on the data to be stored in the memory 3 and the data read from the data cache memory 3, the load data to the register file 1 in the load instruction is generated in the data processing unit 5, so the store instruction and the load It is possible to process the instruction and the instruction in parallel without providing a stop cycle.

The present embodiment can be similarly applied to an information processing apparatus which processes a store instruction and a plurality of load instructions in parallel.

[0040]

As described above, according to the information processing device of the first aspect of the invention, the address comparator stores the storage address in the store instruction held in the address holding circuit and the read in the load instruction. Based on the data read from the data cache memory and the store data of the data holding circuit that temporarily holds the data to be stored in the data cache memory when it is detected that there is a match with the address. Since the data processing unit for generating the load data to the register file in the load instruction is provided, the store instruction and the load instruction can be pipelined without providing a stop cycle.

According to the information processing apparatus of the second aspect of the invention, when the address comparator detects that there is a coincident portion between the store address in the store instruction and the read address in the load instruction. In addition, a data processing unit that generates load data to the register file in the load instruction based on the store data to be stored in the data cache memory in the store instruction and the data read from the data cache memory , Store instructions and load instructions can be processed in parallel without providing a stop cycle.

As described above, according to the first and second aspects of the present invention, when the data cache hits, the load instruction to be executed next to the store instruction can be processed completely in one clock at a high speed. If the present invention is applied to an electronic computer, especially a superscalar processor, high speed processing can be realized.

[Brief description of drawings]

FIG. 1 is a schematic configuration diagram of an information processing apparatus according to a first embodiment of the present invention.

FIG. 2 is a diagram showing an execution order of each stage of pipeline processing in the first embodiment.

FIG. 3 is a diagram showing a method of generating load data according to the first embodiment.

FIG. 4 is a schematic configuration diagram of an information processing apparatus according to a second embodiment of the present invention.

FIG. 5 is a diagram showing an execution order of each stage of parallel processing in the second embodiment.

FIG. 6 is a schematic configuration diagram of a conventional information processing apparatus.

FIG. 7 is a diagram showing an execution order of each stage of pipeline processing in a conventional information processing apparatus.

[Explanation of symbols]

 1 register file 2 arithmetic processing unit 3 data cache memory 4 data holding circuit 5 data processing unit 11 address holding circuit 12 address comparator

Claims (2)

[Claims] 1. An information processing apparatus capable of pipeline processing a store instruction and a load instruction to be executed next to the store instruction, the arithmetic processing section having a register file, a data cache memory, and the store instruction. A data holding circuit for temporarily holding store data to be read from the register file and stored in the data cache memory based on the above, an address holding circuit for holding a storage address in the store instruction, and the address holding circuit An address comparator for comparing an address held in the address and a read address in the load instruction, a storage address held in the address holding circuit by the address comparator and a read address in the load instruction When it is detected that there is a matching part in the Information comprising a data processing unit for generating load data to the register file in the load instruction based on the stored store data and data read from the data cache memory Processing equipment. 2. An information processing device capable of parallel processing a store instruction and a load instruction to be executed next to the store instruction, the arithmetic processing section having a register file, a data cache memory, and the store instruction. An address comparator that compares a storage address in the load instruction with a read address in the load instruction, and the address comparator has a coincident portion between the storage address in the store instruction and the read address in the load instruction. And a data processing unit that generates load data to the register file in the load instruction based on the store data in the store instruction and the data read from the data cache memory. An information processing device characterized by being provided.