JPH0529359A - Charge coupled device - Google Patents

Abstract

PURPOSE:To prevent a transfer error under an output gate electrode in a charge coupled device having a charge transfer channel that becomes narrower gradu ally in the direction of the output. CONSTITUTION:A charge transfer channel (n-well 14) becomes gradually narrower under several transfer electrodes 10 at ending steps and also under first and second output gate electrodes 11 and 12, but becomes constant under a third gate electrode 13. Under the second output gate electrode 12, the narrow channel effect causes the channel potential to be gradually lower in the direction of the charge transfer, but this lowering trend is cancelled by a fringing field effect under the third output gate 13. Consequently, a faulty transfer of charge can be prevented even when the width of the charge transfer channel is decreased so that the area of a floating diode 15 can be reduced.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a charge-coupled device, and more particularly to a charge-coupled device for detecting signal charges by FDA (floating diffusion amplifier) method.

[0002]

2. Description of the Related Art Of charge-coupled devices (hereinafter referred to as CCDs) used in solid-state image pickup devices (line sensors, area sensors), a CCD connected to its output portion is usually used for high-speed transfer operation. An ion implantation barrier type two-phase drive CCD is used. The configuration and operation of this ion implantation barrier type two-phase drive CCD will be described with reference to the drawings.

FIG. 5 is a schematic plan view showing the vicinity of the output section of a conventional CCD of this type. In the figure, 10 is a plurality of transfer electrodes configured by connecting two adjacent electrodes, 11 is a first output gate electrode, 12 is a second output gate electrode, and 14 is a charge transfer region. A well 15 is a floating diode for charge detection that receives the transfer of the signal charge transferred in the n-well, 16a is a reset gate electrode for periodically resetting the potential of the floating diode 15 to the potential of the reset drain 17, Reference numeral 18 is a MOS transistor whose gate is connected to the floating diode 15 and constitutes an output preamplifier together with the load resistor 19, and 20 is an output terminal of the output preamplifier.

Here, the transfer electrode 10 and the output gate electrode 1
1 and 12 are formed of two-layer polysilicon. Then, the transfer electrodes 10 have two-phase transfer clocks φ ₁ and φ ₂
However, the fixed first output gate voltage V _OG1 is applied to the first output gate electrode 11, the fixed second output gate voltage V _OG2 is applied to the second output gate electrode 12, and the reset gate electrode 16a is applied. Reset pulse φ _R is reset drain 1
A fixed reset drain voltage V _RD is applied to 7.

Next, the operation of transferring the signal charge and detecting the output voltage will be described. FIG. 6 is a sectional view taken along the line AA of FIG. In FIG. 6, 21 is a p-well provided on the n-type semiconductor substrate 22, and 23 is a p-type impurity such as B for giving a potential difference to the transfer channel under the same transfer electrode.
This is a barrier region formed by ion implantation. As shown in the figure, the floating diode 1 for charge detection
5 includes a pn junction between the n well 14 and the p well 21 between the second output gate electrode 12 and the reset gate electrode 16a.

FIG. 7 shows a timing chart of a general drive pulse and potentials of applied constant voltages (V _OG1 , V _OG2 , V _RD ) and FIG. 8 shows a state of charge transfer at each time of FIG. In FIG. 7, V _1H (= V _2H ) and V _1L (= V _2L ) represent high and low potentials of φ ₁ (φ ₂ ), respectively.
V _RH and V _RL indicate the high potential and the low potential of the reset pulse φ _R.

The gate voltage V _OG1 applied to the first output gate electrode 11 is the potential of the charge transfer channel below the first output gate electrode (hereinafter referred to as the channel potential).
v _{OG 1} is higher than the channel potential v _SL of the non-barrier region (hereinafter referred to as storage region) under the transfer electrode when V _2L is applied to the transfer electrode, and under the transfer electrode when V _2H is applied. Is set so as to be lower than the channel potential v _SH of the storage region. Also, the gate voltage V _OG2
Is set so that the channel potential v _OG2 under the second output gate electrode is higher than the channel potential v _OG1 under the first output gate electrode. Furthermore, the reset gate electrode 16
The high potential V _RH of the reset pulse φ _R applied to a is set so that the channel potential v _RH under the reset gate electrode at that time is higher than the constant potential V _RD applied to the reset drain.

As shown in FIG. 8, at time t = t ₁ , the signal charge Q ₁ is accumulated in the storage area below the final transfer electrode 10. This signal charge Q ₁ is at time t =
At t ₂ , the charges pass through under the first and second output gate electrodes 11 and 12 and are injected into the charge detection floating diode 15.

Letting ΔV be the potential change of the floating diode 15 for charge detection at this time, ΔV is C ₁ which is the junction capacitance of the floating diode 15 and C which is the coupling capacitance between the floating diode 15 and the reset gate electrode 16a. ₂ , similarly, the coupling capacitance between the floating diode 15 and the second output gate electrode 12 is C ₃ , and the floating diode 15 to M
The wiring capacitance of the wiring to the OS transistor 18 is C ₄ , MO
The input capacitance of the S transistor 18 can be represented as C ₅ as follows. ΔV = Q ₁ / (C ₁ + C ₂ + C ₃ + C ₄ + C ₅ ) ...

This potential change ΔV is due to the MOS transistor 1
8 and a load resistor 19 are input to an output preamplifier, and the output preamplifier detects it as an output voltage V _OUT . This output voltage V _OUT can be expressed as follows, where R is the resistance value of the load resistor 19 and gm is the mutual conductance of the MOS transistor 18. _{V OUT = ΔV · gm · R} / (1 + gm · R) ..., the _{equation, V OUT = Q 1 · gm} · R / (1 + gm · R) (C 1 + C 2 + C 3 + C 4 + C 5) ... obtained.

As shown in FIG. 8, the signal charge Q ₁ detected as a voltage at t = t ₂ is transferred to the outside through the reset drain 17 by applying V _RH to the reset gate electrode 16a at t = t ₃ . It is discharged, and at the same time, the next signal charge Q ₂ is accumulated in the storage region below the transfer electrode 10 at the final stage. Then, at t = t ₄ , V _RL is applied to the reset gate electrode to return to the state of t = t ₁ . The signal charges Q ₁ , Q ₂ , Q ₃ , ... Are sequentially detected as the output voltage by repeating the series of operations.

As is clear from the equation, in order to obtain as large an output voltage V _OUT as possible with respect to the signal charge Q, C ₁ ~
It is necessary to reduce each capacitance of C ₅ , and for that purpose, it is necessary to make the area of the floating diode 15 as small as possible.

On the other hand, the maximum signal charge amount Q _MAX is determined by the transfer electrode 1
It can be expressed as follows using the potential difference Δv _BS between the channel potential of the barrier region below 0 and the channel potential of the storage region. Q _MAX = K · Δv _BS · W · L Here, K is a proportional constant, W is a charge transfer channel width of the storage region, and L is a charge transfer channel length of the storage region. When this ion implantation barrier type two-phase driving CCD is used as a horizontal transfer portion of a solid-state image sensor, for example, an area sensor, the charge transfer channel length L of the storage region is determined by the size of the solid-state image sensor and the number of horizontal pixels. Further, since Δv _BS cannot be easily changed in relation to the drive voltage (for example, 5 V), it is necessary to increase the charge transfer channel width W of the storage region as much as possible in order to increase Q _MAX .

In consideration of these two points, generally, as shown in FIG. 5, the transfer electrode 10 to the second output gate electrode 1 are connected.
C with a structure in which the width of the charge transfer region is gradually narrowed toward 2
CD is used.

[0015]

However, in the above-described conventional CCD, the width of the charge transfer region is gradually narrowed from the transfer electrode to the second output gate electrode which is the final stage of the output gate electrode. Due to the channel effect, the channel potential gradually decreases, and there is a problem in that a signal charge transfer failure occurs under the second output gate electrode where the effect is most prominent. This situation will be described with reference to the drawings.

FIG. 9 is a diagram showing the relationship between the width of the charge transfer region and the channel potential in the storage region. When the width of the charge transfer region is 10 μm or less, the channel potential is significantly lowered due to the narrow channel effect. Usually, the width of the charge transfer region under the second output gate electrode is 10 to several μm.
It gradually narrows until the
As shown in FIG. 10, the channel potentials are from v _OG2 to v _OG2.
It gradually decreases to _OG2 ′. This difference Δv _OG2 = v _OG2 −v
_OG2 'has a size of about 0.5 to 2V.

Times t ₁ and t ₂ in FIG. 10 are times having the same timing as times t ₁ and t ₂ in FIG.
At time t = t ₁ , the signal charge Q accumulated below the final stage of the transfer electrode 10 passes under the first and second output gate electrodes 11 and 12 and is injected into the floating diode 15 at t = t ₂ . However, at this time, since the channel potential is gradually reduced under the second output gate electrode 12, a certain amount of signal charge ΔQ is left in this portion. Since this charge ΔQ is transferred only by diffusion of electrons, it cannot be completely transferred at a normal drive frequency (several MHz to several tens of MHz) of the transfer clocks φ ₁ and φ ₂ , and here, transfer failure occurs. Occurs.

[0018]

In the charge-coupled device of the present invention, the width of the charge transfer region is gradually narrowed from under the transfer electrode near the output gate electrode to under the output gate electrode. The output gate electrode is divided into a plurality of parts, and the width of the charge transfer region below the final output gate electrode is constant.

[0019]

Since the width of the charge transfer region under the second output gate electrode adjacent to the final output gate electrode from the end is gradually narrowed, its potential tends to be gradually reduced by the narrow channel effect. However, according to the present invention, this potential drop is caused by the fringing field of the final output gate electrode.
The narrow channel effect is substantially diminished as it is compensated by the ld) effect. Therefore, even if the width of the charge transfer region is sufficiently narrowed to reduce the area of the floating diode, the charge transfer failure does not occur.

[0020]

Embodiments of the present invention will now be described with reference to the drawings. FIG. 1 is a schematic plan view of the vicinity of an output section according to the first embodiment of the present invention. In the figure, the same parts as those of the conventional example shown in FIG. 5 are designated by the same reference numerals, and a duplicate description will be omitted. The present embodiment is different from the conventional example of FIG. 5 in that it is made of polysilicon of the first layer, and the width of the charge transfer channel is gradually narrowed from several tens of μm to several μm. Is adjacent to the second output gate electrode 12 having a gradually decreasing voltage, the third output gate electrode 13 made of polysilicon of the second layer and having a constant width of the charge transfer channel is provided on the floating diode 15 side. _Is provided, and a constant third output gate voltage V _OG3 is applied to this electrode.

In the present embodiment, the reset gate electrode 16 is also formed of the second layer of polysilicon so that the area of the floating diode 15 is constant even if the misalignment of the mask occurs. There is.

With the above-described structure, a fringing field generated between the third output gate electrode 13 and the second output gate electrode 12 is generated below the second output gate electrode 12. The decrease in the channel potential present is alleviated, and the transfer failure in this portion is prevented. Here, since the decrease of the channel potential under the second output gate electrode 12 is about 0.5 V to 2 V, the gate voltage V _OG3 is
Accordingly, the gate voltage V _OG2 applied to the second output gate electrode 12 is set sufficiently high within the range where the maximum signal amount of the floating diode is not limited. For example,
The decrease in the channel potential under the second output gate electrode 12 is 1
V, the thickness of the gate oxide film is 1000Å, and the distance (center-to-center) between the second output gate electrode and the third output gate electrode is 2
In the case of μm, V _OG3 is higher than V _OG2 by about 4V.

A state in which the narrow channel effect is eliminated by the edge electric field is shown in FIG. 2A is a sectional view taken along the line AA in FIG. 1, and FIG. 2B is a channel potential diagram in the section. In FIG. 2B, the transfer clock φ
_The solid line represents the channel potential when ₁ is V _1H and φ ₂ is V _2L .
Further, the channel potential when φ ₁ is V _1L and φ ₂ is V _2H is shown by a chain line. The channel potential below the second output gate electrode 12 is generally higher than the channel potential (indicated by a dotted line in the figure) when there is no effect of the edge electric field due to the effect of the edge electric field of the adjacent third output gate electrode 13. In particular, this effect becomes larger as it gets closer to the adjacent third output gate electrode, so that the channel potential gradually increases as a whole in the transfer direction of the signal charge, so that transfer failure does not occur.

FIG. 3 is a schematic plan view of the vicinity of the output section of the second embodiment of the present invention. 4A is a cross-sectional view taken along the line AA, and FIG. 4B is a channel potential diagram on the cross section. This embodiment is different from the first embodiment in that the final transfer electrode 10a is formed of only the second-layer polysilicon, and the first output gate electrode 11a and the third output gate electrode 13a are formed as the first transfer gate electrode 11a. The first layer of polysilicon, the second
The output gate electrode 12a of is the second layer of polysilicon,
This is a point that the reset gate electrodes 16a are each formed of the first-layer polysilicon. As shown in FIG. 4B, this embodiment can also achieve the same effect as the previous embodiment.

By the way, the floating diode 15
The gate electrode of the MOS transistor 18 connected to is usually formed of the first-layer polysilicon. The reason is that the polysilicon of the second layer is more likely to change in size due to variations in etching conditions than the polysilicon of the first layer, and the variation is caused by variations in input capacitance and variations in output voltage. Because it directly affects. Thus, in the case of the present embodiment, in the wiring from the floating diode 15 to the MOS transistor 18, the adjacent third output gate electrode 13a and reset gate electrode 16a are formed of the first-layer polysilicon. Therefore, in order to prevent the coupling capacitance from varying due to the misalignment of the mask between these electrodes, it is preferable to form the first layer of polysilicon. Therefore, in the present embodiment, this wiring and the gate electrode of the MOS transistor 18 can be made common, and the wiring capacitance can be reduced, so that the output voltage can be made larger than in the first embodiment.

[0026]

As described above, according to the present invention, the width of the charge transfer region is gradually narrowed from below the transfer electrode near the output gate electrode to below the output gate electrode. In the charge-coupled device divided into a plurality, the width of the charge transfer region under the final gate electrode of the output gate electrode is made constant, so according to the present invention, adjacent to this electrode, The reduction of the channel potential due to the narrow channel effect that appears under the output gate electrode in which the width of the charge transfer region is gradually narrowed under the same electrode can be eliminated by the fringing field effect of the final output gate electrode. Therefore, according to the present invention, even if the area of the floating diode for charge detection is reduced, defective transfer does not occur, and it is possible to provide a charge coupled device with high sensitivity and high charge transfer efficiency.

[Brief description of drawings]

FIG. 1 is a plan view showing a first embodiment of the present invention.

2 is a cross-sectional view taken along the line AA of FIG. 1 and a channel potential diagram in the cross section.

FIG. 3 is a plan view showing a second embodiment of the present invention.

4 is a cross-sectional view taken along the line AA of FIG. 3 and a channel potential diagram in the cross section.

FIG. 5 is a plan view of a conventional example.

6 is a cross-sectional view taken along the line AA of FIG.

FIG. 7 is a timing chart of drive pulses of a two-phase drive type CCD.

FIG. 8 is a diagram showing a charge transfer state of a conventional example.

FIG. 9 is a diagram showing a relationship between a width of a charge transfer region and a channel potential.

10A and 10B are a cross-sectional view and a channel potential diagram for explaining problems in the conventional example.

[Explanation of symbols]

Reference numeral 10 ... Transfer electrode, 10a ... Final transfer electrode formed only of second layer polysilicon, 11, 11a ... First output gate electrode, 12, 12a ... Second output gate electrode, 13, 13a ... 3 output gate electrodes,
14 ... N-well (charge transfer region), 15 ... Floating diode for charge detection, 16, 16a ... Reset gate electrode, 17 ... Reset drain,
18 ... MOS transistor, 19 ... Load resistance,
20 ... Output terminal, 21 ... P-well, 22 ... N-type semiconductor substrate, 23 ... Barrier region.

Claims (1)

Claim: What is claimed is: 1. A charge transfer region, a charge detection region provided in a subsequent stage of the charge transfer region, a plurality of transfer electrodes provided on the charge transfer region, and the charge transfer region. In a charge-coupled device having a plurality of output gate electrodes provided on the final part of the region, the width of the charge transfer region is gradually narrowed from below the transfer electrode near the output gate electrode to below the output gate electrode, and A charge-coupled device, characterized in that it is made uniform under the final output gate electrode.