JPH05282238A - Information processor - Google Patents

Abstract

PURPOSE:To freely extend a function by allowing the function to have a flexibility, to simplify the circuit constitution of an established extended part, and to shorten the period of a development design by reading attribute information by a main body side device, and operating an access control to the extended part based on the content. CONSTITUTION:An extended part 108 is equipped with a status register 112 whose access timing is constant which stores the attribute information such as the timing. On the other hand, a bus control part 102 is equipped with a control register 117 for freely operating the access control to the extended part 108, and a control circuit which operates the access control to the extended part 108 based on the value of the control register 117. Then, at the time of an initializing processing after a power source is supplied, a CPU 101 reads the storage data of the status register 112, and writes control data matched with the value of the status register 112 in the control register 117 in the bus control part 102, so that the actual access control to the extended part 108 can be freely attained.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an information processing apparatus provided with an expansion section for additionally setting a specific function and a main body side apparatus on which the expansion section is mounted.

More specifically, the present invention relates to an information processing apparatus to which an IC card or expansion board used for a controller of a laser beam printer can be mounted.

[0003]

2. Description of the Related Art In recent years, with the rapid development of semiconductor technology represented by a large-capacity memory or a high-speed 32-bit microprocessor, the development of system products such as small and high-performance personal computers and laser printers has been spurred. Is coming. Among these system products, the controller unit of the laser beam printer has a configuration as shown in FIG. 28.

In FIG. 28, 1 excluding the expansion portion 108a
All the components 01 to 107 are incorporated in the controller section as standard. Here, 101 is the overall control of the printer controller, that is, the host device 10.
9, a CPU that performs communication with the printer mechanism unit 110, the operation panel 111, etc., and generates bitmap image data for outputting print data to the printer mechanism unit 110 based on data output from the host device 109. 10
Reference numeral 2a denotes a CPU 101 and its peripheral memory or control unit 1.
The bus control unit is responsible for timing control of read / write operations with respect to 03-108a and DMA control. Reference numeral 103 denotes an R that stores a code program that describes an operation sequence of the CPU 101 and font data of text characters.
OM and 104 are a page memory for storing one page of bitmap image data and a RAM used as a work area of the CPU 101.

Reference numeral 105 denotes an I / O with the host device 109.
F; RS-232C and Centronics (Centron
ics), control L that controls LAN etc.
Host I / F control consisting of SI and I / F buffer. Reference numeral 106 denotes a control circuit for performing command / status communication with the printer mechanism unit 110 and the printer mechanism unit 1.
The printer control unit includes a synchronizing circuit that outputs bitmap image data in synchronization with a vertical / horizontal synchronizing signal from the line 10, and a line FIFO that stores the image data for one line. 107 is an LED or LC on the operation panel 111
It is a panel control unit that controls the lighting of D and the input control of operation switches. Reference numeral 108a denotes an expansion unit including an IC card or an expansion board, which includes a ROM used to expand font data and the like and a RAM used to expand a data memory.

[0006]

However, the expansion unit 108a shown in the above conventional example is fixedly arranged in the memory space or I / O space of the CPU 101, and the access timing is uniquely determined to control the bus. Part 102
Since it is controlled by a, certain control is applied to the application of the extension unit 108a.

For example, R is used for expanding font data.
This extension section 108a is an IC card composed of OM.
If the above is supported, the timing control of this IC card is predetermined by the bus control unit 102a built in the main body side, so a new IC card using a ROM with a different capacity and access speed will be created at a later date. In some cases, you will be subject to certain restrictions.

When the extension section 108a is made to function as an extension I / O to support SCSI-I / F, LAN, etc., the I / O area to be used is fixedly arranged and access timing control is performed on the bus. Even if the control unit 102a independently performs this, future system expansion will be limited, which is not preferable.

In order to avoid such a problem, there is a method of controlling the timing of the extension section 108a by the extension section 108a itself. In order to carry out this method, a new control circuit for monitoring the address bus signal and the bus control signal output from the CPU 101 and controlling the timing is required independently of the bus control unit 102a. However, if a large number of applications are to be performed by such an extension unit, it is not realistic to individually configure such control circuits according to each application, and such new control circuits are not possible. The extension 10
There is a problem in that the cost of the expansion portion 108a is increased by incorporating it in the 8a.

Therefore, in view of the above points, the object of the present invention is to
It is an object of the present invention to provide an information processing apparatus which is an expansion unit having a simple structure, but which is flexible in its function and can be expanded freely.

[0011]

In order to achieve the above object, the present invention provides an information processing apparatus including an expansion section for additionally setting a specific function and a main body side apparatus to which the expansion section is attached. In the above, the extension unit has means for generating attribute information unique to the extension unit, and the main body side device is
A means for accessing the extension part based on the attribute information is provided.

[0012]

According to the above configuration of the present invention, at the time of initialization processing after the power is turned on, the main body side device can read the attribute information and perform the actual access control to the extension part based on the content.

[0013]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Prior to describing the embodiments of the present invention in detail, the modes for carrying out the present invention will be outlined below.

In the first embodiment of the present invention, there is provided an embedded controller having a communication means for communicating with an external device, a control means for performing a predetermined process based on data obtained from the communication means, and a storage means. , For the embedded controller,
An expansion unit having a storage unit such as a ROM or a RAM and an input / output unit can be added, and an attribute register describing attribute information such as the function and access timing of each unit forming the expansion unit is provided in the expansion unit. Further, a control register and a control circuit for freely (variably) controlling access to the expansion means based on a data value read from the attribute register are provided in the embedded control device.

In other words, a status register having a constant access timing for storing attribute information such as its timing is provided in the extension section, while a control register and a control register for freely controlling the access of the extension section are provided in the control section. A bus control unit including a control circuit that controls access to the expansion unit based on the value of the control register is provided, and the CPU reads the stored data of the status register in initialization processing after power-on, etc. By writing the matching control data to the control register in the bus control unit, the actual access control to the expansion unit can be freely performed.

According to a second embodiment of the present invention, in the above-mentioned embedded control device, in the case where the expansion means has a ROM for controlling the input / output means to be added, in addition to the attribute register. By storing the attribute information of the expansion means in the ROM, the access and operation to the expansion means can be freely (variably) controlled.

That is, in the case where a ROM exists in the extension section in addition to the attribute register, the attribute information of the extension section is stored in the ROM to flexibly cope with extension for various I / O and the like. There is.

In a third embodiment of the present invention, in the above embedded controller, a signal indicating the attribute information is assigned to an interface (connector) signal between the expansion means and the embedded controller. The control circuit in the built-in control device controls access to the expansion means according to the levels of these signals.

That is, by assigning a signal indicating the attribute information to the interface (connector) signal of the extension unit and performing access control of the extension unit in the bus control unit according to the level of these signals, the extension unit is controlled. The access control for is flexible (variable).

Next, embodiments of the present invention will be described in detail with reference to the drawings.

Embodiment 1 FIG. 1 is a block diagram showing the overall configuration of an embodiment of the present invention, that is, the overall configuration of a printer controller. In the figure, 101 is a CPU that controls the printer controller, 102 is a bus control unit that performs bus timing control and DMA control between the CPU 101 and its peripheral memory or I / O control units 103 to 108, and 103.
Is a ROM that stores a program that describes the operation sequence of the CPU 101, character font data, and the like, and 104 is an image memory that stores bitmap image data that is output to the printer mechanism unit 110, and a RAM that is used as a work area of the CPU 101.

Reference numeral 105 denotes an I / F with the host device 109.
(RS-232C, Centronics, LAN, etc.)
A host I / F control unit 106 that controls the image data from the RAM 104 in accordance with a vertical / horizontal synchronization signal from the communication control unit that performs command / status communication with the printer mechanism unit 110 or the printer mechanism unit 110. A printer engine control unit including a print control unit that sequentially reads and outputs to the printer mechanism unit 110, a panel control unit 107 that controls the display of LCDs and LEDs on the operation panel 111, and an input control of operation switches, and a ROM and a RAM 108. Is an expansion unit composed of an IC card or an expansion board as a memory section manager or to support an expansion I / F (hard disk or the like).

In FIG. 1, the expansion unit 108 has an expansion unit status register 112 that describes the attributes of the expansion unit itself and the access timing. The CPU 101 uses the extension status register 11 for initialization after power-on.
By reading 2 from the RO, which constitutes the expansion unit 108,
The configuration of the expansion unit 108 is configured by recognizing the presence or absence of M or RAM, the capacity, and the access timing, and setting the detected attribute or access timing of the expansion unit 108 in the expansion unit control register 117 included in the bus control unit 102. I do.

FIG. 2 is a memory map of the printer controller shown in FIG. As shown in the figure, the ROM portion, the RAM portion, and the I / O portion are allocated from the lower address, and the extension ROM, the extension RAM, the extension status register, and the extension I / O area belong to the extension portion 108. .. The above-mentioned extended status register 112 is a CPU
Memory (or I / O) fixed so that 101 can be accessed without configuration at initialization
It is assigned to an address and the access timing is fixed.

Further, the extension control register 117 is an I / O
It is located at the first address in the area. Here, the allocation of the expansion ROM, the expansion RAM, and the expansion I / O area in the memory space is fixed in the figure, but they can be dynamically arranged.

FIG. 3 is a block diagram showing the internal structure of the expansion section 108 shown in FIG. In the figure, reference numeral 112 is an expansion ROM 113, an expansion RAM 114 and an expansion I / O.
An expansion unit status register that stores the attributes and timing of the 115, and 116 outputs the address to the expansion RAM (DRAM), the row address and the column address.
n) An address multiplexer for dividing the address. The I / F between the expansion unit 108 and the controller unit includes an address bus, a data bus, and signals for controlling the operations of the components 112 to 116.

The control signals shown in FIG. 3 will be described below. / XSRCS and / XIOCS, / XRO
MCS is a chip select signal for the extension status register 112, the extension I / O 115, and the extension ROM 113, respectively. / XMR and / XMW are extended memory units 113 and 114, read and write signals, /
XIOR and / XIOW are expansion I / O units 112 and 11
5 read and write signals. / XRAS, / XCAS, and / CASE are expansion RAM 114, respectively.
Row address strobes and column address strobes, and a column address select signal for the address multiplexer 116. further,
/ XINT, / XREQ, and / XACK are the interrupt request, DMA request, and DM from the extended I / O 115, respectively.
A acknowledge signal.

The output control of the control signals is all output from the bus control unit 102, and the respective bus timings will be described later in the description of the bus control unit 102.

FIG. 4 is a diagram showing the register configuration of the extension part status register 112 in FIG. Each bit of this register is connected to the CPU data bus: D <31 ... 0>. ROM EN (bit 0) and RAM
EN (bit1), IO EN (bit2), DMA
EN (bit 3) indicates whether or not the expansion ROM 113, the expansion RAM 114, and the DMA 115 of the expansion I / O exist, respectively. ROM TM0 (bit4) and ROM TM1 (bit 5) indicates the timing of the expansion ROM 113, here, the number of weights.

The bus timing of the CPU 101 (CPU read and CPU write) is 2 cycles, and the number of waits is 0 when each device can be accessed in 2 cycles, and the number of waits is 1 when 3 cycles are required. ROM SZ0 (bit6) and ROM SZ
1 (bit 7) indicates the size of the expansion ROM 113. here,

[0031]

[Equation 1]

In this case, the size of the expansion ROM 113 is

[0033]

[Equation 2]

It is expressed as follows. Next, RAM TR
D (bit8) and RAM TWR (bit9), R
AM TRF (bit10), RAM TRF (bit
11) shows the read, write, refresh, and row miss timings of the expansion RAM 114. When each bit is 0, there is no wait, and when it is 1, there is one wait.

In this controller, the RAM 104 and the expansion RAM 114 are composed of DRAM,
Normal read and write are in fast page mode (row
When the address is not changed, the bus timing is shortened by using a mode in which access is controlled by the column address and / CAS while / RAS is asserted. In this case, if the address bit corresponding to the row address among the addresses output from the CPU 101 is changed, a cycle for generating a new row address and latching it with / RAS is required. It is called a cycle. Here, both the low-miss cycle and the refresh cycle are 4 cycles without wait.

Next, the RAM SZ0 (bit12) and R
AM SZ1 (bit 13) is a bit indicating the size of the expansion RAM 114, and the value of these signal bits and RA
The relationship with the M size is expressed by the equations (1) and (2) as in the case of the expansion ROM 113. Furthermore, IO FT
0 (bit14) to IO FT3 (bit17) indicates a function as an extended I / O,

[0037]

[Equation 3]

In case of

[0039]

[Equation 4]

I / O configurations are assigned as shown in FIG. In this case, control LS used in each I / O configuration
If I is specified, the timing of each I / O and I / O
Address space, presence / absence of DMA function and timing are FU
It becomes known by the NC code formula (4). Alternatively, by describing the type of LSI to be used and the program in the expansion ROM 113, expandability is facilitated.

FIG. 5 is a diagram showing the internal configuration of the bus control unit 102. In the figure, reference numeral 117 denotes an extension control register which describes the timing of the extension. Also, 118
Is C during a read or write cycle of the CPU 101
The address decoder generates a signal for selecting a device from the address output from the PU 101 and the address strobe signal / AS.

Here, the ROM EN and XROM E
N, RAM EN, XRAM EN, HST EN, P
TR EN, PNL EN, XIO EN, XSR E
N, XCTL EN, REG EN is ROM
103, expansion ROM 113, RAM 104, expansion R
AM 114, host I / F control unit 105, printer engine control unit 106, panel control unit 107, extended I / O 1
15, selection signals for the extension status register 112, the extension control register 118, and other internal registers.

Reference numeral 119 denotes read and write access timing between the CPU 101 and each device, and DM.
It is a timing generator that performs access timing at A time. The input to this timing generator is a selection signal for each device from the address decoder 118, CP
Clock signal CLK from U101, reset signal / R
ST, address strobe signal / AS, bus hold enable signal / HLDA, timing data from extension control register 117, DMA request signal from peripheral device /
REQ0, / REQ1, / XREQ, DMA enable signal ENB from DMA controller 120, DMA mode signal MODE, and further DRAM controller 12
The refresh request signal REF from 1 and the wait request signal RAM are provided, and a control signal for accessing each device is generated based on these control inputs.

The control signal output from the timing generator 119 will be described below.

/ ROMCS and / XROMCS, / H
STCS, / PTRCS, / PNLCS, / XIOC
S and / XSRCS are ROM103 and expanded RO respectively
These are chip select signals of M113, host I / F control unit 105, print engine control unit 106, panel control unit 107, and extension unit status register 112.

/ MR and / MW, / XMR, / XMW
Are read signals and write signals for the ROM 103 and the RAM 104, respectively, and the expansion ROM 113 and the expansion RAM 11.
4 is a read signal and a write signal. / IOR and / IOW, / XIOR, and / XIOW are read signals and write signals for the I / Os 105 to 107 of the controller section, the extension section status register 112 and the extension I / O1.
Read signal and write signal for 15.

/ HOLD is a hold request signal for requesting the CPU 101 to release the address bus and the data bus when DMA requests / REQ0, / REQ1, / XREQ from the peripheral device are generated, and this signal is C
When output to PU 101, CPU 101 outputs / HL
DA is output to release the bus, and DMA execution is started.

/ RDY is the CPU 10 one cycle before the completion of a bus cycle when a bus access for reading or writing is executed from the CPU 101 to a peripheral device.
This signal is output to 1 and by delaying this signal and outputting it, it is possible to generate a wait state and extend the bus cycle.

STA and STB are directed to the DRAM controller 121 by / RAS, / CAS, / XRAS, /
State signal to drive XCAS, RAM /
XRAM- is a selector signal which becomes 1 when the RAM 104 is accessed and becomes 0 when the expansion RAM 105 is accessed.

CNT tells the DMA controller 121
DMA transfer counter and DMA address counter
Is an enable signal for counting. Also, XCT
L WR and REG WR is the extension control register 11
7 and registers within the DMA controller 120.
Signal.

Next, 120 is a DMA controller for controlling data transfer (DMA) between the RAM 104 or expansion RAM 114 and the I / O device without passing through the CPU 101, and internally stores a transfer byte and a transfer destination address. Register, a transfer counter for counting a set number of transfer bytes and a transfer destination address, an address counter, etc., and a count enable signal CNT from the timing generator is turned on (t
At the same time, the transfer counter and the address counter are counted simultaneously with CLK, and after counting the number of transfer bytes, ENB is turned off (false) to terminate the DMA transfer.

Reference numeral 121 designates the RAM 104 and the extended R.
A DRAM controller for controlling the AM 114, including state signals STA, STB, RAM / XRAM
-/ RAS, / XRAS, / CAS, / XCAS are generated and output, as well as control of refresh cycle and low-miss cycle, output of multiplexed address MA <m ... 0> to RAM 104, expansion RAM 114
Address select signal / CASE for
Outputting L.

FIG. 6 shows the inside of the extension control register 117.
1 is a diagram showing the configuration, and the CPU 101 is an extension unit stator.
Read a register and based on the value in that register
Set the value of this register. ROM TM0 (bit
0) and ROM TM1 (bit1) is expansion ROM1
These bits specify 13 timings (number of waits).
It RAM TRD (bit2) and RAM TWR
(Bit3), RAM TRF (bit4), RAM T
RM (bit 5) is for each expansion RAM 114
Read, write, refresh, low miss timing
Is a bit that specifies the
If there is no eight, and 1 is set, one wait state is set.

IO TRD0 (bit6) and IO
TRD1 (bit7) sets the read timing (number of waits) for the extended I / O 115 to IO. TWR0 (bit
8) and IO TWR1 (bit9) is extended I / O1
It is a bit that specifies the write timing (number of waits) for 16. DMA TRD0 (bit10) and DMA TRD1 (bit 11) indicates the read timing (number of waits) of the extension DMA as DMA TWR0
(Bit12) and DMA TWR1 (bit13)
Is a bit that specifies the write timing (number of waits) of the extension DMA.

The read / write timing for these extended I / O and DMA is the extended I / O function IO in the extended section status register 115. FT0-IO
Based on the value of FT3, the CPU 101 discriminates the I / O function and sets it.

Next, the bus timing of the CPU 101 in the timing generator 119 will be described.
FIG. 7 is a state transition diagram for access from the CPU 101 to peripheral devices. In the figure,
IDLE and HOLD, T shown in circle or ellipse
Reference _{numerals 1} , T ₂ and _TW indicate bus states (states), which are an idle (waiting) state, a bus hold state for a DMA cycle, a first state, a second state and a wait state, respectively.

Arrows indicate transitions to other states or repetitions of the same state, and follow the conditional expressions of the signals described in each state (unconditionally, transition to the state of the arrow destination). ..

The operation flow in FIG. 7 will be described below. The bus cycle of the CPU 101 is represented by the bus timing charts shown in FIGS.

FIG. 8 shows the weight or read cycle,
FIG. 9 shows a 1-wait write cycle, and FIG. 10 shows a 2-wait read cycle. In the cycle without weight as shown in FIG. 8, the flow in FIG. 7 is IDLE → T ₁
→ T ₂ → IDLE, but in one wait cycle of FIG. 8, IDLE → T ₁ → T _W → T ₂ → IDLE,
In the 2-weight cycle shown in FIG. 9, IDLE → T ₁ → T _W →
The wait state T _W is inserted between the T ₁ state and the T ₂ state like T _W → T ₂ → IDLE.

In the cycle without wait, the address strobe signal / AS is asserted (/ AS = 0) at the start of the T ₁ state, and the / RDY signal is asserted (/ RDY = 0) in the same state to cause T ₂ However, in one wait cycle, / RDY is not asserted in this T ₁ state (/ RDY = 1).
Therefore, the wait state T _W is automatically inserted in the next state. That is, the bus timing is T ₁ state when there is no wait, and n wait cycles (n ≧
In the case of 1), / RDY is asserted (/ RDY = 0) in the nth wait state.

In FIG. 7, the IDLE state is / AS.
This state also occurs when the RAM 104 and the expansion RAM 114 have a refresh or low-miss cycle other than = 1. Further, the HOLD state is the DMA request from the peripheral device / REQ0 or / REQ1, / X
When REQ is generated, the timing generator is / H
It is generated by a hold acknowledge signal / HLDA which is asserted after OLD is asserted and the CPU 101 completes the bus cycle being executed. This HOLD state transits to the IDLE state when / HLDA is deasserted (/ HLDA = 1) after the DMA processing is completed.

Here, the timing charts of the read cycle and the write cycle of FIGS. 8 and 9 will be described. In the read cycle of FIG. 8, the address A is entered at the start of the T ₁ state.
<31 ... 0> is output, the address strobe signal / AS and the read signal / RD are asserted, and T ₂ is output from the timing generator in the same state by / RDY.
Data bus D at the end of T ₂ state after transition to state
Read the data of <31 ... 0>. A <31 ... 0> and / AS and / RD hold the state until the end of the T ₂ state.

On the other hand, in the write cycle of FIG. 9, A <31 ... 0> and / AS are output at the start of the T ₁ state, and D <31 ... 0 is synchronized with the falling edge of CLK in the same state.
>, The write data is output to the above, and the write signal / WR is output in synchronization with the rising edge of the T ₂ state. Since the timing generator 119 asserts / RDY not in the T ₁ state but in the T _W state to be inserted next, the bus timing becomes the 1 wait state in this case.

FIG. 11 shows the timing generator 119.
It is a figure which shows the internal structure of. In the figure, 122a, 122b and 122c are 3-input NOR and 2-input NOR.
Is. Here, 122a is the ROM control unit 124 in the bus cycle between the CPU 101 and the peripheral device.
And signals ROMRDY, RAMRDY, IORDY output from the RAM controller 125 and the I / O controller 126.
The / RDY signal is generated and output. Reference numerals 122b and 123b denote ROMRD and RAMRD to R output from the ROM control unit 124 and the RAM control unit 125, respectively.
Read signal / MR for OM103 and RAM104
, And extended RO from XROMRD and XRAMRD
Read signal / XM for M113 and expansion RAM114
Generate R. Reference numerals 123a and 123b are inverters, and write signals RAMWR and XRAMW of the RAM 104 and expansion RAM 114 output from the RAM control unit 125.
Generate / MW and / XMW from R and respectively.

Reference numeral 124 is a ROM control unit for controlling the read cycle for the ROM 103 and expansion ROM 113 of the CPU 101. In the ROM control unit 124,
The read timing for the ROM 103 is fixed, but the read timing for the expansion ROM 113 is R
OM TM0 and ROM Control according to TM1.
In the read cycle for ROM103, / ROMC
S and / ROMRD, ROMRDY are output (see FIG. 12), whereas / XROMCS and / XROMRD,
ROMRDY is output (see FIG. 13).

Reference numeral 125 designates the RAM 104 and expansion RAM.
A RAM control unit for controlling read / write to 114, refresh, and row-miss cycle. Again, the timing control for the RAM 104 is fixed, and for the expansion RAM 114, the RAM TRD and RAM TWR, RAM TRF, RAM TRM
Control according to. Cycle to RAM 104 (RAM In EN = 1), RAMRD or RAM
Drive WR, STA, STB, RAMRDY, and
AM / XRAM- = 1.

On the other hand, a cycle (XRAM In EN = 1), XRAMRD or X
RAMWR, STA, STB and RAMRDY are driven, and RAM / XRAM = 0. Where STA is R
Row address strobe signal / R for AM104
Drive / XRAS for AS and expansion RAM 114 (that is, STA is / RAS or an inverted signal of / XRAS) and STB is col for RAM 104.
umn address strobe signal / CAS and expansion RAM1
Drive / XCAS for 14 (ie ST
B is an inverted signal of / CAS or / XCAS).

14 and 15 show the RAM control unit 12
6 is a state transition diagram of FIG. Here, FIG.
Read, write, refresh, and row-miss cycles have no wait. That is, the read and row-miss cycles are composed of 2 states, the write cycle is composed of 3 states, and the refresh cycle is composed of 4 states. The expressions in the ellipse are the state signals STA and ST.
The level of B is shown. In the above four cycles, the start and idle states are RSC = 10 (/ R
AS = 0, / CAS = 1). In the read cycle (page mode), as shown in the timing chart of FIG. 16, the state is RSC = 10 → 11 (→
10).

[0069] In a write cycle (Page Mode), the write data by T ₁ state as shown in the timing of FIG. 17 is output, the next state in / CPUWR is asserted, / CAS of the output T ₂ In this case, one wait state is the minimum cycle in order to assert in the state. Therefore, the state in this case transits to SRC = 10 → 10 → 11 (→ 10).

RAM read / write in this controller is normally / CA with / RAS fixed at Low.
Although S control is performed, a row-miss cycle occurs when the row address changes and in a read or write cycle after the refresh cycle.

FIG. 18 is a timing chart showing a cycle of row-miss + read (page mode). In the T ₁ state, the row address output on A <31 ... 0> and the r address latched in the DRAM controller 127
The values of the ow address are compared and RAMWT is asserted (/ CASEL is deasserted). Then, the new row address is latched by deasserting / RAS in the first T _W state and / RAS in the second T _W state, and the CLK
RAMWT is deasserted at the falling edge of (/ CAS
(EL is asserted) and / RDY is asserted. In the last T ₂ state, / CAS is asserted to read the data. The state in this case is RSC = 10
→ 00 → 10 → 11 (→ 10).

On the other hand, in the low-miss + write cycle,
SRC = 10 → 00 → 10 → 10 → 11 (→ 10).

FIG. 19 shows a refresh cycle, and the state in this case is SRC = 10 (/ RAS =
0, / CAS = 1) → 00 (/ RAS = / CAS = 1)
→ 01 (/ RAS = 0, / CAS = 1) → 11 (/ RA
It changes like S = / CAS = 0) (→ 10). Here, the CAS before RAS refresh cycle is executed. In the refresh cycle, DR
The AM controller 121 asserts RAMWT and REF at the same time, but asserts only RAMWT in a low-miss cycle.

FIG. 20 is a timing chart when a read cycle from the CPU 101 occurs during execution of the refresh cycle. The refresh cycle has four states, but here it is shown that a read cycle occurs in the fourth state. Therefore, T ₁
Up to the state is a refresh cycle, and the next T _{W to} T
The 4 states of the ₂ states become a low-miss + read (page mode) cycle. The state in the figure is SR
C = 10 → 00 → 01 → 11 → 10 → 00 → 10 → 11
It changes to (→ 10).

FIG. 15 shows the STA for the expansion RAM 114.
And STB state transition diagrams. RAM for read, ride, and refresh cycles TRD,
RAM TWR, RAM SR when TRF is 1
Wait one time in the state of C = 11. Also, the low-miss cycle is RAM SRC = 00 when TRM = 1
Wait for 1 state. When one wait state is entered in this way, read and low-miss cycles are executed in three states, write cycles are executed in four states, and refresh cycles are executed in five states.

Reference numeral 126 shown in FIG. 11 is a host I / F system.
Control unit 105, printer engine control unit 106, panel system
Access to the control section 107, extended I / O 115, etc.
It is an I / O control unit for controlling the operation. This I / O control unit 1
26 fixed all I / O except extended I / O 115
Control at the timing when the expansion I / O 115
For IO TRD0 and IO I / O by TRD1
IO cycle TWR0 and IO By TWR1
The I / O write cycle can be variably controlled.

/ HSTCS and / PTRCS, / PN
LCS is a chip select signal to the host I / F control unit 105, printer engine control unit 106, and panel control unit 107, respectively, and when accessing these I / O units, I / O read signal / IOR or I / O. The write signal / IOW is driven. Also, with / XIOCS
XSRCS is a chip select signal to the expansion I / O 115 and the expansion unit status register.
/ O as read or write signal / XIRO, / X
Drive IOW.

Furthermore, XCTL WR and REG WR
Are write signals for the extension control register 117 and other internal I / O registers. The I / O control unit 126 uses the CP
IO in the state before the T ₂ state when executing a bus cycle from U101 RDY is asserted and / RDY from the RDY generator 123 is asserted.

21 and 22 respectively show the CPU 1
It is a timing diagram which shows the bus cycle of I / O read from 01 and I / O write. Here, FIG. 21 shows the host I
The read cycle (1 wait state) for the / F control unit 105 is shown. On the other hand, FIG. 22 shows an example of a write cycle (4 wait states) for the extended I / O 115. In this case, IO TWR0 and IO TW
Both R1 are 1.

Reference numeral 127 shown in FIG. 11 indicates an extended I / O 11
I / O unit including 5 and RAM 104 or expansion RAM
A DMA control unit that controls the timing of direct data transfer (DMA) with 114. This is / REQ0
And / REQ1 from the controller I / O, / X
REQ is a DMA request signal from the extended I / O 115, and outputs DMA acknowledge signals / ACK0, / ACK1, / XACK to these inputs, respectively. In addition, these input signals are used for the DMA transfer by the CPU1.
01 to request bus hold request signal / HOLD
Is asserted until the end of the DMA transfer.

The CPU 101 asserts the bus hold acknowledge signal / HDLA to the / HOLD input to give the DMA controller 127 and the DMA controller 120 the right to use the bus, and the DMA transfer is started. The DMA controller 127 includes a DMA controller 120.
A count enable signal is output to the DMA controller 120 to cause the DMA controller 120 to count the data transfer counter and the address counter. On the other hand, when the data transfer counter counts a preset number of transfer bytes, the DMA controller 120 outputs the DMA enable signal. F ENB
and the DMA transfer is completed.

The DMA controller 127 receives the DMA read (I /
Data transfer from O to RAM), the RAM control unit 12
RAM for 5 WR or XRAM The WR is driven, and the I / O control unit 126 is driven to drive / IOR or / XIOR. On the other hand, at the time of DMA write (data transfer from RAM to I / O), the RAM is sent to the RAM controller 125. RD or XRAM RD
Drive the I / O controller 126 to / IOW
Alternatively, drive / XIOW.

FIG. 23 is a state transition diagram for the DMA read cycle and the DMA write cycle of the DMA control unit 127. 24 and 25 are timing charts of the DMA read cycle and the DMA write cycle, respectively. When there is no wait, the DMA read cycle requires 5 states and the DMA write cycle requires 4 states.
In the state transition diagram shown in FIG. 23, expressions in the ellipse, T ₁ through T ₄ is T ₁ through T _5, DMA write cycle is in each state (DMA read cycle timing diagram shown in FIG. 24 and FIG. 25 ) Describing state: DST
= [ACK, IOR, IOW, CAS, MR, MW].

In the DMA read cycle, as shown in FIG. 24, / ACK is sent in the T ₂ state and / ACK is sent in the T ₃ state.
IOR is asserted to read from the I / O block, and T
Writes to the RAM by asserting / MW in ₄ states and / CAS in T ₅ state. The state in this case is DST = 000000 → 100000 → 11000
It changes in the order of 0 → 110001 → 110101 (→ 000000).

On the other hand, in the DMA write cycle, as shown in FIG. 25, / ACK and / MR are set to T ₃ in the T ₂ state.
In the state, / CAS is asserted to read from the RAM section, and in the T ₄ state, / IOW write is asserted to write to the I / O section. The state in this case is D
ST = 000000 → 100010 → 101110 (→
000000).

For the extended I / O 115, DM
A TRD0 and DMA The number of DMA read cycle waits is TWR0 and DMA T
The number of waits for the DMA write cycle can be designated by WR1. Therefore, in the DMA read cycle, DST
= 110000, DST = in the DMA write cycle
A wait state occurs at 101110.

The wait state for the RAM section
Is the RAM to the RAM control unit 125 TRD and RAM TW
Determined by R, DST = in DMA read cycle
110101, DST = 1 in DMA write cycle
A wait state occurs at 00110.

As described above, R
When the OM, RAM, and I / O are expanded, the expansion unit 108
In contrast, an extension unit state register 112 in which the attributes and timing information of the extension unit 108 itself are described is provided, and in the initialization processing such as when the power is turned on, the CPU 10
1 reads the extension status register and sets data in the extension control register 117 in the bus control unit 102 so as to match the information, whereby the extension section 10
Flexible response to 8 is possible.

Second Embodiment FIG. 26 is a diagram showing the internal structure of the extension status register 12 as the second embodiment of the present invention. As shown in FIG. 4A (first embodiment), bits 0 to 3 in FIG. EN and RAM EN, IO
EN, DMA EN is fixedly assigned.
ROM in bit4 INF is newly assigned. This bit 4 is used when the expansion ROM 113 exists (ROM This bit can be set only to EN = 1) and is a bit indicating whether or not to store in the expansion RAM 114 or the expansion ROM 113. When INF is 1, ROM as shown in FIG. TM0 (bit5) and R
OM Only TM1 (bit 6) needs to be added, and the register can be configured with a small number of bits.

On the other hand, ROM When INF is 0,
In (b) of 6, it is necessary to describe such information in bits of bit 7 and above (ROM INF is ROM
If EN is 0, it must be 0).

When the expansion ROM 113 does not exist, for example, when only the expansion RAM 114 exists (RAM E
N = 1) has bits 5 to 8 as shown in (c) of FIG.
Timing information RAM TRD, RAM TWR, R
AM TRF, RAM Size information RAM for TRM in bits 9-10 SZ0, RAM Describe SZ1.

When various I / Os are to be associated with the expansion unit 108, the program for controlling the expansion I / O 115 is generally the expansion ROM 1 in the expansion unit 108.
It is desirable to describe in 13, and I / O expansion can be flexibly performed. In this case, as shown in FIG. 27, the internal structure of the expansion ROM 113 is such that the attribute information of the expansion unit 108 itself from the lowest address, that is, the ROM size, RA
It consists of a management area in which M timing, size, I / O functions, etc. are described and a program area.

The timing control for each device of the expansion unit 108 is performed by the bus control unit 10 as in the first embodiment.
It is performed only by setting the data in the extended control register 117 in the second item.

Embodiment 3 As the third embodiment of the present invention, the configuration described below can be adopted.

That is, for a small-scale controller whose use is limited, the attribute information is directly displayed on the interface (connector) of the extension section without providing a status register describing the attribute in the extension section. By allocating signals and performing access control of the expansion unit in the bus control unit according to the levels of these signals, the access control of the expansion unit can be made flexible (variable).

As described above, in the interface and control method of the expansion unit such as the expansion board or IC card to be expanded by the controller of the page printer, the attribute and timing information of the expansion unit itself are described in the expansion unit. It should be added by providing a status register with constant access timing, a control register that can variably specify access control of the expansion unit in the controller unit, and a control unit that controls the expansion unit based on the setting value of this control register. It is possible to reduce the cost by simplifying the circuit configuration of the expansion section and to shorten the development and design period.

When the extension section has various I / O means and a ROM for controlling the I / O means, the attribute information is written not only in the status register of the extension section but also in this ROM. The extension will be able to support a wider range of applications.

Furthermore, when the application is limited to a small scale, the attribute information of the extension unit itself can be assigned to the interface (connector) of the extension unit, and the access control for the attribute information can be made variable.

[0099]

As described above, according to the present invention, at the time of initialization processing after the power is turned on, the main body side device reads the attribute information, and based on the contents, actual access control to the extension part is performed. Since it is possible to reduce the cost by simplifying the circuit configuration of the expansion unit to be added, it is possible to shorten the development and design.

Further, according to the present invention, a wider range of applications can be supported by the extension section.

[Brief description of drawings]

FIG. 1 is a block diagram of a printer controller showing the overall configuration of the present invention.

FIG. 2 is a memory map diagram of the present embodiment.

FIG. 3 is a block diagram of an extension unit.

FIG. 4 is a configuration diagram of an extension status register.

FIG. 5 is a block diagram of a bus control unit.

FIG. 6 is a configuration diagram of an extension control register.

FIG. 7 is a state transition diagram of the timing generator for the bus cycle of the CPU.

FIG. 8 is a timing chart showing a CPU read cycle (without wait).

FIG. 9 is a timing chart showing a write cycle (1 wait state) of the CPU.

FIG. 10 is a timing chart showing a read cycle (2 wait states) of the CPU.

FIG. 11 is a block diagram of a timing generator.

FIG. 12 is a timing diagram showing a read cycle for the ROM of the CPU.

FIG. 13 is a timing chart showing a read cycle (2 wait states) for the expansion ROM of the CPU.

FIG. 14 is a state transition diagram for a RAM unit (RAM, extended RAM).

FIG. 15 is a state transition diagram for the RAM section (when there is a wait state).

FIG. 16 is a timing diagram showing a CPU read cycle for the RAM section.

FIG. 17 is a timing diagram showing a CPU write cycle for the RAM section.

FIG. 18 is a timing diagram showing a row miss + read cycle for the RAM section.

FIG. 19 is a diagram showing a refresh cycle of a RAM section.

FIG. 20 is a timing diagram showing a RAM section refresh + CPU read cycle.

FIG. 21 is a timing diagram showing a CPU read cycle for the I / O unit.

FIG. 22 is a timing diagram showing a CPU write cycle for the I / O unit.

FIG. 23 is a state transition diagram at the time of DMA transfer.

FIG. 24 is a timing diagram showing a DMA read cycle.

FIG. 25 is a timing diagram showing a DMA write cycle.

26 (a), (b) and (c) are configuration diagrams of an extension status register in the second embodiment of the present invention.

FIG. 27 is a memory map diagram in the extended TOM.

FIG. 28 is a block diagram of a printer controller in a conventional example.

[Explanation of symbols]

 101 CPU 102, 102a Bus control unit 103 ROM 104 RAM 105 Host I / F control unit 106 Printer engine control unit 107 Panel control unit 108, 108a Expansion unit 109 Host device 110 Printer engine 111 Operation panel 112 Expansion unit status register 113 Expansion ROM 114 Expansion RAM 115 Expansion I / O 116 Address Multiplexer 117 Expansion Unit Control Register 118 Address Decoder 119 Timing Generator 120 DMA Controller 121 DRMA Controller 122a 3 Input NOR 122b, 122c 2 Input NOR 123a, 123b Inverter 124 ROM Controller 125 RAM Controller 126 I / O control unit 127 DMA control unit

Claims (1)

[Claims] 1. An information processing apparatus comprising: an expansion unit for additionally setting a specific function; and a main body side device to which the expansion unit is attached, wherein the expansion unit is provided with attribute information unique to the expansion unit. An information processing apparatus, comprising: a means for causing the main body side apparatus to include means for accessing the extension section based on the attribute information.