JPH05197360A - Image processing system and method therefor - Google Patents

Abstract

PURPOSE:To control the hierarchizing display of plural windows at a high speed. CONSTITUTION:Output image data memory 8 is provided with words equivalent to the number of picture elements constituting an output image, and pixel data for expressing the color of the picture element is stored in it. Output image control data memory 10 is provided with the words equivalent to the number of picture elements constituting the output image, and information required for control is stored in it, and it is composed of a RAM with fast access speed. An output image memory control part 12 performs the read/write control of the pixel data and the discharge control of the pixel data from a periodical serial port on the output image data memory 8, and the read/write control of control data on the output image control data memory 10, etc. A pixel data write decision part 19 decides whether or not the write of the pixel data on the output image data memory 8 is permitted based on designation information at every picture element read out on to an output image control data bus 11 and representing whether or not the write should be permitted.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention comprises an image processing system equipped with a multi-window system for displaying a plurality of images on an image display device in a divided manner, and particularly for high-speed drawing and multi-window display of moving images. And its method.

[0002]

2. Description of the Related Art In recent years, a multi-window system has been widely used in personal computers and workstations, and a plurality of application programs on the multi-window system can be displayed on a screen of an image display device. A dedicated display area is provided. Furthermore, the application program is an operation system (hereinafter referred to as O
It is possible to open or close a plurality of display areas "windows" by opening / closing a file or starting / terminating a process by making a predetermined request to S).

In a typical multi-window system, the window currently interfacing with the user operating the system is treated as the active window and is positioned at the top of the windows on the screen. Will be displayed. Therefore active
The entire display area of the window is visible. Then, in some windows other than the active window, a part of the display area may be hidden by another window. Further, the OS of the multi-window system controls the overlapping display (hierarchical display) of windows in addition to the basic control of opening / closing of windows.

Most of the personal computers and work stations equipped with the multi-window system carry out screen display on the image display device with one output image memory in the bit map format. The exclusive display control of the hidden portion is generally performed mainly by the OS of the multi-window system.

[0005]

However, when the hierarchical display of a plurality of windows is controlled as in the above-mentioned multi-window system, high-speed image development, especially display of moving images in windows is performed. Then, there is a problem that user's satisfaction cannot be obtained in terms of display speed.

[0006]

The present invention has been made for the purpose of solving the above-mentioned problems, and has the following constitution as one means for solving the above-mentioned problems. That is,
The invention according to claim 1 is provided with a memory for dividing and displaying a plurality of image information from a plurality of independent input image signal sources on a single screen, and a part of the image information in the divided display, Alternatively, in an image processing system that performs divided display such that all of the information overlaps with other image information, in accordance with the divided display configuration of the image information on the screen, information indicating the correspondence between the divided display configuration and the input image signal source is created. 1. The information creating means of No. 1, the control means for controlling the output of the image information from the input image signal source according to the information, and the divided display configuration of the image information on the screen, based on the divided display image to the memory. Second information creating means for creating information writing instruction information, and image information output under the control of the control means, according to the instruction information created by the second information creating means, And means for deploying on Li.

Preferably, the writing instruction information of the image information by the second information creating means includes the correspondence information between the specific information of each pixel forming the image information and the specific element forming the memory. Further, the invention according to claim 4 is provided with a display memory for dividing and displaying a plurality of image information from a plurality of independent input image signal sources on a single screen so that the plurality of image information are overlapped. In an image processing system for performing various displays, first information creating means for creating information indicating the correspondence between the divided display structure and the input image signal source according to the divided display structure of image information on the screen, and the information Based on the control means for controlling the output of the image information from the input image signal source, the divided display configuration of the image information on the screen, the specific information of each pixel constituting the image information, and the display memory Second information creating means for creating write instruction information of image information including correspondence with a specific element constituting the image information, and image information output by control by the control means is created by the second information creating means. It Instruction information to slave connexion with, and means to expand the display memory.

According to the sixth aspect of the invention, since a plurality of image information from a plurality of independent input image signal sources are displayed on a single screen, the image information overlaps with other image information. In the image processing method for performing such a display, according to the display configuration of the image information on the screen, a first information creating step of creating information indicating the correspondence between the display configuration and the input image signal source, and according to the information A control step of controlling output of image information from an input image signal source, and a second information creating step of creating instruction information for writing the image information in a memory based on a display configuration of the image information on a screen And a step of expanding the image information output under the control of the control step on the memory according to the instruction information created in the second information creating step.

[0009]

With the above structure, the function of controlling the hierarchical display of a plurality of windows at high speed is achieved.

[0010]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Preferred embodiments of the present invention will be described in detail below with reference to the accompanying drawings. FIG. 1 is a block diagram showing the overall configuration of an image processing system (hereinafter referred to as a system) according to an embodiment of the present invention. In the figure, the CPU
Reference numeral 1 denotes a processor that executes a predetermined process according to a program, is a control center of the present system, and is a main controller that controls the entire system. The DMA controller 2 performs periodic data transfer of pixel data from an input image signal processing unit 7 described later to an output image data memory 8. The CPU 1 and the DMA controller 2 or the input image signal processing unit 7 are connected via a CPU address bus 3 and a CPU data bus 4. The CPU control bus 5 is the CPU 1 or DM.
It handles signals such as a signal indicating the start or end of bus access by the A controller 2 and a read / write identification signal.

The input image signal line 6 is a video signal from a video camera or the like (not shown), specifically, the input image red,
An analog signal representing each of the green and blue pigment components and a sync signal are handled. The input image signal processing unit 7 is composed of, for example, an A / D converter, a low pass filter, an input image memory, an input image memory control unit, an image enlarging / reducing conversion unit, etc., and via the input image signal line 6. The input image sent in as a digital data is taken into the input image memory, and the pixel data converted and generated at an arbitrary enlargement / reduction ratio in an arbitrary cutout range of the input image is ordered in accordance with an instruction from the CPU 1. It has the function of discharging to. In the present embodiment, the number of input image signal sources is four, and therefore four sets of the input image signal line 6 and the input image signal processing unit 7 are provided. Hereinafter, these four input image signal lines 6 are referred to as 6a, 6b, 6c and 6d, respectively, and the corresponding input image signal processing units 7 are referred to as 7a, 7b and 7 respectively.
c and 7d.

The output image data memory 8 is a memory for editing an output image for an image display device (not shown). The output image data memory 8 has the number of words corresponding to the number of pixels forming the output image on the display device, and one word on the memory corresponding to each pixel is expanded on the screen of the display device. Pixel data for expressing the color of a pixel is stored. In this system, since the pixel data is represented by 24 bits (8 bits for each of red, green, and blue pigment components), the output image data memory 8 has a word width of 24 bits. The output image data memory 8 is composed of a dual port (random port + serial port) DRAM that is often used as a video frame memory. Of these, the random port side is connected to the CPU data bus 4 and enables random writing of pixel data to arbitrary pixel positions on the output screen. On the other hand, the serial port side is connected to a display device synchronizing section 16 which will be described later, and enables periodic and regular high-speed discharge of pixel data to the display device. And output image data bus 9
In the output image data memory 8, pixel data having a width of 24 bits is sequentially discharged from the serial port of the output image data memory 8.

The output image control data memory 10 has a number of words corresponding to the number of pixels forming the output image on the display device, like the output image data memory 8, and the number of words in the memory corresponding to each pixel is 1. The word stores information necessary for the target control, and has a word width capable of expressing the control information. In this embodiment, since the designation information for each pixel indicating whether or not the writing of the pixel data is permitted is stored, the output image control data memory 10
Has a word width of "4 bits" equal to "4" which is the number of input image signal sources. The output image control data memory 10 is composed of a RAM having an access speed higher than that of the output image data memory 8. The output image control data bus 11 is a data input / output bus of the output image control data memory 10.

The output image memory controller 12 controls writing / reading of pixel data from the random port to the output image data memory 8 and discharges pixel data from the serial port to the output image data memory 8 periodically. Control, write / read control of control data to / from the output image control data memory 10, and write control of pixel data to the output image data memory according to the state of the pixel data write permission signal 20. Further, the output image data memory address bus 13 carries address information for the output image data memory 8, and the output image memory control unit 12 generates this address information.

The output image data / memory control bus 14 is
Handles output image data, address strobe signals for memory 8, write / read strobe signals, etc.
The output image memory control unit 12 generates all the signals on the control bus 14. Further, the output image control data / memory control bus 15 handles a chip enable signal, a write / read strobe signal, etc. for the output image control data memory 10, and the signals on this control bus 15 also
All are generated by the output image memory control unit 12.

The display device synchronizing section 16 applies, for example, to a CRT to the pixel data discharged onto the output image data bus 9.
It has a function of superimposing a synchronization signal on an image display device such as a monitor, and is specifically composed of a D / A converter, a synchronization signal generation circuit, an analog calculator, and the like. Further, the output image signal line 17 includes a video signal output from the display device synchronization unit 16, specifically, an analog signal representing each red, green, and blue pigment component of the output image, and a synchronization signal. It is connected to an image display device (not shown) such as a CRT monitor.

The display device synchronizing signal 18 is output from the display device synchronizing section 16 and is composed of signals such as a vertical synchronizing signal, a horizontal synchronizing signal, a blanking signal and a dot clock. The output image memory control section 12 periodically controls the discharge of the pixel data from the serial port to the output image data memory 8 based on the display device synchronizing signal 18.

In the pixel data write determination unit 19, the pixels to be output to the output image data memory 8 are read based on the designation information read out onto the output image control data bus 11 for each pixel whether writing is permitted or not. It is determined whether data writing is permitted. Further, the pixel data write permission signal 20 becomes active when the pixel data write determination unit 19 determines that the writing of the pixel data to the output image data memory 8 is permitted. The pixel data write permission signal 20 is input to the output image memory control unit 12.

FIG. 2 is a diagram showing a bit format of data discharged from the CPU 1 shown in FIG. 1 or the input image signal processing unit 7 onto the CPU data bus 4. As shown in the figure, pixel data for expressing the color of each pixel is arranged in the lower 24 bits of the same data, and in the bits 29 to 28, the above-mentioned four input image signal processing units (7a) are arranged. , 7b, 7c, 7d), an identifier encoded with 2 bits is stored. Further, in the bit 31, a flag bit for identifying whether the data discharged onto the CPU data bus 4 is from the CPU 1 or the input image signal processing unit 7 is arranged. In the example shown in FIG. 2, since the bit 31 is set to “1”, this indicates that this data is the data read from the input image signal processing unit 7.

FIG. 3 shows the output image control data memory 10
The bit format of the control data stored in the control data and the control data on the output image control data bus 11 is represented by 4 bits, and each of the 4 bits has the above-mentioned four input image signal processing units (7a, 7b, 7c, 7d). When this bit is "0", it means that writing of the pixel data discharged from the corresponding input image signal processing unit 7 is prohibited for the pixel (word), and the bit is "1". The case indicates that writing is permitted. Needless to say, when all 4 bits are "1", writing of pixel data from any of the input image signal processing units (7a, 7b, 7c, 7d) is permitted for that pixel (word). It means that. On the other hand, when all of the 4 bits are “0”, the writing of the pixel data from any of the input image signal processing units (7a, 7b, 7c, 7d) to the pixel (word) does not cause the pixel (word). It means that it is prohibited to.

FIG. 4 is a diagram showing a bit format of data read from the output image data memory 8 and the output image control data memory 10 by the CPU 1 through the CPU data bus 4. As shown in the figure,
Pixel data stored in the output image data memory 8 is arranged in the lower 24 bits of the data, and bit 27
Output image control data memory 1 in 4 bits of
The control data stored in 0 are arranged respectively. The bit format of the control data arranged in these 4 bits 27 to 24 is the same as that shown in FIG.

FIG. 5 is a diagram showing the bit format of the data discharged onto the CPU data bus 4 when the CPU 1 writes the pixel data in the output image data memory 8, and the lower 24 bits thereof are Pixel data to be stored in the output image data memory 8 is arranged. Further, in the bit 31, a flag bit for identifying whether the data discharged onto the CPU data bus 4 is from the CPU 1 or the input image signal processing unit 7 is arranged. In the example shown in the figure, “0” is set in the bit 31, indicating that the data is the data discharged by the CPU 1. In the bit 30, a flag bit for identifying the write mode for the output image data memory 8 or the write mode for the output image control data memory 10 is arranged. In the figure, "1" is set in the bit 30 to indicate that it is in the writing mode of the pixel data to the output image data memory 8.

FIG. 6 shows that when the CPU 1 writes control data in the output image control data memory 10.
FIG. 6 is a diagram showing a bit format of data to be discharged onto a CPU data bus 4. In the figure, bit 2
Control data to be written in the output image control data memory 10 is arranged in 4 bits 7 to 24. Further, in the bit 31, a flag bit for identifying whether the data discharged onto the CPU data bus 4 is from the CPU 1 or the input image signal processing unit 7 is arranged. In the case of the figure, "0" is set in the bit 31, and C
It indicates that the data is the data discharged by PU1. A flag bit for identifying the writing mode to the output image data memory 8 or the writing mode to the output image control data memory 10 is arranged in the bit 30. Here, "0" is set in the bit 30. Therefore, it is indicated that the mode is the control data writing mode to the output image control data memory 10.

FIG. 7 is a diagram showing an example of split display on the screen of the image display device (not shown) in the system according to the embodiment of the present invention. In the figure, the display areas a and a ′ form a window Wa, and the output image generated by the input image signal processing unit 7a in FIG. 1 is displayed. On the other hand, the portion of the display area b is the window Wb, and the output image generated by the input image signal processing unit 7b is displayed. Further, the display area g is a background screen, and an image pattern based on pixel data written in advance by the CPU 1 is displayed.

In the example shown here, the active window is the window Wa, and the display area of the window Wa is entirely visible. On the other hand, in the window Wb, the lower right part of the display area is the window Wb.
It is hidden by a. That is, in the figure, the display area a '
The portion of is a portion of the window Wa that overlaps the window Wb.

FIG. 8 is a diagram showing the contents of the output image control data memory 10 corresponding to each of the four display areas (a, a ', b, g) in the divided display example shown in FIG. Here, the display area g corresponds to the background screen, and any of the input image signal processing units (7a, 7b, 7)
The writing of pixel data from c, 7d) is also not permitted. Therefore, the output image control data memory 1
In the content of 0, all 4 bits are “0”. The display area a is a portion in which the output image generated by the input image signal processing unit 7a is displayed, and only writing of pixel data from the input image processing unit 7a is permitted. Therefore, the content of the output image control data memory 10 is the bit (bit 0) corresponding to the input image processing unit 7a.
Only "1" is "0001".

The display area b is a portion where the output image generated by the input image signal processing section 7b is displayed.
Only writing of pixel data from the input image processing unit 7b is permitted. Therefore, the output image control data memory 10
The content of is only "0010" of "1" only for the bit (bit 1) corresponding to the input image processing unit 7b. The display area a'is a portion in which the output image generated by the input image signal processing unit 7a is displayed in an overlapping manner with the output image generated by the input image signal processing unit 7b, and as a result, Only writing of pixel data from the input image processing unit 7a is permitted. Therefore, the contents of the output image control data memory 10 are similar to those of the display area a, and the input image processing unit 7
Only the bit corresponding to a is "0001" of "1".

FIG. 9 is a diagram showing another example of divided display on the screen of the image display device in the system according to the embodiment of the present invention. In the figure, the display area a part constitutes a window Wa, and the output image generated by the input image signal processing unit 7a is displayed. On the other hand, the display areas a ′ and b are windows Wb, and the output image generated by the input image signal processing unit 7b is displayed. Further, the display area g is the background screen,
1, the image pattern based on the pixel data written in advance is displayed.

In this example, the active window is the window Wb, and the display area of the window Wb is entirely visible. On the other hand, the upper left portion of the display area of the window Wa is hidden by the window Wb. That is, the display area a ′ is a portion of the window Wb that overlaps the window Wa.

FIG. 10 shows the contents of the output image control data memory 10 corresponding to each of the four display areas (a, a ', b, g) in the divided display example shown in FIG. The only difference from the divided display example shown in FIG. 8 is the display area a ′. The display area a ′ is a portion in which the output image generated by the input image signal processing unit 7b is displayed so as to overlap with the output image generated by the input image signal processing unit 7a, and as a result, the input image is displayed. Only writing of pixel data from the processing unit 7b is allowed. Therefore, the content of the output image control data memory 10 is "0010" of "1" only in the bit corresponding to the input image signal processing unit 7b, as in the display area b.

Next, control in the image processing system according to the embodiment of the present invention will be described. FIG. 11 shows the CPU 1 and DM in the image processing system according to the embodiment of the present invention.
3 is a flow chart showing a control procedure in the A controller 2. Incidentally, here, the control procedure is stored in the memory 1a in the CPU 1 and executed, but this procedure may be stored in another memory. Further, an example will be described in which after executing the split display on the screen of the image display apparatus shown in FIG. 7, the execution shifts to the split display on the screen of the image display apparatus shown in FIG.

In step S1 of FIG. 11, CPU1
In order to realize the window structure shown in FIG. 7, as shown in FIG. 8, 4-bit control data different for each display area is output image control data corresponding to all the pixels forming the output image. Write to all words on memory 10. CPU when writing this control data
The format of the data that 1 ejects onto the CPU data bus 4 is that shown in FIG.

That is, as shown in FIG. 6, among the data output by the CPU 1, the control data to be written in the output image control data memory 10 is set in 4 bits of bits 27 to 24. Bit 31 is the CPU as described above
Since this is a flag bit for identifying whether the data discharged onto the data bus 4 is from the CPU 1 or the input image signal processing unit 7, in this case, "0" is set in the bit 31, This indicates that the data has been discharged by the CPU 1. Further, since the bit 30 is a flag bit for identifying the write mode for the output image data memory 8 or the write mode for the output image control data memory 10, "0" is set in the bit 30 here. Then, it is indicated that the control mode is the mode for writing the control data to the output image control data memory 10.

As a result, the CPU 1 determines whether each of the four input image signal processing units (7a, 7b, 7c, 7d) is allowed to write the pixel data in the output image data memory 8. It is specified for each pixel forming the output image, that is, for each word in the output image data memory 8. In step S2, the CPU 1 writes the pixel data to display the background screen pattern in the word on the output image data memory 8 corresponding to the portion of the display area g in FIG. When writing the pixel data of this background screen pattern, C
The format of the data that PU1 ejects onto CPU data bus 4 is that shown in FIG.

As shown in FIG. 5, pixel data to be written in the output image data memory 8 is set in the lower 24 bits of the data output by the CPU 1. Further, as described above, the bit 31 is a flag bit for identifying whether the data discharged onto the CPU data bus 4 is from the CPU 1 or the input image signal processing unit 7, and in this case, , Bit 31 is set to "0" and CP
It shows that U1 is the discharged data. Bit 30
Is a mode for writing to the output image data memory 8 or
This is a flag bit for identifying the output image control data memory 10 write mode. In this case,
Set "1" in bit 30 to output the image data.
This shows the mode for writing pixel data into the memory 8.

In step S1, the CPU 1 sets the contents of the output image control data memory 10 to "0" for all 4 bits, so that any input image signal processing unit (7a, 7b, 7c, 7d). The pixel data generated in () cannot be written in the display area g. Therefore, the background screen pattern once written in the display area g by the CPU 1 in step S2 is as shown in FIG.
Unless the window structure shown in FIG. 3 is changed, the window structure is stored in the output image data memory 8 and continues to be displayed on the screen of the image display device.

Next, in step S3, the CPU 1 displays the initial screen pattern in the word on the output image data memory 8 corresponding to the display areas a and a'constituting the window Wa in FIG. Therefore, "black" pixel data (24-bit all "0" pattern) is written. When the pixel data of the initial screen pattern of this window Wa is written, the CPU 1
The format of the data discharged onto the data bus 4 is
It is shown in FIG.

The display areas a and a'are generated by the input image signal processing section 7a because the contents of the output image control data memory 10 are set to "0001" by the CPU 1 in step S1. Only the pixel data that has been written can be written in the display areas a and a ′. However, when writing the pixel data of the initial screen pattern of the window Wa, the CPU 1
"0" placed in bit 31 and "1" placed in bit 30 of the data to be transmitted on the PU data bus 4.
Therefore, the output image memory control unit 12 is
The CPU recognizes that the writing operation of the pixel data to the output image data memory 8 is being performed by the CPU, regardless of the control information of the output image control data memory 10.
The pixel data write operation of 1 is executed.

Similarly, in step S3, the CPU 1 displays the display area b forming the window Wb in FIG.
In order to display the initial screen pattern, the pixel data of "pure black" (24-bit pattern of all "0") is written in the word on the output image data memory 8 corresponding to the portion. In this way, the CPU 1 has steps S1 to S3.
By the processing of FIG. 7, the control data is set in the output image control data memory 10 based on the window configuration shown in FIG. 7, the background screen pattern is written in the area not included in any window, and The initial screen pattern is written in the window.

In step S4, the CPU 1 sets the cut-out range and the enlargement / reduction ratio of the input image in the input image signal processing section 7a, and prepares to sequentially discharge the pixel data for one frame. Similarly, for the input image signal processing unit 7b, the input image cropping range and the enlargement / enlargement
A reduction ratio is set, and preparations are made to sequentially discharge pixel data for one frame.

Next, in step S5, the CPU 1 outputs the pixel data sequentially output from the input image signal processing section 7a to one channel of the DMA controller 2,
Parameters such as a transfer source address, a transfer destination address, and the number of transfer words are set in order to perform regular transfer in the rectangular portions of the display areas a and a ′ that form the window Wa in FIG. 7. Thus, the input image signal processing unit 7a
To prepare for discharging pixel data. Similarly,
The CPU 1 regularly supplies the pixel data sequentially discharged from the input image signal processing unit 7b to another channel of the DMA controller 2 in the rectangular areas of the display areas b and a'that configure the window Wb in FIG. Parameters such as a transfer source address, a transfer destination address, and a transfer word number are set in order to perform the transfer. This prepares for discharge of pixel data from the input image signal processing unit 7b. Then, in step S6, the CPU 1 activates the two channels of the DMA controller 2 initialized in step S5.

In step S7, the DAM controller 2
Then, the pixel data transfer operation is performed. That is, the input image signal processing units 7a and 7b have the above-mentioned step S4.
The pixel data generated from one frame of the input image is continuously discharged according to the cutout range of the input image and the enlargement / reduction ratio set by the CPU 1. And
The DMA controller 2 writes the pixel data for one frame discharged from the input image signal processing units 7 a and 7 b into a predetermined rectangular portion on the output image data memory 8.

From the input image signal processing units 7a and 7b,
When the transfer of one frame of pixel data to the output image data memory 8 is completed, the CPU 1 checks in step S8 whether or not the system operator has changed the window configuration. If it is determined in step S8 that there is no change in the window configuration, the process proceeds to step S5, and the window Wa and the window Wb are changed.
The DMA controller 2 is operated to display the next one frame of. However, if it is determined in step S8 that the window configuration has changed, step S8
Returning to 1, according to the new window structure, the control data is reset to the word in the output image control memory 10 corresponding to the pixel having the change in the window structure.

Next, in step S8 of FIG. 11, the control procedure when the window configuration is requested to be changed from that shown in FIG. 7 to that shown in FIG. 9 will be described. In the window configuration shown in FIG. 9, the sizes and positions of the windows Wa and Wb are not changed as compared with the window configuration shown in FIG. 7, and only the overlapping state is changed. Further, in the window configuration shown in FIG. 7, the active window is Wa, and part of the window Wb (display area a ′) is hidden by the window Wa. In the window configuration shown in FIG. 9, conversely, the active window is Wb, and part of the window Wa (display area a ′) is hidden by the window Wb.

Therefore, the change from the window structure shown in FIG. 7 to the window structure shown in FIG. 9 is performed by inputting what is displayed in the display area a'which is an overlapping portion of two windows (Wa, Wb). It suffices to change the pixel data generated by the image processing unit 7a to the pixel data generated by the input image processing unit 7b. So CPU1
Is the output image control data memory 1 corresponding to the pixel whose window configuration has changed in step S1 of FIG.
Reset the control data for the word on 0. In this example, as a result, the control data is rewritten in the word of the output image control data memory 10 corresponding to the pixel forming the display area a ′. Specifically, the control data of the display area a ′ is changed from “0001” to “0010” as shown in FIGS. 8 and 10.

By doing so, only the pixel data generated by the input image processing unit 7b is permitted to be written in the display area a'instead of the pixel data generated by the input image processing unit 7a. Become. And then C
The output image having the window configuration shown in FIG. 9 is obtained by the PU 1 executing the control of steps S2 to S7.

Next, according to the flow chart shown in FIG. 12, in the image processing system according to the embodiment of the present invention,
The control procedure in the output image memory control unit 12 and the pixel data write determination unit 19 will be described. Step S of FIG.
At 11, the output image memory control unit 12 waits for writing by the CPU 1 or the DMA controller 2 to the output image data memory 8 or the output image control data memory 10. The writing of data to the output image data memory 8 or the output image control data memory 10 indicates that the address for the memory has been discharged onto the CPU address bus 3 and the writing on the CPU control bus 5. It can be detected because the control signal is in the active state.

In step S11, the CPU 1 or DM
When the writing of data to the memory by the A controller 2 is detected, the process proceeds to step S12, where the source of pixel data is the CPU 1 or the input image signal processing unit 7 on the CPU data bus 4. It is identified by the bit 31 of the data that has been discharged. That is, FIG. 2, FIG.
As shown in FIG. 6, when the CPU 1 writes pixel data or control data, “0” is placed in the bit 31, and when the input image signal processing unit 7 writes pixel data, “1” is placed. Therefore, the output image memory control unit 12
Thereby, the emission source of the pixel data can be easily identified.

Therefore, when the input image signal processing section 7 is identified as the pixel data discharge source in step S12 (bit 31 = "1"), the processing is stopped in step S13.
Move to. In step S13, the output image memory control unit 12 reads control data from the word in the output image control data memory 10 corresponding to the word in the output image data memory 8 to which the pixel data is written.
As shown in FIG. 3, the read control data indicates whether or not each input image signal processing unit (7a, 7b, 7c, 7d) is permitted to write pixel data to the pixel (word). Is represented.

Next, in step S14, the pixel data write determination unit 19 determines whether the input image signal processing unit (7a, 7b, 7c, 7d) is to use the bits 29 to 28 of the data discharged to the CPU data bus 4. Identify. That is, as shown in FIG. 2, the input image signal processing unit (7a,
7b, 7c, 7d), when writing pixel data, the input image signal identifier encoded by 2 bits is arranged in bits 29 to 28 of the data to be discharged. Therefore, the pixel data writing determination unit 19 can easily identify from which input image signal processing unit (7a, 7b, 7c, 7d) the pixel data is currently discharged.

In the subsequent step S15, the pixel data write determination unit 19 allows the input image signal processing unit 7 which is currently discharging pixel data to write to the target word in the output image data memory 8. Determine whether or not. Here, the control data read onto the output image control data bus 11 in step S13,
Based on the identification result in step S14, the input image signal processing unit 7 which is currently discharging pixel data determines whether or not writing to the target word in the output image memory 8 is permitted.

If it is determined in step S15 that writing is permitted, the process proceeds to step S16, and the pixel data actually discharged by the input image signal processing section 7 is converted into the target output image data. Write to a word on memory 8. This completes the transfer operation of the pixel data from the input image signal processing unit 7 to the output image data memory 8 by the DMA controller 2, and therefore the process returns to step S11 to wait for writing to the next output image memory.

On the other hand, if it is determined in step S15 that the writing is prohibited, the DMA controller 2 forcibly moves the input image signal processing section 7 to the output image data memory 8 by the currently executed DMA controller 2. The pixel data transfer operation is completed and the process is returned to step S11 to wait for writing to the next output image memory. Also,
In step S12, the pixel data discharge source is the CPU1.
If it is identified (bit 31 = "0"), the process proceeds to step S17. Here, the output image memory control unit 12 identifies whether the image memory to be written by the CPU 1 is the output image data memory 8 or the output image control data memory 10 by the bit 30 of the data discharged to the CPU data bus 4. To do. That is, as shown in FIGS. 5 and 6, when the CPU 1 writes the pixel data in the output image data memory 8, the bit 30 is set to “1”,
Further, since "0" is placed when the control data is written in the output image control data memory 10, the output image memory control unit 12 can easily identify the image memory to be written.

If it is determined in step S17 that the CPU 1 writes the pixel data in the output image data memory 8 (bit 30 = "1"), the process proceeds to step S17.
18, the output image memory control unit 12 writes the pixel data actually discharged by the CPU 1 into a word on the target output image data memory 8. This is the CPU
Since the writing operation of the pixel data on the output image data memory 8 by 1 is completed, the process is restarted at step S11.
To wait for writing to the next output image memory.

However, in step S17, the CPU
If it is determined that 1 is to write the control data in the output image control data memory 10 (bit 30 = "0"), the output image memory control unit 12 determines in step S19 that the control data actually discharged by the CPU 1 is output. Is written into the word on the desired output image control data memory 10. In this process, the output image control data memory 10 by the CPU 1
Since the operation of writing the control data to the upper side is completed, the process returns to step S11 again and waits for writing to the next output image memory.

As described above, according to this embodiment,
By controlling the control information for the hierarchical display of a plurality of windows for each pixel forming the output image by the hardware called the image memory, the O of the system relating to the display control is controlled.
This has the effect of reducing the load on S and increasing the display speed. In addition, high-speed expansion of the initial screen pattern of the window and superimposition on the moving screen can be realized. The present invention may be applied to a system including a plurality of devices or an apparatus including a single device.

[0057]

As described above, according to the present invention,
As a control for the hierarchical display of a plurality of windows, there is an effect that high-speed image development can be realized by managing the writing control of the output image by hardware.

[Brief description of drawings]

FIG. 1 is a block diagram showing the overall configuration of an image processing system according to an embodiment of the present invention,

FIG. 2 shows bits of data discharged from the input image signal processing unit 7 or the CPU 1 onto the CPU / data bus 4.
Figure showing the format,

FIG. 3 shows bits of control data of the system according to the embodiment.
Figure showing the format,

FIG. 4 is a diagram showing a bit format of data read by the CPU 1 from the output image data memory 8 and the output image control data memory 10.

5 is a diagram showing a bit format of data to be discharged onto the CPU data bus 4 when the CPU 1 writes pixel data in the output image data memory 8. FIG.

FIG. 6 is a diagram showing a bit format of data to be discharged onto the CPU data bus 4 when the CPU 1 writes control data in the output image control data memory 10.

FIG. 7 is a diagram showing an example of split display of a screen in the image processing system according to the embodiment,

8 is a diagram showing the contents of the output image control data memory 10 corresponding to the display area in the split display example shown in FIG.

FIG. 9 is a diagram showing another example of split display of a screen in the image processing system according to the embodiment,

10 is a diagram showing the contents of the output image control data memory 10 corresponding to the display area in the split display example shown in FIG.

FIG. 11 is a CP in the image processing system according to the embodiment.
U1 and a flow chart showing control by the DMA controller 2,

FIG. 12 is a flow chart showing control by the output image memory control unit 12 and the pixel data write determination unit 19 in the image processing system according to the embodiment.

[Explanation of symbols]

 1 CPU 2 DMA Controller 3 CPU Address Bus 4 CPU Data Bus 5 CPU Control Bus 6 Input Image Signal Line 7 Input Image Signal Processor 8 Output Image Data Memory 9 Output Image Data Bus 10 Output Image Control Data Memory 11 Output image control data bus 12 Output image memory control unit 13 Output image data memory address bus 14 Output image data / memory control bus 15 Output image control data / memory control bus 16 Display device synchronization unit 17 Output image signal line 18 display device synchronization signal 19 image data write determination unit 20 pixel data write enable signal

Claims (6)

[Claims] 1. A memory for dividing and displaying a plurality of image information from a plurality of independent input image signal sources on a single screen is provided, and in the divided display, a part or all of the image information is other. In an image processing system that performs divided display so as to overlap the image information of No. 1, according to the divided display configuration of the image information on the screen, first information creation for creating information indicating the correspondence between the divided display configuration and the input image signal source Means, a control means for controlling the output of the image information from the input image signal source according to the information, and an instruction to write the image information to the memory based on the divided display configuration of the image information on the screen. Second information creating means for creating information, and image information output under the control of the control means are stored in the memory according to the instruction information created by the second information creating means. The image processing system characterized in that it comprises a means for opening. 2. The image information writing instruction information by the second information creating means includes correspondence information between the specific information of each pixel forming the image information and the specific element forming the memory. The image processing system according to claim 1. 3. The image processing system according to claim 2, wherein the specific information of each pixel is color information. 4. An image processing for displaying a plurality of image information from a plurality of independent input image signal sources, the display memory for displaying the plurality of image information on a single screen in a divided manner. In the system, according to a split display configuration of image information on a screen, first information creating means for creating information indicating a correspondence between the split display configuration and an input image signal source, and the input image signal source according to the information. A control means for controlling the output of the image information from the display device, based on the divided display configuration of the image information on the screen, specific information of each pixel forming the image information, and a specific element forming the display memory. Second information creating means for creating writing instruction information of image information including correspondence, and image information output under the control of the control means is changed to instruction information created by the second information creating means. Connexion, the image processing system characterized by comprising a means for developing the display memory. 5. The image processing system according to claim 4, wherein the specific information of each pixel is color information. 6. An image processing method for displaying a plurality of image information from a plurality of independent input image signal sources on a single screen so that the image information overlaps with other image information. A first information creating step of creating information indicating the correspondence between the display structure and the input image signal source according to the display structure of the image information on the screen, and the image information from the input image signal source according to the information And a second information creating step of creating instruction information for writing the image information into the memory based on the display configuration of the image information on the screen, and the control by the controlling step. And a step of expanding the output image information on the memory according to the instruction information created in the second information creating step.